I_0_2_FN_SYSTEM_RESET reboot_mode:0 cmd:(null)
> bl31 reboot reason: 0xd
> bl31 reboot reason: 0x0
> system cmd 1.
> ...REBOOT...
>
> Tested: on VIM1 VIM2 VIM3 VIM3L khadas sbcs - 1000+ successful reboots
> and Odroid boards, WeTek Play2 (GXBB)
>
&
Hi Neil,
Neil Armstrong writes:
> On 02/03/2021 05:22, Artem Lapkin wrote:
>> Problem: random stucks on reboot stage about 1/20 stuck/reboots
>> // debug kernel log
>> [4.496660] reboot: kernel restart prepare CMD:(null)
>> [4.498114] meson_ee_pwrc c883c000.system-controller:power-contro
Neil Armstrong writes:
> On 09/03/2021 18:13, Kevin Hilman wrote:
>> Hi Neil,
>>
>> Neil Armstrong writes:
>>
>>> On 02/03/2021 05:22, Artem Lapkin wrote:
>>>> Problem: random stucks on reboot stage about 1/20 stuck/reboots
>>>> //
Jitao Shi writes:
> "auo,kd101n80-45na" 2st LCD SPEC update, need to modify the timing
> between IOVCC and mipi data.
> The 2st version of SPEC modifies the timing requirements from IOVCC to
> Mipi Data. IOVCC is now required to take precedence over MIPI DATA,
> otherwise there is a risk of leaka
Neil Armstrong writes:
> On 13/03/2019 15:10, Neil Armstrong wrote:
>> This patchset adds the G12A specific bindings for the Display VPU
>> and VPU Power Control.
>>
>> The Amlogic Meson G12A Display module is based on the Meson GXM SoC
>> with an updated Plane Blender, thus VPU architecture and
Neil Armstrong writes:
> On 08/12/2018 18:12, Martin Blumenstingl wrote:
>> This series adds support for the Mali-450 GPU on Meson8 and Meson8b.
>> Meson6 uses a Mali-400 GPU but since we don't have a clock driver (and
>> I don't have a device for testing) Meson6 is left out in this series.
>>
>
0x65771290);
> + }
> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x5554);
> } else {
Reviewed-by: K
Neil Armstrong writes:
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
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Neil Armstrong writes:
> Add missing XBGR & ABGR formats variants from the primary plane.
>
> Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
_
Neil Armstrong writes:
> Add immutable zpos property to primary and overlay planes to specify
> the current fixed zpos position.
>
> Fixes: f9a2348196d1 ("drm/meson: Support Overlay plane for video rendering")
> Signed-off-by: Neil Armstrong
s and switch
> to the Common Clock framework for clocks handling in the future.
>
> When 420 is needed, it calls drm_bridge_format_set() for notify the
> bridge the input format has changed to YUV420.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
with a couple v
out_format = MEDIA_BUS_FMT_YUV8_1X24;
> + specify_out_format = true;
> + }
> + }
> +
> + /* Set a connector bus format if required */
> + drm_display_info_set_bus_formats(info, &out_format,
> +
pdate & disable callbacks.
>
> Fixes: 490f50c109d1 ("drm/meson: Add G12A support for OSD1 Plane")
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
."
> Fix this by disabling the OSD1 plane in the blender registers, and also
> enabling it back using the same register.
>
> Fixes: 490f50c109d1 ("drm/meson: Add G12A support for OSD1 Plane")
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
As noted
Julien Masson writes:
> This patch add new macros which are used to set the following
> registers:
> - VPP_OSD_SCALE_COEF_IDX
> - VPP_DOLBY_CTRL
> - VPP_OFIFO_SIZE
> - VPP_HOLD_LINES
> - VPP_SC_MISC
> - VPP_VADJ_CTRL
>
> Signed-off-by: Julien Masson
[...]
> @@ -97,20 +97,22 @@ void meson_vpp_i
Julien Masson writes:
> This patch add new macro HHI_HDMI_PLL_CNTL_EN which is used to enable
> HDMI PLL.
>
> Signed-off-by: Julien Masson
> ---
> drivers/gpu/drm/meson/meson_vclk.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/meson/meson_vclk.c
>
Julien Masson writes:
> This patch series aims to clean-up differents parts of the drm meson
> code source.
>
> Couple macros have been defined and used to set several registers
> instead of using magic constants.
>
> I also took the opportunity to:
> - add/remove/update comments
> - remove usele
Neil Armstrong writes:
> On 15/03/2019 14:56, Neil Armstrong wrote:
>> This patchset adds :
>> - Optional reset properties in the midgard bindings
>> - Mali T820 Node in Amlogic Meson GXM DTSI
>>
>> Changes since v1:
>> - Updated midgard DT wording following the recently submitted
>> bifrost
Hi Obed,
Oded Gabbay writes:
[...]
> I want to update that I'm currently in discussions with Dave to figure
> out what's the best way to move forward. We are writing it down to do
> a proper comparison between the two paths (new accel subsystem or
> using drm). I guess it will take a week or so
Hi Oded (and sorry I misspelled your name last time),
Oded Gabbay writes:
> On Tue, Aug 23, 2022 at 9:24 PM Kevin Hilman wrote:
>>
>> Hi Obed,
>>
>> Oded Gabbay writes:
>>
>> [...]
>>
>> > I want to update that I'm currently in disc
;s expected to work as-is on GXM and G12B SoCs.
Tested on meson-sm1-sei610 with 4k@60p (VP9) streams.
Tested-by: Kevin Hilman
Kevin
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From: Kevin Hilman
On some SoCs, the VPU is in a power-domain and needs runtime PM
enabled and used in order to keep the power domain on.
Signed-off-by: Kevin Hilman
---
drivers/gpu/drm/meson/meson_drv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_drv.c
setup")
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
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Neil Armstrong writes:
> Hi Kevin,
>
> On 25/09/2019 21:31, Kevin Hilman wrote:
>> From: Kevin Hilman
>>
>> On some SoCs, the VPU is in a power-domain and needs runtime PM
>> enabled and used in order to keep the power domain on.
>>
>> Signed-off
t; - Added a define for the RDMA descriptor size
> - Fixed overflow detection
Reviewed-by: Kevin Hilman
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visual glitches.
>
> Signed-off-by: Neil Armstrong
otherwise...
Reviewed-by: Kevin Hilman
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lin Android Mali blobs found at [1].
>
> Both SoCs has been tested using buffers generated under AOSP, but only
> G12A was tested using a runtime stream of AFBC buffers, GXM was only
> tested using static buffers loaded from files.
Reviewed-by: Kevin Hilman
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his serie has been tested on Amlogic G12A based SEI510 board, using
> the newly accepted VRTC driver and the rtcwake utility.
Tested-by: Kevin Hilman
Tested on my G12A SEI510 board, and I verified that it fixes
suspend/resume issues previously seen.
Kevin
Neil Armstrong writes:
> On 27/08/2019 21:17, Kevin Hilman wrote:
>> Neil Armstrong writes:
>>
>>> This serie adds the resume/suspend hooks in the Amlogic Meson VPU main
>>> driver
>>> and the DW-HDMI Glue driver to correctly save state and disable
tely unused, so I'm only leaving omap15xx/omap16xx/omap59xx.
Acked-by: Kevin Hilman
with a few tears shed since omap7xx/omap8xx was the first family I
contributed to upstream. :(
Kevin
Jeffrey Hugo writes:
> On 5/17/2023 8:52 AM, Alexandre Bailon wrote:
>> This adds a DRM driver that implements communication between the CPU and an
>> APU. The driver target embedded device that usually run inference using some
>> prebuilt models. The goal is to provide common infrastructure that
Neil Armstrong writes:
> Hi Laurent,
> On 11/30/2016 04:58 PM, Laurent Pinchart wrote:
>> Hi Neil,
>>
>> On Wednesday 30 Nov 2016 16:43:44 Neil Armstrong wrote:
>>> Signed-off-by: Neil Armstrong
>>> ---
>>> .../bindings/display/meson/meson-drm.txt | 101 ++
>>
>> I fo
Bartosz Golaszewski writes:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski
[...]
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> ne
Bartosz Golaszewski writes:
> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
>
> Signed-off-by: Bartosz Golaszewski
[...]
> +#define DA8XX_IO_PHYS0x01c0ul
> +#define DA8XX_SYSCFG0_BASE
+Arnd, Olof
Laurent Pinchart writes:
> Hi Bartosz,
>
> On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >> Create the driver for the da8xx System Configuration and implem
Hi Laurent,
Laurent Pinchart writes:
> On Thursday 20 Oct 2016 09:57:51 Kevin Hilman wrote:
>> Laurent Pinchart writes:
>> > On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> >> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> >>> On Mo
Neil Armstrong writes:
> On 03/21/2017 04:25 PM, Neil Armstrong wrote:
>> The HDMI modes needs more CMA memory to be reserved at boot-time.
>>
>> Signed-off-by: Neil Armstrong
[...]
> Hi Kevin,
>
> Please take this one for the amlogic arm-soc DT tree.
>
Applied to v4.12/dt64,
Kevin
Neil Armstrong writes:
> On 03/21/2017 04:25 PM, Neil Armstrong wrote:
>> Add HDMI output and connector nodes.
>>
>> Signed-off-by: Neil Armstrong
[...]
>
> Hi Kevin,
>
> Please take this one for the amlogic arm-soc DT tree.
>
Applied to v4.12/dt64,
Kevin
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Bartosz Golaszewski writes:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski
Reviewed-by: Kevin Hilman
Bartosz Golaszewski writes:
> Create the driver for the da8xx master peripheral priority
> configuration and implement support for writing to the three
> Master Priority registers on da850 SoCs.
>
> Signed-off-by: Bartosz Golaszewski
Reviewed-by: Kevin Hilman
David Lechner writes:
> On 11/23/2016 04:27 AM, Bartosz Golaszewski wrote:
>> 2016-11-22 23:23 GMT+01:00 David Lechner :
>>> On 11/15/2016 05:00 AM, Bartosz Golaszewski wrote:
Add the nodes for the MSTPRI configuration and DDR2/mDDR memory
controller drivers to da850.dtsi.
>>>
On Wed, Nov 23, 2016 at 9:03 PM, Sekhar Nori wrote:
> On Thursday 24 November 2016 04:18 AM, David Lechner wrote:
>> On 11/23/2016 04:32 PM, Kevin Hilman wrote:
>>> David Lechner writes:
>>>
>>>> On 11/23/2016 04:27 AM, Bartosz Golaszewski wrote:
>>
Hi Mark,
Mark Rutland writes:
> On Mon, Oct 24, 2016 at 06:46:36PM +0200, Bartosz Golaszewski wrote:
>> Create a new driver for the da8xx DDR2/mDDR controller and implement
>> support for writing to the Peripheral Bus Burst Priority Register.
>>
>> Signed-off-by: Bartosz Golaszewski
>> ---
>>
Mark Rutland writes:
> On Mon, Oct 24, 2016 at 10:35:30AM -0700, Kevin Hilman wrote:
>> Hi Mark,
>>
>> Mark Rutland writes:
>> > On Mon, Oct 24, 2016 at 06:46:36PM +0200, Bartosz Golaszewski wrote:
>> >> +static int da8xx_ddrctl_probe(struct platform_d
On Mon, Oct 24, 2016 at 11:41 AM, Kevin Hilman wrote:
> Mark Rutland writes:
>
>> On Mon, Oct 24, 2016 at 10:35:30AM -0700, Kevin Hilman wrote:
>>> Hi Mark,
>>>
>>> Mark Rutland writes:
>>> > On Mon, Oct 24, 2016 at 06:46:36PM +
Bartosz Golaszewski writes:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski
> ---
> .../memory-controllers/ti-da8xx-ddrctl.txt | 20 +++
> drivers/memory/K
Kevin Hilman writes:
> Bartosz Golaszewski writes:
>
>> Create a new driver for the da8xx DDR2/mDDR controller and implement
>> support for writing to the Peripheral Bus Burst Priority Register.
>>
>> Signed-off-by: Bartosz Golaszewski
>> ---
>>
< knob->shift;
> +
> + dev_dbg(dev, "writing 0x%08x to %s\n", reg, setting->name);
> +
> + __raw_writel(reg, ddrctl + knob->reg);
Can you use the normal readl/writel here? Or explain why the raw ones
are needed?
> + }
> +
> + return 0;
> +}
> +
Otherwise, looks good to me. With the changes above, feel free to add
Reviewed-by: Kevin Hilman
Kevin
Sekhar Nori writes:
> On Monday 31 October 2016 03:24 PM, Bartosz Golaszewski wrote:
>> 2016-10-31 10:52 GMT+01:00 Sekhar Nori :
>>> Hi Bartosz,
>>>
>>> On Monday 31 October 2016 03:10 PM, Bartosz Golaszewski wrote:
2016-10-31 5:30 GMT+01:00 Rob Herring :
> On Wed, Oct 26, 2016 at 07:35:
Laurent Pinchart writes:
> Hi Bartosz,
>
> Thank you for the patch.
>
> On Monday 31 Oct 2016 15:45:37 Bartosz Golaszewski wrote:
>> Enable the MSTPRI configuration and DDR2/mDDR memory controller
>> nodes on da850-lcdk. This is needed in order to adjust the memory
>> throughput constraints for b
Ulf Hansson writes:
> On 11 May 2016 at 23:25, Rafael J. Wysocki wrote:
>> On Wed, May 11, 2016 at 10:00 AM, Ulf Hansson
>> wrote:
>>> If the PM domain is powered off when the first device in the domain starts
>>> its system PM prepare phase, genpd prevents any further attempts to power
>>> on
aving on GXL) and 10bit
> (Scatter on G12A/SM1, default on GXL).
>
> It's expected to work as-is on GXM and G12B SoCs.
Reviewed-by: Kevin Hilman
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em Saving on GXL) and 10bit
> (Scatter on G12A/SM1, default on GXL).
Tested on meson-sm1-sei610 (VP9 60fps content).
Tested-by: Kevin Hilman
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e fix removes the usage of genpd's internal
> suspend_power_off flag as it's not needed after this change. Because of
> this change I am also requesting an ack from the drm driver maintainer.
>
>
> ---
> drivers/base/power/domain.c | 84
>
at the driver level. For
> example, genpd's ->restore() callback invokes pm_generic_resume(), while
> it should be pm_generic_restore(). Let's fix this as well.
>
> Signed-off-by: Ulf Hansson
Reviewed-by: Kevin Hilman
Acked-by: Kevin Hilman
Kevin
Andrzej Hajda writes:
> On 10/30/2014 08:36 AM, Krzysztof Kozlowski wrote:
>> On Åro, 2014-10-29 at 10:46 -0700, Kevin Hilman wrote:
>>> Krzysztof Kozlowski writes:
>>>
>>>> When resuming the system the power domain has to be powered on early so
>>
Fix this by moving the platform
> drivers registration to exynos_drm_init().
>
> Suggested-by: Andrzej Hajda
> Signed-off-by: Javier Martinez Canillas
> ---
>
> This issue was reported by both Krzysztof Kozlowski [0] and Kevin Hilman [1].
>
> Inki Dae said that he will fix
Gustavo Padovan writes:
> 2014-11-18 Kevin Hilman :
>
>> Javier Martinez Canillas writes:
>>
>> > The Exynos DRM driver register its sub-devices platform drivers in
>> > the probe function but after commit 43c0767 ("of/platform: Move
>> > platf
Javier Martinez Canillas writes:
> [adding Paolo and Vivek as cc]
>
> Hello,
>
> On 11/18/2014 07:41 PM, Kevin Hilman wrote:
>>
>> It fixes the DRM deadlock, issue for me on exynos5800-peach-pi, but then
>> it proceeds to panic in the workqueue code calle
Paolo Pisati writes:
> On Wed, Nov 19, 2014 at 10:35:40AM +0100, Javier Martinez Canillas wrote:
>> Hello Ajay,
>>
>> On 11/18/2014 07:20 AM, Ajay kumar wrote:
>> > On Sat, Nov 15, 2014 at 3:24 PM, Ajay Kumar
>> > wrote:
>> >> This series is based on master branch of Linus tree at:
>> >> git:/
Kevin Hilman writes:
> Javier Martinez Canillas writes:
>
>> [adding Paolo and Vivek as cc]
>>
>> Hello,
>>
>> On 11/18/2014 07:41 PM, Kevin Hilman wrote:
>>>
>>> It fixes the DRM deadlock, issue for me on exynos5800-peach-pi, but then
&g
Hi Jyri,
Jyri Sarha writes:
> On 08/23/16 15:56, Karl Beldan wrote:
>> Hi,
>>
>> I found some missing bits for rev1 of the LCDC and here are some of the
>> changes I am using to use the DRM driver on an LCDCK (which has a rev1).
>> 1/3 seems required by rev1 of the IP and without it my the LCDC
Krzysztof Kozlowski writes:
> When resuming the system the power domain has to be powered on early so
> any runtime PM aware devices could resume.
>
> This fixes following scenario reproduced on Exynos DRM:
> 1. Power domain is off before suspending the system.
> 2. System is suspended to RAM.
>
Neil Armstrong writes:
> This patchset adds :
> - Optional reset properties in the midgard bindings
> - Mali T820 Node in Amlogic Meson GXM DTSI
>
> Christian Hewitt (1):
> arm64: dts: meson-gxm: Add Mali-T820 node
>
> Neil Armstrong (1):
> dt-bindings: gpu: mali-midgard: Add resets property
Krzysztof Kozlowski writes:
> After adding display power domain for Exynos5250 in commit
> 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") the
> display on Chromebook Snow and others stopped working after boot.
>
> The reason for this suggested Andrzej Hajda: the DP clock was d
Krzysztof Kozlowski writes:
> 2015-04-30 2:31 GMT+09:00 Kevin Hilman :
>> Krzysztof Kozlowski writes:
>>
>>> After adding display power domain for Exynos5250 in commit
>>> 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") the
>&g
Hi Vivek,
Vivek Gautam writes:
[...]
> I tested linux-next on Exynos5800 peach-pi board with linux-next and and the
> two
> patches $Subject and [0].
>
> Below is my git hash:
> 4d9e6ee drm/exynos: Move platform drivers registration to module init
> 4545ed4 POSTED: arm: dts: Exynos5: Use pmu_s
Javier Martinez Canillas writes:
> Hello,
>
> For completeness I'll comment what we talked with Kevin on IRC
> since probably this is the same issue that Paolo is facing.
>
> On 11/20/2014 05:41 PM, Kevin Hilman wrote:
>> Peach # setenv preboot "usb start; sleep
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