This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers
Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath
for SC7180 target")
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13
drivers/gpu/drm/msm/disp/dpu1/dpu_h
This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation
is not supported on the newest DPU versions. (note that decimation is not
implemented, so this changes nothing)
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 14 +--
.../gpu/dr
init has been called, the icc path
init needs to be after msm_gpu_init for the error path to work.
v2: changed to not only check for EPROBE_DEFER
v3: move icc path init after msm_gpu_init to avoid deleting a WARN_ON
v4: added two patches to fix issues with probe deferring later in v3
Jonathan Marek
Initialize hardware clock-gating registers on A640 and A650 GPUs.
At least for A650, this solves some performance issues.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 117 -
drivers/gpu
These patches bring up SM8150 and SM8250 with basic functionality.
Tested with displayport output (single mixer, video mode case).
v2: rebased
Jonathan Marek (8):
drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250
drm/msm/dpu: update UBWC config for sm8150 and sm8250
drm/msm
This brings up basic video mode functionality for SM8250 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1
adreno_gpu_init calls pm_runtime_enable, so adreno_gpu_cleanup needs to
call pm_runtime_disable.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno
init has been called, the icc path
init needs to be after msm_gpu_init for the error path to work.
v2: changed to not only check for EPROBE_DEFER
v3: move icc path init after msm_gpu_init to avoid deleting a WARN_ON
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adre
This brings up basic video mode functionality for SM8150 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1
is
used in the upstream driver.
Also simplifies the overly complicated change that was introduced in
e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 --
.../gpu/drm/msm/disp/dpu1/dpu_hw_ca
These never get set back to 0 when probing fails, so an attempt to probe
again results in broken behavior. Fix the problem by setting thse to zero
before they are used.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gpu.c | 4
1 file changed, 4 insertions(+)
diff --git a
On 7/9/20 11:15 AM, Rob Clark wrote:
On Thu, Jul 9, 2020 at 7:35 AM Jonathan Marek wrote:
Check for errors instead of silently not using icc if the msm driver
probes before the interconnect driver.
Allow ENODATA for ocmem path, as it is optional and this error
is returned when "gfx-mem&
On 7/13/20 11:24 AM, Georgi Djakov wrote:
On 7/1/20 07:25, Jonathan Marek wrote:
The a6xx GMU can vote for ddr and cnoc bandwidth, but it needs to be able
to query the interconnect driver for bcm addresses and commands.
It's not very clear to me how the GMU firmware would be dealing with
init has been called, the icc path
init needs to be after msm_gpu_init for the error path to work.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 65 +++--
1 file changed, 38 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adr
On 7/15/20 2:29 PM, Rob Clark wrote:
From: Rob Clark
If there is no interconnect-names, but there is an interconnects
property, then of_icc_get(dev, "gfx-mem"); would return an error
rather than NULL.
Also, if there is no interconnect-names property, there will never
be a ocmem path. But of_i
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 68 ---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 117 --
drivers/gpu/drm/msm/adreno
Some of the RSCC registers on A650 are in a separate region.
Note this also changes the address of these registers:
RSCC_TCS1_DRV0_STATUS
RSCC_TCS2_DRV0_STATUS
RSCC_TCS3_DRV0_STATUS
Based on the values in msm-4.14 and msm-4.19 kernels.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 748cd379065f..c6ecb3189ec5 100644
--- a/drivers/gpu/drm
On 4/20/20 3:51 PM, Bjorn Andersson wrote:
On Mon 20 Apr 07:03 PDT 2020, Jonathan Marek wrote:
This reverts commit a5fb8b918920c6f7706a8b5b8ea535a7f077a7f6.
Why?
It removes something I need for the next patches in the series, however
I'm open to suggestions on a better solution (J
This is required for a650 to work.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4
3 files changed, 21 insertions(+)
diff --git a/drivers
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 10 +
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 3e51939eb867..b583bf6e293b 100644
--- a
Adreno 640 and 650 GPUs need some registers set differently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++-
2 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu
Newer GPUs have different gmu firmware path.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 136 +++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 6 +
3 files changed, 138 insertions(+), 15
This reverts commit a5fb8b918920c6f7706a8b5b8ea535a7f077a7f6.
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 +++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 +-
2 files changed, 107 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drive
This is required for a650 to work.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4
3 files changed, 20 insertions(+)
diff --git a/drivers/gpu
This gives more fine-grained control over how memory is allocated over the
DMA api. In particular, it allows using an address range or pinning to
a fixed address.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ++
drivers/gpu/drm/msm/adreno
This flag sets IOMMU_PRIV, which is required for some a6xx GMU objects.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 3 +++
drivers/gpu/drm/msm/msm_gem.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
This function allows pinning iova to a specific page range (for a6xx GMU).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.h | 6 +-
drivers/gpu/drm/msm/msm_gem.c | 28 +---
drivers/gpu/drm/msm/msm_gem_vma.c | 6 --
3 files changed, 30
Adreno 640 and 650 GPUs need some registers set differently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++-
2 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu
Add HFI v2 code paths required by Adreno 640 and 650 GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 66 ---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 117
Newer GPUs have different GMU firmware path.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 135 +++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 6 +
3 files changed, 136 insertions(+), 16
On 4/21/20 12:30 PM, Jordan Crouse wrote:
On Mon, Apr 20, 2020 at 10:03:08AM -0400, Jonathan Marek wrote:
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 68 ---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 90 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 38 +-
3 files changed, 85 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm
Add Adreno 640 and 650 GPU info to the gpulist.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 10 +
3 files changed, 35 insertions
Newer GPUs have different GMU firmware path.
v3: updated a6xx_gmu_fw_load based on feedback, including gmu_write_bulk,
and removed extra whitespace change
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 138 +++---
drivers/gpu/drm/msm/adreno
This function allows pinning iova to a specific page range (for a6xx GMU).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.h | 6 +-
drivers/gpu/drm/msm/msm_gem.c | 28 +---
drivers/gpu/drm/msm/msm_gem_vma.c | 6 --
3 files changed, 30
: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 90 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 38 +-
3
This is required for a650 to work.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4
3 files changed, 20 insertions
A650"
Changes in V3:
Updated patches 6 and 7 (see commit logs for details)
Jonathan Marek (9):
drm/msm: add msm_gem_get_and_pin_iova_range
drm/msm: add internal MSM_BO_MAP_PRIV flag
drm/msm/a6xx: use msm_gem for GMU memory objects
drm/msm/a6xx: add A640/A650 to gpulist
drm/msm/a6xx:
Add HFI v2 code paths required by Adreno 640 and 650 GPUs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 66 ---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
drivers/gpu/drm
Add Adreno 640 and 650 GPU info to the gpulist.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 10 +
3
This flag sets IOMMU_PRIV, which is required for some a6xx GMU objects.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gem.c | 3 +++
drivers/gpu/drm/msm/msm_gem.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b
Adreno 640 and 650 GPUs need some registers set differently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++-
2 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu
This gives more fine-grained control over how memory is allocated over the
DMA api. In particular, it allows using an address range or pinning to
a fixed address.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115
On 6/11/20 10:37 AM, Dmitry Baryshkov wrote:
On 26/05/2020 06:22, Jonathan Marek wrote:
This brings up basic video mode functionality for SM8150 DPU. Command
mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is
This will allow supporting different hwcg tables for a6xx.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 129 ++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 111 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 7 ++
3 files
A650 has a separate RSCC region, so dump RSCC registers separately, reading
them from the RSCC base. Without this change a GPU hang will cause a system
reset if CONFIG_DEV_COREDUMP is enabled.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +
drivers/gpu
Initialize hardware clock-gating registers on A640 and A650 GPUs.
At least for A650, this solves some performance issues.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++-
drivers/gpu/drm/msm/adreno
.h in adreno_device.c)
Jonathan Marek (2):
drm/msm/a6xx: hwcg tables in gpulist
drm/msm/a6xx: add A640/A650 hwcg
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 140 ++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 219 +
dr
a6xx driver to
fill out the GMU bw_table (two ddr bandwidth levels in this example, note
this would be using the frequency table in dts and not hardcoded values).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 20 ---
drivers/interconnect/qcom/icc-rpmh.c
been called on the list yet when going through the defer error path.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 ++---
drivers/gpu/drm/msm/msm_gpu.c | 2 --
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/dr
, but use these dummy tables for now.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 74 +++
1 file changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 9921e632f1ca
On 7/1/20 12:56 PM, Jordan Crouse wrote:
On Wed, Jul 01, 2020 at 12:25:25AM -0400, Jonathan Marek wrote:
The a6xx GMU can vote for ddr and cnoc bandwidth, but it needs to be able
to query the interconnect driver for bcm addresses and commands.
I'm not sure what is the best way to go
On 7/1/20 1:12 PM, Matthias Kaehlcke wrote:
Hi Jonathan,
On Tue, Jun 30, 2020 at 11:08:41PM -0400, Jonathan Marek wrote:
Check for EPROBE_DEFER instead of silently not using icc if the msm driver
probes before the interconnect driver.
Agreed with supporting deferred ICC probing.
Only check
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250.
Implementation is based on 10nm driver, but updated based on the downstream
7nm driver.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../devicetree/bindings/display/msm/dsi.t
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config
is re-used as the config is the same.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 5 -
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 ++
2 files changed, 6
Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250.
v2:
- added workaround for 5GHz max_rate overflowing in 32-bit builds
(based on robclark's suggestion)
- Updated Kconfig option to mention SM8250 and not just SM8150
Jonathan Marek (3):
drm/msm/d
ad of time to correctly set the
hw_apriv flag so that it can be used by msm_gpu to properly setup
global buffers.
Fixes: 604234f33658 ("drm/msm: Enable expanded apriv support for a650")
Signed-off-by: Jordan Crouse
Tested-by: Jonathan Marek
---
drivers/gpu/drm/msm/ad
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm/msm_drm.h
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/dr
This is to support cached and cached-coherent memory types in vulkan.
I made a corresponding WIP merge request [1] which shows usage of this.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6949
Jonathan Marek (3):
drm/msm: add MSM_BO_CACHED_COHERENT
drm/msm: add
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 305db1db1064
On 10/2/20 3:53 AM, Christoph Hellwig wrote:
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
NAK, dma-noncoherent.h is not for driver use. And will in fact go
away in 5.10.
Not actually used, so can be removed.
#include
@@ -808,6 +809,20 @@ int msm_gem_cpu_fini(stru
On 10/5/20 4:29 AM, Christoph Hellwig wrote:
On Fri, Oct 02, 2020 at 08:46:35AM -0400, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj
On 10/6/20 3:23 AM, Christoph Hellwig wrote:
On Mon, Oct 05, 2020 at 10:35:43AM -0400, Jonathan Marek wrote:
The cache synchronization doesn't have anything to do with IOMMU (for
example: cache synchronization would be useful in cases where drm/msm
doesn't use IOMMU).
It has to do
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250.
Implementation is based on 10nm driver, but updated based on the downstream
7nm driver.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi.txt | 6 +-
drivers/gpu/drm/m
The clk_pre/clk_post values in shared_timings are used instead, and these
are unused.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config
is re-used as the config is the same.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 5 -
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a
Add support for SM8150 and SM8250 DSI.
Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250.
Jonathan Marek (3):
drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timing
drm/msm/dsi: add DSI config for sm8150 and sm8250
drm/msm/dsi: add support for 7n
The clk_pre/clk_post values in shared_timings are used instead, and these
are unused.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b
event this from happening.
Fixes: 1f60d11423db ("drm: msm: a6xx: send opp instead of a frequency")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/m
The patch reorganizing the set_freq function made it so the gmu resume
doesn't always set the frequency, because a6xx_gmu_set_freq() exits early
when the frequency hasn't been changed. Note this always happens when
resuming GMU after recovering from a hang.
Use a simple workaround to prevent this
On 8/15/20 4:20 PM, Rob Clark wrote:
On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov
wrote:
On 12/08/2020 07:42, Tanmay Shah wrote:
> From: Chandan Uddaraju
>
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
[skipped]
> diff --git a/dri
This fixes changing the frequency in sysfs while suspended, for example
when doing something like this:
cat devfreq/3d0.gpu/max_freq > devfreq/3d0.gpu/min_freq
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +--
1 file changed, 9 insertions(+)
Also skip the newly added HFI set freq path if the GMU is powered down,
which was missing because of patches crossing paths.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu
currently broken for SC7180).
Jonathan Marek (8):
drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250
drm/msm/dpu: update UBWC config for sm8150 and sm8250
drm/msm/dpu: move some sspp caps to dpu_caps
drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845
drm/msm/dpu: set mi
Calculate the correct timings for displayport, from downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers
Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath
for SC7180 target")
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13
drivers/gpu/drm/msm/disp/dpu1/dpu_h
All DPU versions starting from 4.0 use the sdm845 version, so check for
that instead of checking each version individually. This chooses the right
function for sm8150 and sm8250.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 ++---
1 file changed, 2 insertions
This brings up basic video mode functionality for SM8250 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1
is
used in the upstream driver.
Also simplifies the overly complicated change that was introduced in
e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 --
.../gpu/drm/msm/disp/dpu1/dpu_hw_ca
This is required for A640 and A650 to be able to share UBWC-compressed
images with other HW such as display, which expect this configuration.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++-
1 file changed, 32 insertions(+), 6 deletions
This brings up basic video mode functionality for SM8150 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1
This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation
is not supported on the newest DPU versions. (note that decimation is not
implemented, so this changes nothing)
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 14 +--
.../gpu/dr
A2XX has its own very simple MMU.
Added a msm_use_mmu() function because we can't rely on iommu_present to
decide to use MMU or not.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Makefile | 3 +-
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 57 +--
driver
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 4 ++--
drivers/gpu/drm/msm/msm_debugfs.c | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 15 +++
include/linux/qcom_scm.h | 3 +++
4 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers
For allocation in contiguous memory when the GPU has MMU but not mdp4.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index ae25d763cd8c..8f765f284d11 100644
Add the mdp5_cfg_hw entry for MDP5 version v1.15 found on msm8917.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 86
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5
derived from the a3xx driver and tested on the following hardware:
imx51-zii-rdu1 (a200 with 128kb gmem)
imx53-qsrb (a200)
msm8060-tenderloin (a220)
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 445
Controls which of the 8 lanes are used for 6 bit color.
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 22 ---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
b/drivers/gpu/drm
:24:12PM -0500, Jonathan Marek wrote:
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 4 ++--
drivers/gpu/drm/msm/msm_debugfs.c | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 15 +++
include/linux/qcom_scm.h | 3 +++
4 files changed, 17 insertions
otherwise, priv->kms is non-NULL and msm_drm_uninit will cause a panic.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index bda23011494d..94b0593f6090 100644
--
Makes it possible to have MMU for GPU but not display.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index d97f6ecb0531..6657453a3a58 100644
--- a
Controls which of the 8 lanes are used for 6 bit color.
Signed-off-by: Jonathan Marek
---
.../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 22 ---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
b/drivers/gpu/drm
Makes it possible to have MMU for GPU but not display.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index d97f6ecb0531..6657453a3a58 100644
--- a
For allocation in contiguous memory when the GPU has MMU but not mdp4.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4
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