The properties below refer to items in panel-common.yaml, which means
that needs to be referenced in the schema.
Signed-off-by: John Keeping
---
.../devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree
The panel orientation needs to parsed from a device-tree and assigned to
the panel's connector in order to make orientation property available to
userspace. That's what this patch does for ILI9881C based panels.
Signed-off-by: John Keeping
---
drivers/gpu/drm/panel/panel-ilitek-ili98
Support the "rotation" DT property for ILI9881C based panels.
The first patch is a fix for the binding, then the usual binding update
followed by the corresponding driver update.
John Keeping (3):
dt-bindings: ili9881c: add missing panel-common inheritance
dt-bindings: ili9881c: ad
Allow the standard rotation property from panel-common for ILI9881C
based panels.
Signed-off-by: John Keeping
---
.../devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/panel/ilitek
The Rockchip fbdev code does not add anything compared to
drm_fbdev_generic_setup(); the one custom function for .fb_mmap does the
same thing as gem_prime_mmap which is called by the helper.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/Makefile | 1 -
drivers/gpu/drm
Hi Bert,
On Tue, Oct 26, 2021 at 05:18:47PM -0700, Bert Schiettecatte wrote:
> I have an application I'm working on where I'm using OpenGLES / EGL
> and dri/drm/kms. The main loop of my application looks like the code
> below. When running htop, I see that the number of minor faults
> (memory) are
Hi Thomas,
On Fri, Oct 29, 2021 at 09:00:08PM +0200, Thomas Zimmermann wrote:
> Am 29.10.21 um 13:50 schrieb John Keeping:
> > The Rockchip fbdev code does not add anything compared to
> > drm_fbdev_generic_setup(); the one custom function for .fb_mmap does the
> > same th
On Sun, 31 Oct 2021 19:09:39 +0100
Thomas Zimmermann wrote:
> Am 30.10.21 um 14:05 schrieb John Keeping:
> > On Fri, Oct 29, 2021 at 09:00:08PM +0200, Thomas Zimmermann wrote:
> >> Am 29.10.21 um 13:50 schrieb John Keeping:
> >>> The Rockchip fbdev code doe
Allow drm_fbdev_generic_setup() to pick the default bpp value for the
framebuffer.
This has no functional impact because the default is 32, given that
mode_config.preferred_depth is not set for Rockchip.
Suggested-by: Thomas Zimmermann
Signed-off-by: John Keeping
---
This needs [1] to be
Hi Thomas,
On Mon, Nov 01, 2021 at 11:34:15AM +, John Keeping wrote:
> On Sun, 31 Oct 2021 19:09:39 +0100
> Thomas Zimmermann wrote:
> > Am 30.10.21 um 14:05 schrieb John Keeping:
> > > On Fri, Oct 29, 2021 at 09:00:08PM +0200, Thomas Zimmermann wrote:
> > >
, and enable_afbc is always set
in the preceding .atomic_check, so the only issue here is inspecting the
state later when these field end up no longer reflecting what has been
programmed in the hardware.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
1 file
Rockchip VOP subclasses drm_crtc_state so implementing the
atomic_print_state hook allows printing the additional Rockchip-specific
fields of the CRTC state.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 14 ++
1 file changed, 14 insertions(+)
diff
9bff ("drm/rockchip: vop: group vop registers")
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 09a790
Call the necessary function to set add the orientation property when the
connector is created so that it is available before the device is
registered.
Fixes: 15b9ca1641f0 ("drm: Config orientation property if panel provides it")
Signed-off-by: John Keeping
---
drivers/gpu/drm/bridge/panel.c |
Hi Sam & Doug,
On Sat, Jan 21, 2023 at 09:57:18AM +0100, Sam Ravnborg wrote:
> On Fri, Jan 20, 2023 at 01:44:38PM -0800, Doug Anderson wrote:
> > On Fri, Jan 20, 2023 at 3:43 AM John Keeping wrote:
> > >
> > > Commit 15b9ca1641f0 ("drm: Config orientation
Hi Laurent,
On Sun, Jan 22, 2023 at 05:01:27PM +0200, Laurent Pinchart wrote:
> On Sat, Jan 21, 2023 at 05:58:11PM +0000, John Keeping wrote:
> > On Sat, Jan 21, 2023 at 09:57:18AM +0100, Sam Ravnborg wrote:
> > > On Fri, Jan 20, 2023 at 01:44:38PM -0800, Doug Anderson wrote:
&
r7:0000 r6:
> r5:c01491a8
> [7.977144] r4:c200e800 r3:0001
> [7.977155] ---[ end trace ]---
>
> On 10/29/21 13:50, John Keeping wrote:
> > The Rockchip fbdev code does not add anything compared to
> > drm_fbdev_generic_s
On Mon, Oct 17, 2022 at 08:30:23PM +0200, Johan Jonker wrote:
>
>
> On 10/17/22 13:29, Heiko Stuebner wrote:
> > Am Montag, 17. Oktober 2022, 12:05:16 CEST schrieb John Keeping:
> >> Hi Johan,
> >>
> >> On Mon, Oct 17, 2022 at 10:11:32AM +0200, Johan J
sub function
> rockchip_fb_alloc() and cleanup the rockchip_drm_fb.h header file.
>
> Signed-off-by: Johan Jonker
Reviewed-by: John Keeping
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 43 --
> drivers/gpu/drm/rockchip/rockchip_drm_fb.h | 6 ---
&g
: 24af7c34b290 ("drm/rockchip: use generic fbdev setup")
Reported-by: Johan Jonker
Cc: Thomas Zimmermann
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_dr
On Mon, Sep 26, 2022 at 10:37:52PM +0200, Aurelien Jarno wrote:
> When the avdd-0v9 or avdd-1v8 supply are not yet available, EPROBE_DEFER
> is returned by rockchip_hdmi_parse_dt(). This causes the following error
> message to be printed multiple times:
>
> dwhdmi-rockchip fe0a.hdmi: [drm:
If a buffer is allocated with alloc_kmap, then it is vmap'd on creation
and there is no reason to map it again in rockchip_gem_prime_vmap() when
the existing mapping can be used.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 13 ++---
1 file change
Hi Sean,
On Sun, 12 Mar 2017 07:06:59 -0500, Rob Herring wrote:
> On Fri, Mar 03, 2017 at 11:39:45AM +0000, John Keeping wrote:
> > This reset is required in order to fully reset the internal state of the
> > MIPI controller.
> >
> > Signed-off-by: John Keeping
>
The bias, bandgap and PLL should all be configured before we enable
them.
Signed-off-by: John Keeping
---
v3:
- Squash together two patches that both affect initialization order of
the PHY
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++-
1 file changed, 6 insertions
This is not needed since we can access the mode via the CRTC from the
enable hook. Also remove the "mode" field that is no longer used.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
New in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 13 +
When connected to the MIPI DSI output, we need to use N{H,V}SYNC for the
internal connection but these flags are meaningless for DSI panels.
Switch the test so that we do not set the P{H,V}SYNC bits unless the
mode requires it.
Signed-off-by: John Keeping
Reviewed-by: Mark Yao
---
v3:
- Add
With atomic modesetting the hardware will be powered off when the
mode_set function is called. We should configure the hardware in the
enable function, which is the atomic version of "commit" so let's use
the enable hook rather than commit while we're at it.
Signed-off-by:
Also don't power up the DSI host at this point since this is not
necessary in order to configure the PHY and we do so later when
selecting video or command mode.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/r
This clock rate is derived from the PHY PLL, so it should be calculated
dynamically. Use the same calculation as the vendor kernel to derive
the escape clock speed.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Improve the commit message a bit
- Add Chris' Review
We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits
are set so we can't just check "val & mask" because that will be true if
either bit is set.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
dri
in order to
ensure that the PHY configuration is correct.
Signed-off-by: John Keeping
---
v3:
- Wrap some long lines
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
54, N = 4 as given by the databook.
While doing this, change the loop limits to encode the actual limits on
the divisor, which are:
40MHz >= (pllref / N) >= 5MHz
Signed-off-by: John Keeping
---
Unchanged in v3
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
1
As an aid to debugging.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gp
Requesting the HS clock from the PHY before we initialize it causes an
invalid signal to be sent out since the input clock is not yet
configured. The PHY databook suggests only asserting this signal when
performing HS transfers, so let's do that.
Signed-off-by: John Keeping
Reviewed-by:
This re-roll mostly just gather up reviewed-by tags, although I have
also wrapped some long lines and squashed together some commits as
suggested by Chris Zhong.
Version 2 was posted here:
https://www.spinics.net/lists/arm-kernel/msg556683.html
John Keeping (24):
drm/rockchip: dw-mipi-dsi
I haven't found any method for getting the length of a response, so this
just uses the requested rx_len
Signed-off-by: John Keeping
---
v3:
- Fix checkpatch warnings
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 56 ++
1 file changed, 56 inser
Some panels need to be configured with commands sent over the MIPI link,
which they will do in the prepare hook. Call this after the PHY has
been initialized so that we are able to send commands to the panel.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Review
By dereferencing the MIPI command buffer as a u32* we rely on it being
correctly aligned on ARM, but this may not be the case. Copy it into a
stack variable that will be correctly aligned.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged
Instead of always sending commands in LP mode, respect the
MIPI_DSI_MSG_USE_LPM flag to decide how to send each message. Also
request acks if MIPI_DSI_MSG_REQ_ACK is set.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gp
call which seems to be a workaround for a specific panel and
thus belongs in the panel driver.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 12 ++--
1 file changed, 2 insertions(+
This ensures that the output resolution is known before fbcon loads.
Signed-off-by: John Keeping
---
Unchanged in v3
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b
As a side-effect of this, encode the endianness explicitly rather than
casting a u16.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 +++--
1 file changed, 7 insertions(+), 2 dele
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/roc
In order to fully reset the state of the MIPI controller we must assert
this reset.
This is slightly more complicated than it could be in order to maintain
compatibility with device trees that do not specify the reset property.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add
This shows that we only use the mode from the enable function and
prepares us to remove the "mode" field and the mode_set hook in the next
commit.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
New in v2
drivers/gpu/drm/rockchip/dw-
at we have just read from the status register.
Signed-off-by: John Keeping
Tested-by: Chris Zhong
Reviewed-by: Chris Zhong
---
Unchanged in v3
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/r
As the documentation for readx_poll_timeout says, we want to use the
specialized macro for readl rather than using the generic version
directly.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
This matches other drivers.
Signed-off-by: John Keeping
---
Unchanged in v3
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index
On Mon, 30 Jan 2017 10:26:11 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:44PM +0000, John Keeping wrote:
> > I haven't found any method for getting the length of a response, so this
> > just uses the requested rx_len
> >
> > Signed-off-by: John Ke
On Mon, 30 Jan 2017 13:01:46 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:26PM +0000, John Keeping wrote:
> > As a side-effect of this, encode the endianness explicitly rather than
> > casting a u16.
> >
> > Signed-off-by: John Keeping
> > Reviewe
On Mon, 30 Jan 2017 15:09:55 -0500, Sean Paul wrote:
> On Mon, Jan 30, 2017 at 06:16:36PM +0000, John Keeping wrote:
> > On Mon, 30 Jan 2017 13:01:46 -0500, Sean Paul wrote:
> >
> > > On Sun, Jan 29, 2017 at 01:24:26PM +, John Keeping wrote:
> > > >
On Mon, 30 Jan 2017 15:08:11 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:30PM +0000, John Keeping wrote:
> > By dereferencing the MIPI command buffer as a u32* we rely on it being
> > correctly aligned on ARM, but this may not be the case. Copy it into a
> > sta
On Mon, 30 Jan 2017 15:19:53 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:32PM +0000, John Keeping wrote:
> > Panel drivers may want to sent commands during the disable function, for
> > example MIPI_DCS_SET_DISPLAY_OFF before the video signal ends. In order
> >
On Mon, 30 Jan 2017 15:28:08 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:35PM +0000, John Keeping wrote:
> > The bias, bandgap and PLL should all be configured before we enable
> > them.
> >
>
> Do you know why the test codes are hard-coded magic? It
On Mon, 30 Jan 2017 16:57:36 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:36PM +0000, John Keeping wrote:
> > These values are specified as constant time periods but the PHY
> > configuration is in terms of the current lane byte clock so using
> > constant value
On Mon, 30 Jan 2017 15:16:09 -0500, Sean Paul wrote:
> On Mon, Jan 30, 2017 at 06:14:27PM +0000, John Keeping wrote:
> > On Mon, 30 Jan 2017 10:26:11 -0500, Sean Paul wrote:
> >
> > > On Sun, Jan 29, 2017 at 01:24:44PM +, John Keeping wrote:
> > > > I
On Mon, 30 Jan 2017 15:25:10 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:33PM +0000, John Keeping wrote:
> > This clock rate is derived from the PHY PLL, so it should be calculated
> > dynamically. Use the same calculation as the vendor kernel to derive
> > t
On Tue, 31 Jan 2017 14:21:17 -0500, Sean Paul wrote:
> On Sun, Jan 29, 2017 at 01:24:41PM +0000, John Keeping wrote:
> > This ensures that the output resolution is known before fbcon loads.
> >
> > Signed-off-by: John Keeping
> > ---
> > Unchanged in v3
> >
On Wed, 15 Feb 2017 11:38:45 +0800, Chris Zhong wrote:
> On 01/29/2017 09:24 PM, John Keeping wrote:
> > In order to fully reset the state of the MIPI controller we must assert
> > this reset.
> >
> > This is slightly more complicated than it could be in order to main
On Thu, 16 Feb 2017 10:12:33 +0800, Chris Zhong wrote:
> On 02/15/2017 08:39 PM, John Keeping wrote:
> > On Wed, 15 Feb 2017 11:38:45 +0800, Chris Zhong wrote:
> >
> >> On 01/29/2017 09:24 PM, John Keeping wrote:
> >>> In order to fully reset the state o
On Thu, 16 Feb 2017 11:01:46 +0800, Chris Zhong wrote:
> On 02/01/2017 03:22 AM, Sean Paul wrote:
> > On Sun, Jan 29, 2017 at 01:24:42PM +0000, John Keeping wrote:
> >
> > Reviewed-by: Sean Paul
> >
> >> Signed-off-by: John Keeping
> >> Reviewed-
On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> > Hi all
> >
> > [Resend this v7 version series, since there are 5 mails have gone missing,
> > last
> > week]
> >
> > This version does not change the existing v6 patches, just
On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping wrote:
> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> >
> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> >> > Hi all
&
This clock rate is derived from the PHY PLL, so it should be calculated
dynamically. This calculation is the same as that used by the vendor
kernel and ensures that the escape clock runs at <20MHz as required by
the MIPI specification.
Signed-off-by: John Keeping
Reviewed-by: Chris Zh
With atomic modesetting the hardware will be powered off when the
mode_set function is called. We should configure the hardware in the
enable function, which is the atomic version of "commit" so let's use
the enable hook rather than commit while we're at it.
Signed-off-by: Jo
at we have just read from the status register.
Signed-off-by: John Keeping
Tested-by: Chris Zhong
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
Unchanged in v3
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++
1 file changed, 6 i
We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits
are set so we can't just check "val & mask" because that will be true if
either bit is set.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Rev
This is not needed since we can access the mode via the CRTC from the
enable hook. Also remove the "mode" field that is no longer used.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Add Chris' R
When connected to the MIPI DSI output, we need to use N{H,V}SYNC for the
internal connection but these flags are meaningless for DSI panels.
Switch the test so that we do not set the P{H,V}SYNC bits unless the
mode requires it.
Signed-off-by: John Keeping
Reviewed-by: Mark Yao
Reviewed-by: Sean
on the list if anyone wants to pick it up in the future.
Version 3 was posted here:
http://www.spinics.net/lists/dri-devel/msg130977.html
Thanks to Sean Paul and Chris Zhong for their review and testing of this
series.
John Keeping (23):
drm/rockchip: dw-mipi-dsi: don't configure hard
call which seems to be a workaround for a specific panel and
thus belongs in the panel driver.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Add Chris' Reviewed-by
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-
As the documentation for readx_poll_timeout says, we want to use the
specialized macro for readl rather than using the generic version
directly.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Add Chris' Reviewed-by
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Add Chris' Reviewed-by
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
di
in order to
ensure that the PHY configuration is correct.
Signed-off-by: John Keeping
---
v4:
- Simplify ns2bc and ns2ui calculations as suggested by Sean Paul
v3:
- Wrap some long lines
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 35 ++
1 file
Also don't power up the DSI host at this point since this is not
necessary in order to configure the PHY and we do so later when
selecting video or command mode.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
-
By dereferencing the MIPI command buffer as a u32* we rely on it being
correctly aligned on ARM, but this may not be the case. Copy it into a
stack variable that will be correctly aligned.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged
As an aid to debugging.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Add Chris' Reviewed-by
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
di
In order to fully reset the state of the MIPI controller we must assert
this reset.
This is slightly more complicated than it could be in order to maintain
compatibility with device trees that do not specify the reset property.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v4:
- Fix
This ensures that the output resolution is known before fbcon loads.
mipi_dsi_host_register() is moved above dw_mipi_dsi_register() to
simplify error cleanup since the order of these operations does not
matter.
Signed-off-by: John Keeping
---
v4:
- Use "return 0" to separate normal
54, N = 4 as given by the databook.
While doing this, change the loop limits to encode the actual limits on
the divisor, which are:
40MHz >= (pllref / N) >= 5MHz
Signed-off-by: John Keeping
Reviewed-by: Sean Paul
---
v4:
- Add a comment explaining the limits so that it can be unde
Instead of always sending commands in LP mode, respect the
MIPI_DSI_MSG_USE_LPM flag to decide how to send each message. Also
request acks if MIPI_DSI_MSG_REQ_ACK is set.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
The bias, bandgap and PLL should all be configured before we enable
them.
Signed-off-by: John Keeping
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Squash together two patches that both affect initialization order of
the PHY
Unchanged in v2
---
drivers/gpu/drm/rockch
This matches other drivers.
Signed-off-by: John Keeping
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
Unchanged in v3
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw
Requesting the HS clock from the PHY before we initialize it causes an
invalid signal to be sent out since the input clock is not yet
configured. The PHY databook suggests only asserting this signal when
performing HS transfers, so let's do that.
Signed-off-by: John Keeping
Reviewed-by:
This shows that we only use the mode from the enable function and
prepares us to remove the "mode" field and the mode_set hook in the next
commit.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4:
- Add Sean's Reviewed-by
v3:
- Add Chris' R
Some panels need to be configured with commands sent over the MIPI link,
which they will do in the prepare hook. Call this after the PHY has
been initialized so that we are able to send commands to the panel.
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
Reviewed-by: Sean Paul
---
v4
As a side-effect of this, encode the endianness explicitly rather than
casting a u16.
Signed-off-by: John Keeping
---
v4:
- Introduce "data" variable to avoid confusion around the masking in
GEN_HDATA()
v3:
- Add Chris' Reviewed-by
Unchanged in v2
---
drivers/gpu/drm/rockchi
This reset is required in order to fully reset the internal state of the
MIPI controller.
Signed-off-by: John Keeping
---
On Thu, 2 Mar 2017 13:56:46 -0800, Brian Norris wrote:
> On Fri, Feb 24, 2017 at 12:55:06PM +0000, John Keeping wrote:
> > + /*
> > +* Note that th
On Wed, 15 Mar 2017 09:47:29 -0700, Brian Norris wrote:
> On Wed, Mar 15, 2017 at 04:42:31PM +0800, Chris Zhong wrote:
> > For RK3399, the grf clk should be enabled before writing grf registers,
> > otherwise the register value can not be changed.
> >
> > Signed-off-by: Chris Zhong
> > ---
> >
On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote:
> For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
> disabled, MIPI phy can not work. Let's return a error if there is no
> phy_cfg_clk in dts property, when the pdata match RK3399.
>
> Signed-off-by: Chris Zhong
> ---
>
>
on, 19 Sep 2016 18:17:10 +0100, John Keeping wrote:
> This is a bit of a mixed selection of patches to all areas of the
> Rockchip dw-mipi-dsi driver, which I've been using for a while.
>
> The first few patches fix the driver's use of the atomic API by removing
> hard
We should configure these functions before enabling them.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index
Use the same calculation as the vendor kernel to derive the escape clock
speed.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index f824c99b872e..463e469fd1b8 100644
--- a/drivers/gpu/drm/rockchip/dw
As the documentation for readx_poll_timeout says, we want to use the
specialized macro for readl rather than using the generic version
directly.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a
Rockchip DRM is fully atomic and commit is deprecated for atomic
drivers. No changed are needed beyond renaming the function.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip
In order to fully reset the state of the MIPI controller we must assert
this reset.
This is slightly more complicated than it could be in order to maintain
compatibility with device trees that do not specify the reset property.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi
As an aid to debugging.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 38186df8476e..a25db02e1c19 100644
--- a
We should configure these functions before enabling them.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index
In the atomic world the new connector state is not set when mode_set is
called and we should use the adjusted_mode parameter.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip
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