The cursor plane should use the current plane state hook in
atomic_async_update because it would not be the new plane state in
the global atomic state, since drm_atomic_helper_swap_state happened
when those plane state hook are run.
Fix cursor plane didn't update issue by below modification:
1. Re
Change in v3:
- Fix patch title and drop new line after Fixes tag.
- Add more detail information to commit message.
Change in v2:
- Fix typo in patch message.
jason-jh.lin (1):
drm/mediatek: Fix cursor plane didn't update
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 -
drivers/gpu/drm/media
The cursor plane should use the current plane state in atomic_async_update
because it would not be the new plane state in the global atomic state
since _swap_state happened when those hook are run.
Fix cursor plane issue by below modification:
1. Remove plane_helper_funcs->atomic_update(plane, sta
Add mt8195 SoC DRM binding
1. Due to the 2 display hardware path in mt8195 SoC, we need to add vdosys0
and vdosys1 into mmsys binding document.
2. DSC and MERGE is used in vdosys0, so we need to add DSC binding file
and additional MERGE description into original disp binding document.
jason-
clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --gi
Add mt8195 SoC display binding.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,disp.yaml | 24 +--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
b/Documentation/devicetre
1. clock drivers of MERGE
The MERGE controller may have 2 clock inputs.
The second clock of MERGE is async clock which is controlling
the async buffer between MERGE and other display function blocks.
2. MERGE fifo settings enable
The setting of merge fifo is mainly provided for the dis
There are 2 display hardware path in mt8195, namely vdosys0 and
vdosys1, so add their definition in mtk-mmsys documentation.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt-bindings: arm: mediatek: mmsys: convert to YAML format
-
https://patchwork.kernel.org/project/linux-me
Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+ - Jason-JH Lin
+
+description: |
+ The DSC standard is a specification of the algorithms used for
+ compressing and decompressing image display streams, including
+ the specification of the syntax and semantics of the compressed
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3][4]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dt
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mtk-mutex.c | 93 ++--
1 file changed,
Add DSC into mtk_drm_ddp_comp to support for mt8195.
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specific
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mt8195-mmsys.h|
Add MERGE module file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/med
The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.
Change in v4:
- extract dt-binding patches to another patch series
https://patchwork.kernel.org/project/linux-mediatek/list/?series=51959
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drive
On Fri, 2021-07-23 at 13:13 +0200, Enric Balletbo Serra wrote:
> Hi Jason,
>
> Thank you for your patch.
>
> Missatge de jason-jh.lin del dia dj., 22
> de jul. 2021 a les 11:26:
> >
> > There are 2 display hardware path in mt8195, namely vdosys0 and
> > vdosys1, so add their definition in mtk-m
Hi Enric,
On Mon, 2021-07-26 at 12:08 +0200, Enric Balletbo Serra wrote:
> Hi Jason,
>
> Missatge de Jason-JH Lin del dia dl., 26
> de jul. 2021 a les 9:02:
> >
> > On Fri, 2021-07-23 at 13:13 +0200, Enric Balletbo Serra wrote:
> > > Hi Jason,
>
Hi Enric,
Thanks for your review.
On Wed, 2021-07-28 at 12:56 +0200, Enric Balletbo Serra wrote:
> Hi Jason,
>
> Missatge de Jason-JH Lin del dia dt., 27
> de jul. 2021 a les 4:53:
> >
> > Hi Enric,
> >
> > On Mon, 2021-07-26 at 12:08 +0200, Enric
Change in v2:
- add power-domain property into mediatek,mmsys.yaml
and modify commit message.
jason-jh.lin (5):
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
dt-bindings: mediatek: display: Change format to yaml
dt-bindings: mediatek: display: add MERGE additional description
Add mt8195 SoC display binding.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,disp.yaml | 24 +--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
b/Documentation/devicetre
clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --gi
Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+ - Jason-JH Lin
+
+description: |
+ The DSC standard is a specification of the algorithms used for
+ compressing and decompressing image display streams, including
+ the specification of the syntax and semantics of the compressed
1. clock drivers of MERGE
The MERGE controller may have 2 clock inputs.
The second clock of MERGE is async clock which is controlling
the async buffer between MERGE and other display function blocks.
2. MERGE fifo settings enable
The setting of merge fifo is mainly provided for the dis
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt
The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mm
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3][4]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dt
Add DSC into mtk_drm_ddp_comp to support for mt8195.
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specific
Add MERGE module file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/med
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mt8195-mmsys.h|
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drive
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mtk-mutex.c | 93 ++--
1 file changed,
gt; > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 32 ++-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/soc/mediatek/mt8195-mmsys.h | 96 +++
> > drivers/soc/mediatek/mtk-mmsys.c| 11 +
> > drivers/soc/mediatek/mtk-mutex.c| 93 ++-
> > include/linux/soc/mediatek/mtk-mmsys.h | 9 +
> > 13 files changed, 706 insertions(+), 4 deletions(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
--
Jason-JH Lin
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> > .clk_driver = "clk-mt2701-mm",
> > @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -157,6 +164,10 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8183-mmsys",
> > .data = &mt8183_mmsys_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-vdosys0",
> > + .data = &mt8195_vdosys0_driver_data,
> > + },
> > { }
> > };
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 2228bf6133da..01bedfb08094 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -39,6 +39,15 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_UFOE,
> > DDP_COMPONENT_WDMA0,
> > DDP_COMPONENT_WDMA1,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > + DDP_COMPONENT_DP_INTF0,
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> >
--
Jason-JH Lin
erge has no async clock?
>
> Regards,
> Chun-Kuang.
>
Only the MERGE linked to the display function block that is cross
vdosys0 to vdosys1 need to add async clock.
I'll add this description into this patch [1]
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729154912.20051-4-jason-jh@mediatek.com/
Regards,
Jason-JH.Lin
> > + mediatek,gce-client-reg =
> > +<&gce1 SUBSYS_1c01 0x4000
> > 0x1000>;
> > + };
> > +
--
Jason-JH Lin
Change in v3:
- slpit each display function block to individual taml file.
Change in v2:
- add power-domain property into mediatek,mmsys.yaml
and modify commit message.
jason-jh.lin (4):
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
dt-bindings: mediatek: display: split each blo
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema.
2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml
1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml| 75 ++
.../display/mediatek/mediatek,ccorr.yaml | 69 ++
.../display/mediatek/mediatek,color.yaml | 84
1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,dsc.yaml| 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindi
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt
The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.
Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as the lastest patch
- a
1. Adjust to the alphabetic order for the define, function, struct
and array in mediatek-drm driver
2. Remove the unsed define in mtk_drm_ddp_comp.c
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +---
drivers/gpu/drm/mediatek/mtk_drm_ddp_com
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-j
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh@mediatek.com/
-
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
vi
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3][4]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dt
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh@mediatek.com/
---
drivers/soc/mediatek/mtk
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/202108051713
gt; >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index d6f6d1bdad85..0f6bb4bdc58a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -446,6 +446,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_GAMMA, },
> > { .compatible = "mediatek,mt8183-disp-dither",
> > .data = (void *)MTK_DISP_DITHER },
> > + { .compatible = "mediatek,mt8195-disp-dsc",
> > + .data = (void *)MTK_DISP_DSC },
>
> I would like you move this patch before the patch "add mediatek-drm
> of
> vdosys0 support for mt8195" and move this part into that patch.
>
> Regards,
> Chun-Kuang.
>
OK, I'll move this part.
Regards,
Jason-JH.Lin
> > { .compatible = "mediatek,mt8173-disp-ufoe",
> > .data = (void *)MTK_DISP_UFOE },
> > { .compatible = "mediatek,mt2701-dsi",
> > --
> > 2.18.0
> >
--
Jason-JH Lin
type == MTK_DISP_MERGE ||
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 661fb620e266..0afd78c0bc92 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_OD,
> > MTK_DISP_BLS,
> > MTK_DISP_DSC,
> > + MTK_DISP_MERGE,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 0f6bb4bdc58a..53e0de3f17d7 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -448,6 +448,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_DITHER },
> > { .compatible = "mediatek,mt8195-disp-dsc",
> > .data = (void *)MTK_DISP_DSC },
> > + { .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)MTK_DISP_MERGE },
>
> Move this patch before the patch "add mediatek-drm of vdosys0 support
> for mt8195" and move this part into that patch.
>
> Regards,
> Chun-Kuang.
>
I'll move this part.
Regards,
Jason-JH.Lin
> > { .compatible = "mediatek,mt8173-disp-ufoe",
> > .data = (void *)MTK_DISP_UFOE },
> > { .compatible = "mediatek,mt2701-dsi",
> > @@ -558,13 +560,14 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> > private->comp_node[comp_id] = of_node_get(node);
> >
> > /*
> > -* Currently only the CCORR, COLOR, GAMMA, OVL,
> > RDMA, DSI, and DPI
> > +* Currently only the CCORR, COLOR, GAMMA, MERGE,
> > OVL, RDMA, DSI, and DPI
> > * blocks have separate component platform drivers
> > and initialize their own
> > * DDP component structure. The others are
> > initialized here.
> > */
> > if (comp_type == MTK_DISP_CCORR ||
> > comp_type == MTK_DISP_COLOR ||
> > comp_type == MTK_DISP_GAMMA ||
> > + comp_type == MTK_DISP_MERGE ||
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > @@ -665,6 +668,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_disp_ccorr_driver,
> > &mtk_disp_color_driver,
> > &mtk_disp_gamma_driver,
> > + &mtk_disp_merge_driver,
> > &mtk_disp_ovl_driver,
> > &mtk_disp_rdma_driver,
> > &mtk_dpi_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..0fa417219a69 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -49,6 +49,7 @@ struct mtk_drm_private {
> > extern struct platform_driver mtk_disp_ccorr_driver;
> > extern struct platform_driver mtk_disp_color_driver;
> > extern struct platform_driver mtk_disp_gamma_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> >
--
Jason-JH Lin
To avoid the output width and height is incorrect,
AAL_OUTPUT_SIZE configuration should be set.
Fixes: 0664d1392c26 ("drm/mediatek: Add AAL engine basic function")
Signed-off-by: jason-jh.lin
---
Change in v2:
- fix to one line
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file chang
Add component_del in OVL and COLOR remove function.
Fixes: ff1395609e20 ("drm/mediatek: Move mtk_ddp_comp_init() from sub driver to
DRM driver")
Signed-off-by: jason-jh.lin
---
Change in v2:
- add component_del function in COLOR remove function
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 2
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > + {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
>
> Please update the struct to the new version that includes a mask
> field.
>
OK, I'll add [2] before my patch and also test it on mt8195 SoC
platform.
[2]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-li...@fw-web.de/
> Regards,
> Matthias
--
Regards,
Jason-JH Lin
= THIS_MODULE,
> > + .of_match_table = mtk_disp_merge_driver_dt_match,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 560be6bc9d0e..b42a47c06956 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_DITHER,
> > MTK_DISP_DSC,
> > MTK_DISP_GAMMA,
> > + MTK_DISP_MERGE,
> > MTK_DISP_MUTEX,
> > MTK_DISP_OD,
> > MTK_DISP_OVL,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index a95dc1006b82..5eb9c0a04447 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> > private->comp_node[comp_id] = of_node_get(node);
> >
> > /*
> > -* Currently only the CCORR, COLOR, GAMMA, OVL,
> > RDMA, DSI, and DPI
> > +* Currently only the CCORR, COLOR, GAMMA, MERGE,
> > OVL, RDMA, DSI, and DPI
> > * blocks have separate component platform drivers
> > and initialize their own
> > * DDP component structure. The others are
> > initialized here.
> > */
> > if (comp_type == MTK_DISP_CCORR ||
> > comp_type == MTK_DISP_COLOR ||
> > comp_type == MTK_DISP_GAMMA ||
> > + comp_type == MTK_DISP_MERGE ||
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > @@ -639,6 +640,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_disp_ccorr_driver,
> > &mtk_disp_color_driver,
> > &mtk_disp_gamma_driver,
> > + &mtk_disp_merge_driver,
> > &mtk_disp_ovl_driver,
> > &mtk_disp_rdma_driver,
> > &mtk_dpi_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..0fa417219a69 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -49,6 +49,7 @@ struct mtk_drm_private {
> > extern struct platform_driver mtk_disp_ccorr_driver;
> > extern struct platform_driver mtk_disp_color_driver;
> > extern struct platform_driver mtk_disp_gamma_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> >
--
Jason-JH Lin
;
> Ditto.
>
> > [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od
> > },
> > [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, &ddp_od
> > },
> > [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL, 0, &ddp_ovl
> > },
> > @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_GAMMA ||
> > + type == MTK_DISP_MERGE ||
>
> Ditto.
>
> Regards,
> Chun-Kuang.
>
OK, I'll move them into MERGE patch.
Regards,
Jason-JH.Lin
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index d317b944df66..560be6bc9d0e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_CCORR,
> > MTK_DISP_COLOR,
> > MTK_DISP_DITHER,
> > + MTK_DISP_DSC,
> > MTK_DISP_GAMMA,
> > MTK_DISP_MUTEX,
> > MTK_DISP_OD,
> > --
> > 2.18.0
> >
--
Jason-JH Lin
ompatible = "mediatek,mt2701-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8173-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8183-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt2701-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8173-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8183-dpi",
> > - .data = (void *)MTK_DPI },
> > { .compatible = "mediatek,mt2701-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt8183-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > + { .compatible = "mediatek,mt8173-disp-od",
> > + .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8173-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > + .data = (void *)MTK_DISP_OVL_2L },
> > { .compatible = "mediatek,mt2701-disp-pwm",
> > .data = (void *)MTK_DISP_BLS },
> > { .compatible = "mediatek,mt8173-disp-pwm",
> > .data = (void *)MTK_DISP_PWM },
> > - { .compatible = "mediatek,mt8173-disp-od",
> > - .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8183-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-ufoe",
> > + .data = (void *)MTK_DISP_UFOE },
> > + { .compatible = "mediatek,mt8173-disp-wdma",
> > + .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt2701-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8173-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt2701-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8173-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8183-dsi",
> > + .data = (void *)MTK_DSI },
> > { }
> > };
> >
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > - comp_type == MTK_DSI ||
> > - comp_type == MTK_DPI) {
> > + comp_type == MTK_DPI ||
> > + comp_type == MTK_DSI) {
> > dev_info(dev, "Adding component match for
> > %pOF\n",
> > node);
> > drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> >
--
Jason-JH Lin
Remove the unsed define in mtk_drm_ddp_comp.c
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
vi
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting
Change in v6:
- adjust alphabetic order for
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: d
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
Reviewed-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28
2 files changed, 34 insertions(+)
diff -
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268
Adjust to the alphabetic order for the define, function, struct
and array in mediatek-drm driver
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c
Add DISP_REG prefix for the define of register offset to
make the difference from the define of register value.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++--
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/
1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,dsc.yaml| 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindi
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1] soc: mmsys: mediatek: add mask to mmsys routes
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-li...@fw-web.de/
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema.
2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin
---
.../devicetree/bindings/arm/mediate
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
drivers/soc/mediatek/mtk-mutex.c | 93 ++--
1 file changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576.
1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml| 75 ++
.../display/mediatek/mediatek,ccorr.yaml | 69 ++
.../display/mediatek/mediatek,color.yaml | 84
1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,dsc.yaml| 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindi
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
drivers/soc/mediatek/mtk-mutex.c | 98 +++-
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576.
Remove the unsed define in mtk_drm_ddp_comp.c
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp funtion
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unus
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
Reviewed-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28
2 files changed, 34 insertions(+)
diff -
Add DISP_REG prefix for the define of register offset to
make the difference from the define of register value.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++--
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1][2]
[1] soc: mediatek: mmsys: add MT8365 support
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-3-fpar...@baylibre.
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dts:
Adjust to the alphabetic order for the define, function, struct
and array in mediatek-drm driver
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268
1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml| 75 ++
.../display/mediatek/mediatek,ccorr.yaml | 69 ++
.../display/mediatek/mediatek,color.yaml | 84
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
vi
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema.
2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml
cription:
> > + A phandle and PM domain specifier as defined by bindings
> > + of the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml
> > for details.
> > +
>
> This patch is about mt8195, but mt8173 mmsys also has power domain.
> So
> move this part to another patch.
>
> Regards,
> Chun-Kuang.
>
OK, I'll move this part to another patch.
Regards,
Jason-JH.Lin
>
> >"#clock-cells":
> > const: 1
> >
> > --
> > 2.18.0
> >
--
Jason-JH Lin
DDP_COMPONENT_DPI1:
> > sof_id = MUTEX_SOF_DPI1;
> > break;
> > + case DDP_COMPONENT_DP_INTF0:
> > + sof_id = MUTEX_SOF_DP_INTF0;
> > + break;
>
> How about MUTEX_SOF_DP_INTF1?
MUTEX_SOF_DP_INTF1 won't use in vdosys0, so it will be added at the
patch [1] in vdosys1 series.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210818091847.8060-12-nancy@mediatek.com/
>
> > default:
> > if (mtx->data->mutex_mod[id] < 32) {
> > offset = DISP_REG_MUTEX_MOD(mtx->data-
> > >mutex_mod_reg,
> > @@ -386,6 +475,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> > *mutex,
> > case DDP_COMPONENT_DSI3:
> > case DDP_COMPONENT_DPI0:
> > case DDP_COMPONENT_DPI1:
> > + case DDP_COMPONENT_DP_INTF0:
>
> Ditto.
>
> Regards,
> Chun-Kuang.
>
Ditto.
Regards,
Jason-JH.Lin
> > writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> >mtx->regs +
> >DISP_REG_MUTEX_SOF(mtx->data-
> > >mutex_sof_reg,
> > @@ -507,6 +597,8 @@ static const struct of_device_id
> > mutex_driver_dt_match[] = {
> > .data = &mt8173_mutex_driver_data},
> > { .compatible = "mediatek,mt8183-disp-mutex",
> > .data = &mt8183_mutex_driver_data},
> > + { .compatible = "mediatek,mt8195-disp-mutex",
> > + .data = &mt8195_mutex_driver_data},
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
> > --
> > 2.18.0
> >
--
Jason-JH Lin
"mediatek,mt8183-dpi",
> > - .data = (void *)MTK_DPI },
> > { .compatible = "mediatek,mt2701-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > +dsc0: disp_dsc_wrap@1c009000 {
> > +compatible = "mediatek,mt8195-disp-dsc";
> > +reg = <0 0x1c009000 0 0x1000>;
> > +interrupts = ;
> > +power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > +clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> > +mediatek,gce-client-reg = <&gce1 SUBSYS_1c00 0x9000
> > 0x1000>;
> > +};
> > +
> > --
> > 2.18.0
> >
--
Jason-JH Lin
FS_EN GENMASK(8, 8)
> > +#define DISP_REG_MERGE_CFG_37 0x0a4
> > +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> > +#define BUFFER_MODE3
> > +#define FLD_BUFFER_MODEGENMASK(1,
> > 0)
> > +#define DISP_REG_MERGE_CFG_38 0x0a8
> > +#define FLD_VDE_BLOCK_ULTRAGENMASK(0, 0)
> > +#define FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4)
> > +#define FLD_ULTRA_FIFO_VALID_THGENMASK(31,
> > 16)
> > +#define DISP_REG_MERGE_CFG_39 0x0ac
> > +#define FLD_NVDE_FORCE_PREULTRAGENMASK(8,
> > 8)
> > +#define FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12)
> > +#define FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16)
--
Jason-JH Lin
1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,dsc.yaml| 70 +++
1 file changed, 70 insertions(+)
create mode 100644
Documentation/devicetree/bindi
There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt-bindings: arm: mediatek: mmsys: convert to YAML format
Remove the unsed define in mtk_drm_ddp_comp.c
Signed-off-by: jason-jh.lin
---
rebase on [1] series
[1] drm/mediatek: Separate aal module
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 --
1 file changed, 10 d
Power:
1. Add description for power-domains property.
GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 28 ++-
1 file changed, 27 insertions(+), 1
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
vi
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dts:
Change in v9:
- seperate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to m
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1][2]
[1] soc: mediatek: mmsys: add MT8365 support
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-3-fpar...@baylibre.
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
drivers/soc/mediatek/mtk-mutex.c | 98 +++-
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576.
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema.
2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml
Add DISP_REG prefix for the define of register offset to
make the difference from the define of register value.
Signed-off-by: jason-jh.lin
---
rebase on [1] series
[1] drm/mediatek: Separate aal module
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
---
drivers/gpu/drm
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