[PATCH v6 10/12] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes

On Wed, 2015-11-18 at 18:34 +0100, Philipp Zabel wrote: > These muxes are supposed to select a fitting divider after the PLL > is already set to the correct rate. > > Signed-off-by: Philipp Zabel Acked-by: James Liao > --- > drivers/clk/mediatek/clk-mt8173.c | 4 ++-- >

[PATCH v6 11/12] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output

p Zabel Acked-by: James Liao > --- > drivers/clk/mediatek/clk-mt8173.c | 5 + > include/dt-bindings/clock/mt8173-clk.h | 3 ++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/mediatek/clk-mt8173.c > b/drivers/clk/mediatek/clk-mt81