On Sun, Sep 13, 2015 at 6:01 PM, Ondrej Zary
wrote:
> On Sunday 13 September 2015 21:12:25 Ilia Mirkin wrote:
>> On Sun, Sep 13, 2015 at 2:57 PM, Ondrej Zary
>> wrote:
>> > Hello,
>> > I have a PC Chips A31G board with AGPro slot and found that nouveau do
On Wed, Sep 16, 2015 at 3:52 PM, Pierre Moreau wrote:
> If the hardware supports extended tag field (8-bit ones), then enabled it.
> This
> is usually done by the VBIOS, but not on some MBPs (see fdo#86537).
> In case extended tag field is not supported, 5-bit tag field is used which
> limits the
On Wed, Feb 11, 2015 at 3:53 AM, wrote:
> Hello.
>
> I'm looking for a PCI or AGP video card that would work on a Linux port for a
> big endian architecture (HP PA-RISC). Unfortunately the stock video options
> (ATI FireGL X1 and X3) give an incredibly slow unaccelerated 2D due to
> failure to
This is the nva3 counterpart to commit beba44b17 (drm/nv84/disp: Fix
HDMI audio regression). The regression happened as a result of
refactoring in commit 8e9e3d2de (drm/nv84/disp: move hdmi control into
core).
Reported-and-tested-by: Max Baldwin
Signed-off-by: Ilia Mirkin
---
The actual
On Fri, Jul 26, 2013 at 2:28 PM, konrad wilk wrote:
> I just saw this on a box of mine (rc1 worked) I hadn't done yet a bisection.
> Any suggestions?
>
> ring 0 polarity 1
> [6.023776] Already setup the GSI :22
> ^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G^G[6.036680] nouveau [
> DEVICE]
Hello,
I've started seeing the following warning in 3.11-rc2. [In the
interest of full disclosure, I do have a patch applied that tries to
implement drm_planes, which I might have done completely incorrectly,
but looking around it doesn't seem related. I'm definitely not
invoking any of the planes
On Fri, Jul 26, 2013 at 8:39 PM, Ilia Mirkin wrote:
> Hello,
>
> I've started seeing the following warning in 3.11-rc2. [In the
> interest of full disclosure, I do have a patch applied that tries to
> implement drm_planes, which I might have done completely incorrectly,
>
This makes it so that reloading a module does not cause all the
connector ids to change, which are user-visible and sometimes used
for configuration.
Signed-off-by: Ilia Mirkin
---
Only mild testing... reloaded nouveau a few times, all the connectors
kept their original ids.
drivers/gpu/drm
This makes it so that reloading a module does not cause all the
connector ids to change, which are user-visible and sometimes used
for configuration.
Signed-off-by: Ilia Mirkin
---
v1 -> v2: correct loop condition... not sure how that slipped past
me... the code started out by being <
mechanism to load the kernel for the xtensa chips and
provide the necessary interactions to do the rest of the work.
Signed-off-by: Ilia Mirkin
---
This patch applies on top of nouveau/master (16a41bcc8).
This seems to work for me. There was one boot where my userspace
component didn't work
On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin wrote:
> These chipsets include the VP2 engine which is composed of a bitstream
> processor (BSP) that decodes H.264 and a video processor (VP) which can
> do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are
> driven by sep
On Tue, Jun 4, 2013 at 4:48 PM, Henrik Rydberg wrote:
> Hi Ben,
>
> The new mutexes in nvc0/nv50 (fadb17190/b509656) break resume on my
> MBA3,1. A dead-lock somewhere, perhaps? Reverting fixes the problem.
A bunch of people saw it earlier. Fixed for nv50 (which is what I
assume you have) in
http
On Wed, Jun 5, 2013 at 3:05 AM, Maarten Lankhorst
wrote:
> Hey,
>
> Op 04-06-13 20:38, Ilia Mirkin schreef:
>> On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin wrote:
>>> These chipsets include the VP2 engine which is composed of a bitstream
>>> processor (BS
Adding Erik and Thierry, who probably know a lot more about this.
AFAIK Tegra2/3 used an ISA more akin to the NV30/NV40 family, but
probably not similar enough to just reuse nouveau's nvfx_vert/frag
stuff wholesale.
Are you interested in helping along, or were you just trying to figure
out if it
On Tue, Apr 7, 2015 at 3:29 PM, George McCollister
wrote:
> Looks like these are the magic bits that need to be set:
>
> dpll |= (7<<9) | (1<<13) | (1<<14);
>
> Anyone happen to have proper descriptions for these bits so I could
> add them to psb_intel_reg.h or thoughts on how/where an option coul
On Tue, Apr 21, 2015 at 4:10 PM, Emil Velikov
wrote:
> Hi Tobias,
>
> On 20/04/15 19:50, Tobias Jakobi wrote:
>> Only the 'offsets' array was initialized to zero.
>> Since bo_create only sets the handles which are
>> necessary, were we passing garbage data to the
>> kernel when calling drmModeAdd
On Thu, Apr 23, 2015 at 9:39 AM, Tobias Jakobi
wrote:
> Hello Ilia,
>
> On 2015-04-21 21:15, Ilia Mirkin wrote:
>>
>> I know it was immensely useful to me when I was adding YUV plane
>> support to nouveau. Seemed to work as advertised at the time (1.5y
>&
On Fri, Aug 7, 2015 at 5:45 AM, Michel Thierry
wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must always be
> allocated inside the 32-bit address range.
>
> In specific, any resource used with flat/heapless (0x-0xf000)
> General State Heap or Intruction State Heap
mechanism to load the kernel for the xtensa chips and
provide the necessary interactions to do the rest of the work.
Signed-off-by: Ilia Mirkin
---
v1 -> v2:
- factored out similar logic between vp and bsp into a new xtensa.c, similar
to falcon
- moved firmware loading to init rather than c
While using chrome, I got the following. It was able to render the bug
to the screen, so at least something was working (and it also made it
to my logs).
[223614.867297] BUG: unable to handle kernel paging request at c90013a0
[223614.867372] IP: [] iowrite32+0x12/0x33
[223614.867427] PGD 1
On Sat, Dec 28, 2024 at 7:39 AM Gert Vanhaerents <
gert.vanhaere...@hotmail.com> wrote:
> In the meantime I have contacted everyone who could have something to do
> with it:
> Kernel groups
> System D
> Nvidia
> And gues: Everyone says it's not their fault.
>
> But we don't give up. Linux is such
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