At least the Rockchip variant of the dw_hdmi can have controllable power
supplies
providing 1.0 and 1.8V. Therefore add the possibility for the generic bridge
driver to enable supplies provided by the hw-specific drivers.
Signed-off-by: Heiko Stuebner
---
changes since v2:
- rename supplies to
Add the recently added hdmi power supplies to evb and firefly boards.
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rk3288-evb.dtsi | 2 ++
arch/arm/boot/dts/rk3288-firefly.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot
Hi Philipp,
Am Donnerstag, 12. März 2015, 21:45:19 schrieb Heiko Stuebner:
> At least the Rockchip variant of the dw_hdmi can have controllable power
> supplies providing 1.0 and 1.8V. Therefore add the possibility for the
> generic bridge driver to enable supplies provided by the hw
Hi Laurent,
Am Samstag, 28. Februar 2015, 01:42:45 schrieb Heiko Stübner:
> thanks for the comments
>
> Am Donnerstag, 26. Februar 2015, 20:33:33 schrieb Laurent Pinchart:
> > On Saturday 31 January 2015 17:32:56 Heiko Stuebner wrote:
> > > There exist simple vga enco
Hi Yakir,
Am Donnerstag, 12. November 2015, 10:36:51 schrieb Yakir Yang:
> On 11/12/2015 07:23 AM, Heiko Stuebner wrote:
> > Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> >> Add phy driver for the Rockchip DisplayPort PHY module. This
> >> is required to
Hi Yakir,
Am Mittwoch, 11. November 2015, 15:47:32 schrieb Yakir Yang:
> Signed-off-by: Yakir Yang
> ---
> .../display/rockchip/inno_hdmi-rockchip.txt| 50
> ++
> 1 file changed, 50 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/rock
3130c:
>
>drm/rockchip: vop: fix window origin calculation (2015-11-11 08:36:18
> +0800)
>
> ----
> Dominik Behr (1):
>drm/rockchip: vop: fix window origin calculation
>
> Heiko Stuebner (1):
>
component framework.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/i2c/Kconfig | 6 +
drivers/gpu/drm/i2c/Makefile | 2 +
drivers/gpu/drm/i2c/vga-simple.c | 325 +++
3 files changed, 333 insertions(+)
create mode 100644 drivers/gpu/drm/i2c/vga
On socs using the lvds components it also controls the use of the
general rgb outputs and must thus be configured for things like
external encoders.
Therefore register a drm_bridge in this case, an encoder can attach to.
Signed-off-by: Heiko Stuebner
---
.../devicetree/bindings/video/rockchip
Add the necessary devicetree binding document for simple vga encoders.
Signed-off-by: Heiko Stuebner
---
.../devicetree/bindings/drm/i2c/vga-simple.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/i2c/vga-simple.txt
and again directly connected on the
rk3188-radxarock.
Caveats:
- the i2c subdirectory is probably not the right one for my vga encoder
so if somebody could suggest where this should live, I'd be very happy
- I'm not sure if I'm abusing some drm-APIs in a wrong way :-)
Heiko Stuebner
bridges when building the drm device in the load callback.
Signed-off-by: Heiko Stuebner
---
.../devicetree/bindings/video/rockchip-vop.txt | 16 +++
drivers/gpu/drm/rockchip/rockchip_drm_drv.c| 32 ++
2 files changed, 48 insertions(+)
diff --git a
From: Mark Yao
Add binding documentation for Rockchip SoC LVDS driver.
Signed-off-by: Mark Yao
Signed-off-by: Heiko Stuebner
---
.../devicetree/bindings/video/rockchip-lvds.txt| 59 ++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree
From: Mark Yao
This adds support for Rockchip soc lvds found on rk3288
Signed-off-by: Mark Yao
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/rockchip/Kconfig | 9 +
drivers/gpu/drm/rockchip/Makefile| 1 +
drivers/gpu/drm/rockchip/rockchip_lvds.c | 629
The socs itself do not contain encoders for either vga or tv output.
Therefore these will be realized by external components and thus use the
rgb output.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers
Add pinctrl settings for the configurable lcdc0 signals dclk, den, hsync
and vsync. The lcdc0 data pin configuration is not software controlable.
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rk3288.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288
Add an of_node field to struct drm_encoder to let encoders optionally
remember from which devicetree node they originated.
Signed-off-by: Heiko Stuebner
---
include/drm/drm_crtc.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index
Add the sda7123 simple vga encoder, connect it to the vop outputs
and enable the lvds controller with the correct settings.
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm
Add the basic node for the lvds controller of rk3288 and hook it into the
display-subsystem hirarchy.
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rk3288.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch
Am Samstag, 24. Oktober 2015, 11:06:37 schrieb Yakir Yang:
> Add dt binding documentation for rockchip display port PHY.
>
> Tested-by: Javier Martinez Canillas
> Signed-off-by: Yakir Yang
> ---
> Changes in v7: None
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver chan
river of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Tested-by: Javier Martinez Canillas
> Signed-off-by: Yakir Yang
everything else looks nice, so with a better subject
Reviewed-by: Heiko Stuebner
(dp->grf, GRF_SOC_CON12,
> +GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +GRF_EDP_PHY_SIDDQ_ON);
> + if (ret < 0) {
> + dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
&
Am Samstag, 24. Oktober 2015, 11:06:37 schrieb Yakir Yang:
> Add dt binding documentation for rockchip display port PHY.
>
> Tested-by: Javier Martinez Canillas
> Signed-off-by: Yakir Yang
> ---
phy binding looks nice and easy
Reviewed-by: Heiko Stuebner
Hi Yakir,
Am Samstag, 24. Oktober 2015, 11:06:00 schrieb Yakir Yang:
> Analogix dp driver is split from exynos dp driver, so we just
> make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
>
> Beside update some exynos dtsi file with the latest change
> according to the devicetree bindin
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> index 7a3a9cd..9905081 100644
> --- a/Documentation/devicetree/bindings/display/
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp
Am Donnerstag, 29. Oktober 2015, 09:12:21 schrieb Yakir Yang:
> Hi Heiko,
>
> On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
> > Hi Yakir,
> >
> > Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> >> diff --git
> >> a/Documentation/dev
le series on Samsung Exynos5800 Peach Pi Chromebook,
> glad to say that things works rightlly.
Patch 15/17 looks like it didn't make it? I haven't found it in neither my
inbox nor in the linux-rockchip list archive? So I've used the v7 version
for my tests.
This series on a rk3288-veyron-pinky and rk3288-veyron-jerry
Tested-by: Heiko Stuebner
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
>
> Signed-off-by: Yakir Yang
> ---
> Changes in v4:
> - Remove some depreca
Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
>
> Si
Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
>
> Signed-off-by: Yakir Yang
[...]
> diff --git a/drivers/gpu/drm/e
Hi Yakir,
small nit more below
Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> > +- clocks: from common clock binding: handle to dp clock.
> > + of memory mapped region.
> > +- clock-nam
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
>
> Signed-off-by: Yakir Yang
> ---
> Changes in v4:
> - Remove s
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> From: Mark Yao
>
> Add bpc and color mode setting in rockchip_drm_vop driver, so
> connector could try to use the edid drm_display_info to config
> vop output mode.
>
> Signed-off-by: Mark Yao
> Signed-off-by: Yakir Yang
Hi Yakir,
Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some p
Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
> å¨ 09/02/2015 09:27 PM, Rob Herring åé:
> > On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang wrote:
> >> +- clocks: from common clock binding: handle to dp clock.
> >> + of memory mapped region.
> >> +- clock-names: from common
Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner wrote:
> > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> >> Split the dp core driver from exynos directory to bridge
> >> directory, an
lator nodes
- removed trailing whitespace from one line
- drop clock-frequency from armsom sige5 rtc@51
- drop rockchip,grf from cru (lookup is done via compatible)
- order gpu interrupts like expected in the binding
- adjust mmc compatible to binding
Best regards,
--
Heiko Stuebner
mic update
commit: 712ec5de382d009396ced509e75b392d28871aa4
Best regards,
--
Heiko Stuebner
efore check
> 'state' (see line 1077)
>
> [...]
Applied, thanks!
[1/1] drm/rockchip: vop: Fix a dereferenced before check warning
commit: ab1c793f457f740ab7108cc0b1340a402dbf484d
Best regards,
--
Heiko Stuebner
>
> [...]
Applied, thanks!
[1/1] rockchip/drm: vop2: add support for gamma LUT
commit: 4f537776340dab2b680a4d8554567f6884240d0b
I've fixed a number of smaller styling nits that
checkpatch --strict found.
Best regards,
--
Heiko Stuebner
hese are struct drm_mode_config.connection_mutex
> and struct drm_mode_config.mutex.
>
> [...]
Applied, thanks!
[1/1] drm/rockchip: cdn-dp: Use drm_connector_helper_hpd_irq_event()
commit: 666e1960464140cc4bc9203c203097e70b54c95a
Best regards,
--
Heiko Stuebner
Hi,
Am Dienstag, 27. August 2024, 05:03:56 CEST schrieb Jinjie Ruan:
> Avoid need to manually handle of_node_put() by using __free(), and use
> dev_err() to replace deprecated() DRM_DEV_ERROR(), which can simplfy
> code.
please make that two separate commits, one for the dev_err conversion
and on
Hi,
Am Freitag, 30. August 2024, 09:34:54 CEST schrieb Jinjie Ruan:
> Avoids the need for manual cleanup of_node_put() in early exits
> from the loop.
>
> Signed-off-by: Jinjie Ruan
> Reviewed-by: Heiko Stuebner
> ---
> v2:
> - Add Reviewed-by.
> - Split out from
fb311de9cab192b0943426
Best regards,
--
Heiko Stuebner
On Sun, 15 Sep 2024 15:39:43 +0300, Andrew Kreimer wrote:
> Fix a typo in comments.
>
>
Applied, thanks!
[1/1] drm/rockchip: Fix a typo
commit: 87d45979140e49611696e97e2b33df572bf4fa24
Best regards,
--
Heiko Stuebner
Am Dienstag, 27. August 2024, 05:03:57 CEST schrieb Jinjie Ruan:
> Use dev_err_probe to replace deprecated() DRM_DEV_ERROR(), which
> can simplfy code.
>
> Signed-off-by: Jinjie Ruan
> ---
> drivers/gpu/drm/rockchip/rockchip_lvds.c | 30 +---
> 1 file changed, 11 insertions(+
From: Heiko Stuebner
Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
DSI2 host controller, based on the Rockchip version from the driver
rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs.
While the driver is heavily modelled after the previous IP,
From: Heiko Stuebner
This adds the glue code for the MIPI DSI2 bridge on Rockchip SoCs and
enables its use on the RK3588.
Right now the DSI2 controller is always paired with a DC-phy based on a
Samsung IP, so the interface values are set statically for now.
This stays true for the upcoming
From: Heiko Stuebner
The Display Serial Interface 2 (DSI-2) is part of a group of communication
protocols defined by the MIPI Alliance. The RK3588 implements this
specification in its two MIPI DSI-2 Host Controllers that are based on a
new Synopsis IP.
Signed-off-by: Heiko Stuebner
difference is that the phy interface is variable now too
in its width and some other settings.
Heiko Stuebner (3):
drm/bridge/synopsys: Add MIPI DSI2 host controller bridge
dt-bindings: display: rockchip: Add schema for RK3588 DW DSI2
controller
drm/rockchip: Add MIPI DSI2 glue driver for
On Fri, 15 Nov 2024 16:11:31 +0100, Heiko Stuebner wrote:
> The clock is in Hz while the value checked against is in kHz, so
> actual frequencies will never be able to be below to max value.
> Fix this by specifying the max-value in Hz too.
>
>
Applied, thanks!
[1/1] drm/rock
From: Heiko Stuebner
DRM_DEV_ERROR is deprecated and using dev_err_probe saves quite a number
of lines too, so convert the error prints for the dsi-driver.
Signed-off-by: Heiko Stuebner
---
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 80 ++-
1 file changed, 26 insertions
Applied, thanks!
[1/1] drm/rockchip: analogix_dp: allow to work without panel
commit: 86caee745e4506528801d9542db54e7b4c4d834b
Best regards,
--
Heiko Stuebner
From: Heiko Stuebner
The clock is in Hz while the value checked against is in kHz, so
actual frequencies will never be able to be below to max value.
Fix this by specifying the max-value in Hz too.
Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
Signed-off-by: Heik
From: Heiko Stuebner
The Display Serial Interface 2 (DSI-2) is part of a group of communication
protocols defined by the MIPI Alliance. The RK3588 implements this
specification in its two MIPI DSI-2 Host Controllers that are based on a
new Synopsis IP.
Signed-off-by: Heiko Stuebner
From: Heiko Stuebner
This adds the glue code for the MIPI DSI2 bridge on Rockchip SoCs and
enables its use on the RK3588.
Right now the DSI2 controller is always paired with a DC-phy based on a
Samsung IP, so the interface values are set statically for now.
This stays true for the upcoming
From: Heiko Stuebner
Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
DSI2 host controller, based on the Rockchip version from the driver
rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs.
While the driver is heavily modelled after the previous IP,
and use FIELD_PREP instead
- use dev_err instead of DRM_DEV_ERROR
Heiko Stuebner (3):
drm/bridge/synopsys: Add MIPI DSI2 host controller bridge
dt-bindings: display: rockchip: Add schema for RK3588 DW DSI2
controller
drm/rockchip: Add MIPI DSI2 glue driver for RK3588
.../rockchip
_DEV_ERROR
Heiko Stuebner (3):
drm/bridge/synopsys: Add MIPI DSI2 host controller bridge
dt-bindings: display: rockchip: Add schema for RK3588 DW DSI2
controller
drm/rockchip: Add MIPI DSI2 glue driver for RK3588
.../rockchip/rockchip,rk3588-mipi-dsi2.yaml | 119 ++
drivers/gpu/drm/bridg
From: Heiko Stuebner
The Display Serial Interface 2 (DSI-2) is part of a group of communication
protocols defined by the MIPI Alliance. The RK3588 implements this
specification in its two MIPI DSI-2 Host Controllers that are based on a
new Synopsis IP.
Reviewed-by: Rob Herring (Arm)
Signed-off
From: Heiko Stuebner
Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
DSI2 host controller, based on the Rockchip version from the driver
rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs.
While the driver is heavily modelled after the previous IP,
From: Heiko Stuebner
This adds the glue code for the MIPI DSI2 bridge on Rockchip SoCs and
enables its use on the RK3588.
Right now the DSI2 controller is always paired with a DC-phy based on a
Samsung IP, so the interface values are set statically for now.
This stays true for the upcoming
re checkpatch warnings
Best regards,
--
Heiko Stuebner
ock source to VOP2 on RK3588
commit: eb4262203d7d85eb7b6f2696816db272e41f5464
Best regards,
--
Heiko Stuebner
phy0 other than
> hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
>
> [...]
Applied, thanks!
[1/2] dt-bindings: display: rockchip: Fix label name of hdptxphy for RK3588
HDMI TX Controller
commit: 81dde32e7266e7132076b886337bd29b4648e542
Best regards,
--
Heiko Stuebner
phy0 other than
> hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
>
> [...]
Applied, thanks!
[2/2] arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
commit: 2efdb041019fd6c58abefba3eb6fdc4d659e576c
Best regards,
--
Heiko Stuebner
y if_pixclk_rate computation
commit: 9f40d7a94427a503e303b2a2d8db227d615e32c1
[3/5] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0
commit: 2c1268e7aad0819f38e56134bbc2095fd95fde1b
Best regards,
--
Heiko Stuebner
: dts: rockchip: Enable HDMI1 on rock-5b
commit: 77cea7ca13680e14119a3b9635c7ef16cd7ee44e
Best regards,
--
Heiko Stuebner
On Fri, 06 Dec 2024 19:42:33 +0800, Guoqing Jiang wrote:
> It is not needed since drm_atomic_helper_shutdown checks it.
>
>
Applied, thanks!
[1/1] drm/rockchip: Remove unnecessary checking
commit: 8ddc8dfb8329349d5efb0418c9f20025333e2d98
Best regards,
--
Heiko Stuebner
commit: 19851fa2ba9824bede16f55234f63d9423897c3d
Best regards,
--
Heiko Stuebner
anged in atomic_enable
commit: 9c22b6ece2e5c2308f41ba4bec27cfa158397fa7
Best regards,
--
Heiko Stuebner
Hi Andy,
Am Montag, 9. Dezember 2024, 13:29:17 CET schrieb Andy Yan:
> From: Andy Yan
>
> Every layer of vop2 should bind a window, and we also need to make
> sure that this window is not used by other layer.
>
> 0x5 is a reserved layer sel value on rk3568, but it will select
> Cluster3 on rk35
s.
>
> ** IMPORTANT **
>
> [...]
Applied, thanks!
[1/4] drm/rockchip: dw_hdmi_qp: Add support for RK3588 HDMI1 output
commit: 0f818db20c77506ddd870761785740f8230a4207
Best regards,
--
Heiko Stuebner
From: Heiko Stuebner
Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
DSI2 host controller, based on the Rockchip version from the driver
rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs.
While the driver is heavily modelled after the previous IP,
nges in v2:
- clean up includes (Diederik)
- fix Kconfig description (Diederik)
- constant naming (Diederik)
- binding fixes (paths, sorting, labels) (Rob)
- move to use regmap
- drop custom UPDATE macro and use FIELD_PREP instead
- use dev_err instead of DRM_DEV_ERROR
Heiko Stuebner (3):
drm/bridge/syn
From: Heiko Stuebner
This adds the glue code for the MIPI DSI2 bridge on Rockchip SoCs and
enables its use on the RK3588.
Right now the DSI2 controller is always paired with a DC-phy based on a
Samsung IP, so the interface values are set statically for now.
This stays true for the upcoming
From: Heiko Stuebner
The Display Serial Interface 2 (DSI-2) is part of a group of communication
protocols defined by the MIPI Alliance. The RK3588 implements this
specification in its two MIPI DSI-2 Host Controllers that are based on a
new Synopsys IP.
Tested-by: Dmitry Yashin
Reviewed-by: Rob
hanks!
[02/18] drm/rockchip: vop2: Fix cluster windows alpha ctrl regsiters offset
commit: 17b4b10a0df1a1421d5fbdc03bad0bd3799bc966
[03/18] drm/rockchip: vop2: Fix the mixer alpha setup for layer 0
commit: 6b4dfdcde3573a12b72d2869dabd4ca37ad7e9c7
Best regards,
--
Heiko Stuebner
On Tue, 10 Dec 2024 00:10:18 +0100, Heiko Stuebner wrote:
> This series adds a bridge and glue driver for the DSI2 controller found
> in the rk3588 soc from Rockchip, that is based on a Synopsis IP block.
>
> As the manual states:
> The Display Serial Interface 2 (DSI-2) is par
ster windows on rk3566/8
commit: df063c0b8ffbdca486ab2f802e716973985d8f86
[06/16] drm/rockchip: vop2: Add check for 32 bpp format for rk3588
commit: 7e8a56c703c67bfa8d3f71a0c1c297bb1252b897
[07/16] drm/rockchip: vop2: include rockchip_drm_drv.h
commit: 77b1ccb2a27c7b3b118a03bf1730def92070d31b
Best regards,
--
Heiko Stuebner
hanks!
[01/16] drm/rockchip: vop2: Add debugfs support
commit: 779964556c64cd3d76ddfeb34738ef78020fae84
[02/16] drm/rockchip: vop2: Fix the windows switch between different layers
commit: 0ca953ac226eaffbe1a795f5e517095a8d494921
Best regards,
--
Heiko Stuebner
yright description
commit: 041c664da0691a72aca67f72ab6a13789631358e
Best regards,
--
Heiko Stuebner
o incorrect timings for
> DDC, CEC, and HDCP signal generation.
>
> [...]
Applied, thanks!
[1/1] drm/rockchip: Don't change hdmi reference clock rate
commit: 1854df7087be70ad54e24b2e308d7558ebea9f27
Best regards,
--
Heiko Stuebner
chip: vop2: Support 32x8 superblock afbc
commit: 938fbb16aba8f7b88e0fdcf56f315a5bbad41aad
Best regards,
--
Heiko Stuebner
Am Dienstag, 24. Dezember 2024, 10:49:09 CET schrieb Kever Yang:
> rk3562 has 1 ARM Mali-G52 GPU,.
>
> Signed-off-by: Kever Yang
> ---
>
> Changes in v2: None
>
> Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --g
hanks!
[1/1] (drm/rockchip): Consistently use rk3399 registers consts
commit: d74cc229cfbbc5a96139825c297f34accd670bce
Best regards,
--
Heiko Stuebner
inconsistent display contents may be seen on the screen.
>
>
Applied, thanks!
[1/1] drm/rockchip: vop2: Make overlay layer select register configuration take
effect by vsync
commit: c5996e4ab109c8bb5541453b20647eaaf9350f41
Best regards,
--
Heiko Stuebner
Applied, thanks!
[1/1] dt-bindings: display: rockchip,vop: Drop assigned-clocks
commit: 64e6121dc1b18a8208faf5b26efb50206722fd8e
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--
Heiko Stuebner
hip_resume
commit: 1d34597a1e23004c7dd0ab5f58ba1ef95fd9ded5
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--
Heiko Stuebner
On Wed, 12 Mar 2025 14:42:10 +0800, Andy Yan wrote:
> This is a copy-paste error, which affects DP1 usage.
>
>
Applied, thanks!
[1/1] drm/rockchip: vop2: Fix interface enable/mux setting of DP1 on rk3588
commit: 210db264cf87da8908c395b44170f04469009035
Best regards,
--
Heiko Stuebner
ble eDP0 display on RK3588S EVB1 board
commit: 53862b991e79d8816d5ff54b5954d6a0fe1dcd4c
Best regards,
--
Heiko Stuebner
From: Heiko Stuebner
The panel can be connected to via graph nodes, so allow the port property.
This fixes dtc checker warnings like:
>> arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-haikou-video-demo.dtb:
>> panel@0 (leadtek,ltk050h3148w): 'port' does not ma
From: Heiko Stuebner
The panel can be connected to via graph nodes, so allow the port property.
Signed-off-by: Heiko Stuebner
---
.../devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display
Working on an upcoming board dts, I noticed a dtc check warning
about the port node and at the same time the kernel-test-robot
noticed the same warning with a overlay I added recently.
So allow the port node in the binding of two leadtek displays
to fix that.
Heiko Stuebner (2):
dt-bindings
1c0285e06eeb
Andy suggested a name change for a function in patch2.
Best regards,
--
Heiko Stuebner
1c40af51d4a8cd804eaaf9
[6/7] Revert "ARM: dts: rockchip: drop grf reference from rk3036 hdmi"
commit: dd6c77864aa69ba1079998c590b552e35649d51b
Best regards,
--
Heiko Stuebner
; OF [=n]
> Selected by [y]:
> - DRM_ROCKCHIP [=y] && HAS_IOMEM [=y] && DRM [=y] && ROCKCHIP_IOMMU [=y] &&
> ROCKCHIP_ANALOGIX_DP [=y]
>
> [...]
Applied, thanks!
[1/1] drm/rockchip: add CONFIG_OF dependency
commit: 4f1a965d592a0ca7d4ee2125f54d19ba8292295a
Best regards,
--
Heiko Stuebner
the compilation test.
>
>
> [...]
Applied, thanks!
[1/1] drm/rockchip: rk3066_hdmi: switch to drm bridge
commit: 57d6811e8a6d179aeadb7f102369d1ddefe5aae0
Best regards,
--
Heiko Stuebner
ca75c6cfe1478ab
[4/7] drm/rockchip: inno-hdmi: Fix video timing HSYNC/VSYNC polarity setting
for rk3036
commit: ad10b82c2bcac7f87ac6eaecfca33378b43425ee
Best regards,
--
Heiko Stuebner
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