Am Mittwoch, 10. Februar 2021, 12:10:14 CEST schrieb Heiko Stuebner:
> The rk3399 has two ISPs and right now only the first one is usable.
> The second ISP is connected to the TXRX dphy on the soc.
>
> The phy of ISP1 is only accessible through the DSI controller's
> io-memory, so this series adds
Hi Peter,
Am Mittwoch, 11. August 2021, 00:31:24 CEST schrieb Peter Geis:
> Good Evening,
>
> I've been attempting to light off the feiyang fy07024di26a30d panel on
> the rockpro64. This is the official panel from the Pine64 store.
> I've confirmed it works with the downstream kernel on both the
Am Montag, 15. Februar 2021, 15:33:19 CET schrieb Helen Koike:
> > From: Heiko Stuebner
> > diff --git a/drivers/gpu/drm/rockchip/Kconfig
> > b/drivers/gpu/drm/rockchip/Kconfig
> > index cb25c0e8fc9b..3094d4533ad6 100644
> > --- a/drivers/gpu/drm/rockchip/Kconfig
> > +++ b/drivers/gpu/drm/rockchi
Am Mittwoch, 3. Februar 2021, 10:13:06 CET schrieb Jagan Teki:
> Usual I2C configured DSI bridge drivers have drm_bridge_add
> in probe and mipi_dsi_attach in bridge attach functions.
>
> With, this approach the drm pipeline is unable to find the
> dsi bridge in stm drm drivers since the dw-mipi-d
Hi Sebastian,
Am Mittwoch, 3. Februar 2021, 19:14:22 CET schrieb Sebastian Fricke:
> Hey Heiko,
>
> I have tested your patch set on my nanoPC-T4, here is a complete log
> with:
> - relevant kernel log entries
> - system information
> - media ctl output
> - sysfs entry information
>
> https://pas
Hi Sebastian,
Am Freitag, 5. Februar 2021, 07:43:35 CET schrieb Sebastian Fricke:
> On 03.02.2021 20:54, Heiko Stübner wrote:
> >Am Mittwoch, 3. Februar 2021, 19:14:22 CET schrieb Sebastian Fricke:
> >> I have tested your patch set on my nanoPC-T4, here is a comp
k-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -61,6 +61,9 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
set ^= enable;
+if (!enable)
+return;
+
if (gate->lock)
spin_lock_irqsave(gate->lock, flags);
else
Am Freitag, 5. Februar 202
Am Mittwoch, 10. Februar 2021, 12:10:14 CET schrieb Heiko Stuebner:
> The rk3399 has two ISPs and right now only the first one is usable.
> The second ISP is connected to the TXRX dphy on the soc.
>
> The phy of ISP1 is only accessible through the DSI controller's
> io-memory, so this series adds
Hi Sebastian,
Am Freitag, 5. Februar 2021, 15:55:56 CET schrieb Heiko Stübner:
> Hi Sebastian,
>
> I did some tests myself today as well and can confirm your
> hdmi related finding - at least when plugged in on boot.
>
> I tried some combinations of camera vs. hdmi and it s
Hi Sebastian,
Am Donnerstag, 11. Februar 2021, 06:25:15 CET schrieb Sebastian Fricke:
> Hey Heiko,
>
> On 10.02.2021 12:15, Heiko Stübner wrote:
> >Hi Sebastian,
> >
> >Am Freitag, 5. Februar 2021, 15:55:56 CET schrieb Heiko Stübner:
> >> Hi Sebastian,
> &
Am Samstag, 24. Oktober 2020, 05:53:21 CET schrieb Jonathan Liu:
> Error message incorrectly refers to grf clock instead of vpll clock.
>
> Signed-off-by: Jonathan Liu
applied to drm-misc-next
Thanks
Heiko
___
dri-devel mailing list
dri-devel@lists.
Hi Michael,
Am Dienstag, 13. Juli 2021, 10:44:00 CEST schrieb Michael Riesch:
> The HDMI TX block in the RK3568 requires two power supplies, which have
> to be enabled in some cases (at least on the RK3568 EVB1 the voltages
> VDDA0V9_IMAGE and VCCA1V8_IMAGE are disabled by default). It would be
>
Am Donnerstag, 24. Juni 2021, 11:55:02 CEST schrieb Thomas Zimmermann:
> Moving the driver-specific mmap code into a GEM object function allows
> for using DRM helpers for various mmap callbacks.
>
> The respective rockchip functions are being removed. The file_operations
> structure fops is now b
Am Sonntag, 4. Juli 2021, 16:03:09 CEST schrieb Jagan Teki:
> Finding panel_or_bridge might vary based on associated
> DSI devices like DSI panel, bridge, and I2C based DSI
> bridge.
>
> 1. DSI panels and bridges will invoke the host attach
>from probe in order to find the panel_or_bridge.
>
Hi,
looks like I wasn't in the original recipient list, so only got Nick's
answer.
Am Mittwoch, 9. März 2022, 00:10:31 CET schrieb Nick Desaulniers:
> On Mon, Mar 7, 2022 at 10:17 AM Colin Ian King wrote:
> >
> > The pointer connector is being assigned a value that is never read,
> > it is being
Hi,
Am Mittwoch, 8. September 2021, 15:53:56 CEST schrieb Chris Morgan:
> From: Chris Morgan
>
> After commit 928f9e268611 ("clk: fractional-divider: Hide
> clk_fractional_divider_ops from wide audience") was merged it appears
> that the DSI panel on my Odroid Go Advance stopped working. Upon cl
Hi Maxime,
Am Freitag, 17. September 2021, 20:09:25 CEST schrieb Maxime Ripard:
> By depending on devm_drm_panel_bridge_add(), devm_drm_of_get_bridge()
> introduces a circular dependency between the modules drm (where
> devm_drm_of_get_bridge() ends up) and drm_kms_helper (where
> devm_drm_panel_b
Hi,
Am Dienstag, 21. September 2021, 17:04:10 CEST schrieb Palmer Dabbelt:
> On Tue, 21 Sep 2021 02:12:17 PDT (-0700), he...@sntech.de wrote:
> > On Fri, 10 Sep 2021 20:43:18 -0700, Palmer Dabbelt wrote:
> >> cdn_dp_resume is only used under PM_SLEEP, and now that it's static an
> >> unused functi
Hi Alex,
Am Mittwoch, 22. September 2021, 18:35:38 CEST schrieb Alex Bee:
> Hi Colin,
> Am 22.09.21 um 13:24 schrieb Colin King:
> > From: Colin Ian King
> >
> > The pointer connector is being assigned a value that is never
> > read, it is being updated immediately afterwards. The assignment
> >
Am Montag, 17. Januar 2022, 08:44:37 CET schrieb Chen-Yu Tsai:
> On Sat, Jan 15, 2022 at 7:03 AM Brian Norris wrote:
> >
> > Commit b18c6c3c7768 ("ASoC: rockchip: cdn-dp sound output use spdif")
> > switched the platform to SPDIF, but we didn't fix up the device tree.
> >
> > Drop the pinctrl sett
Am Mittwoch, 26. Januar 2022, 15:55:46 CET schrieb Sascha Hauer:
> The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or
> cpll. gpll and cpll also drive many other clocks, so changing the
> dclk_vop[012] clocks could change these other clocks as well. Drop
> CLK_SET_RATE_PARENT to
Hi Peter,
Am Freitag, 7. Januar 2022, 06:13:33 CET schrieb Peter Geis:
> Some implementations do not use the reset signal, instead tying it to dvdd.
> Make the reset gpio optional to permit this.
>
> Signed-off-by: Peter Geis
> ---
> drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 11 ++
Am Montag, 31. Januar 2022, 17:54:39 CET schrieb
quentin.sch...@theobroma-systems.com:
> From: Quentin Schulz
>
> Heiko does not work at Theobroma Systems anymore and the boards using
> those panels are downstream, maintained internally by the company, so
> let's relieve Heiko of maintainership
Am Mittwoch, 17. November 2021, 15:33:46 CET schrieb Sascha Hauer:
> With upcoming VOP2 support VOP won't be the only choice anymore, so make
> the VOP driver optional.
>
> Signed-off-by: Sascha Hauer
> ---
> arch/arm/configs/multi_v7_defconfig | 1 +
> arch/arm64/configs/defconfig
Am Mittwoch, 17. November 2021, 15:50:54 CET schrieb Sascha Hauer:
> On Wed, Nov 17, 2021 at 03:40:26PM +0100, Heiko Stübner wrote:
> > Am Mittwoch, 17. November 2021, 15:33:46 CET schrieb Sascha Hauer:
> > > With upcoming VOP2 support VOP won't be the only choice anymore
Hi Kever,
Am Donnerstag, 18. November 2021, 02:27:10 CET schrieb Kever Yang:
> Hi Sascha Hauer,
>
> On 2021/11/17 下午10:33, Sascha Hauer wrote:
> > This series adds initial graphics support for the Rockchip RK356[68]
> > SoCs. Graphics support is based around the VOP2 controller which
> > replace
Am Freitag, 26. November 2021, 08:40:21 CET schrieb Sascha Hauer:
> On Thu, Nov 25, 2021 at 09:25:28PM +0100, Johan Jonker wrote:
> > Hi Sascha,
> >
> >
> > On 11/17/21 3:33 PM, Sascha Hauer wrote:
> > > The VOP2 is the display output controller on the RK3568. Add the node
> > > for it to the dts
Hi Sascha,
Am Donnerstag, 2. Dezember 2021, 16:34:49 CET schrieb Sascha Hauer:
> On Wed, Nov 17, 2021 at 09:19:38AM -0600, Rob Herring wrote:
> > On Wed, Nov 17, 2021 at 8:34 AM Sascha Hauer wrote:
> > >
> > > This enabled the VOP2 display controller along with hdmi and the
> > > required port ro
Hi Sascha,
Am Mittwoch, 8. Dezember 2021, 16:12:30 CET schrieb Sascha Hauer:
> On the rk3568 we have this (simplified) situation:
>
> .. .-..-.
> -| hpll |--.--| /n ||dclk_vop0|-
> `´ | `-´`-´
> | .-..-.
Hi David,
Am Montag, 6. Dezember 2021, 22:26:50 CET schrieb David Heidelberg:
> Convert into YAML format into format, which can be validated.
>
> Changes:
> - drop panel from example
the patch subject is strange, talking about a "power domain node".
That needs a fix.
Some more things below.
Am Montag, 20. Dezember 2021, 12:06:28 CET schrieb Sascha Hauer:
> Add a device node to drm_encoder which corresponds with the port node
> in the DT description of the encoder. This allows drivers to find the
> of_graph link between a crtc and an encoder.
>
> Signed-off-by: Sascha Hauer
> ---
>
Am Mittwoch, 22. Dezember 2021, 14:52:51 CET schrieb Rob Herring:
> On Wed, Dec 22, 2021 at 6:47 AM Sascha Hauer wrote:
> >
> > On Tue, Dec 21, 2021 at 10:31:23AM -0400, Rob Herring wrote:
> > > On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> > > > "vpll" is a misnomer. A clock inp
Am Dienstag, 2. August 2016, 10:16:04 schrieb Yakir Yang:
> Hi Mark & Heiko,
>
> Ping..
devicetree side looks good, so we're waiting on Mark to pick up patch 1.
Heiko
> On 06/15/2016 09:28 PM, Yakir Yang wrote:
> > Using the common hdmi-codec driver to support hdmi audio function.
> >
> >
Hi Lin,
Am Freitag, 29. Juli 2016, 15:56:56 schrieb Lin Huang:
> On new rockchip platform(rk3399 etc), there have dcf controller to
> do ddr frequency scaling, and this controller will implement in
> arm-trust-firmware. We add a special clock-type to handle that.
>
> Signed-off-by: Lin Huang
pl
Hi Lin,
Am Freitag, 5. August 2016, 16:50:49 schrieb hl:
> On 2016å¹´08æ05æ¥ 06:37, Heiko Stuebner wrote:
> > Am Freitag, 29. Juli 2016, 15:56:55 schrieb Lin Huang:
> >> From: Heiko Stübner
> >>
> >> add clock flag parameter so we can pass specific clock flag
> >> (like CLK_GET_RATE_NOCACHE
Am Mittwoch, 15. Mai 2019, 20:05:03 CEST schrieb Sean Paul:
> On Wed, May 15, 2019 at 11:01:26AM -0700, Doug Anderson wrote:
> > Hi,
> >
> > On Wed, May 15, 2019 at 10:58 AM Sean Paul wrote:
> >
> > > On Thu, May 02, 2019 at 03:38:07PM -0700, Douglas Anderson wrote:
> > > > On Rockchip rk3288-ba
Am Freitag, 3. Mai 2019, 00:38:08 CEST schrieb Douglas Anderson:
> On Rockchip rk3288-based Chromebooks when you do a suspend/resume
> cycle:
>
> 1. You lose the ability to detect an HDMI device being plugged in.
>
> 2. If you're using the i2c bus built in to dw_hdmi then it stops
> working.
>
>
Am Mittwoch, 8. Mai 2019, 18:09:05 CEST schrieb Sean Paul:
> From: Sean Paul
>
> Another version of the SR helpers for your consumption.
>
> Pretty minor differences between v4 and v3:
> - lots of documentation changes
> - Use connector to get at crtc state in encoders
> - Use the damage helpers
Hi Christoph,
Am Mittwoch, 10. April 2019, 16:10:44 CEST schrieb Christoph Muellner:
> On our RK3399-Q7 EVK base board we have the option to connect an arbitrary
> monitor via DP cable. The actual monitor is therefore not known in advance.
> This means, we don't have any panel information besides
Hi Thierry,
Am Dienstag, 13. November 2018, 13:42:05 CET schrieb Heiko Stuebner:
> From: Heiko Stuebner
>
> This is a panel handled through the generic lvds-panel binding,
> so only needs its additional compatible specified.
>
> Signed-off-by: Heiko Stuebner
just pulling this pending patch ou
Am Freitag, 8. Februar 2019, 12:01:37 CET schrieb Stephen Rothwell:
> Hi all,
>
> In commit
>
> 053ff09f1a8f ("drm/rockchip: rgb: update SPDX license identifier")
>
> Fixes tag
>
> Fixes: 1f0f01515172 ("Add support for Rockchip Soc RGB output interface")
>
> has these problem(s):
>
> -
Am Freitag, 8. Februar 2019, 12:40:22 CET schrieb Stephen Rothwell:
> Hi Heiko,
>
> On Fri, 08 Feb 2019 12:31:38 +0100 Heiko Stübner wrote:
> > we had this warning already from the drm-misc-fixes tree :-) .
>
> Sorry about that ... there goes my memory again :-)
No wo
Hi Boris,
Am Freitag, 14. Juni 2019, 15:53:20 CEST schrieb Boris Brezillon:
> On Thu, 13 Jun 2019 16:22:44 -0300
> Ezequiel Garcia wrote:
>
>
> > +static int vop_gamma_lut_request(struct device *dev,
> > +struct resource *res, struct vop *vop)
> > +{
> > + resource
Am Samstag, 15. Juni 2019, 00:47:29 CEST schrieb Douglas Anderson:
> When fixing up the clock in vop_crtc_mode_fixup() we're not doing it
> quite correctly. Specifically if we've got the true clock 26667 Hz,
> we'll perform this calculation:
>26667 / 1000 => 26
>
> Later when we t
Am Mittwoch, 19. Juni 2019, 00:09:57 CEST schrieb Ezequiel Garcia:
> On Tue, 2019-06-18 at 17:47 -0400, Ilia Mirkin wrote:
> > On Tue, Jun 18, 2019 at 5:43 PM Ezequiel Garcia
> > wrote:
> > > Add an optional CRTC gamma LUT support, and enable it on RK3288.
> > > This is currently enabled via a se
Hi Sam,
Am Freitag, 28. Juni 2019, 19:13:42 CEST schrieb Sam Ravnborg:
> Hi Doug.
>
> > Sam: Oh! I hadn't noticed that you've been added as a panel
> > maintainer in commit ef0db94f94a0 ("MAINTAINERS: Add Sam as reviewer
> > for drm/panel"). Does that mean you are able to provide some advice
>
Hi Jonas,
Am Mittwoch, 20. Februar 2019, 23:40:06 CET schrieb Jonas Karlman:
> NV12 framebuffers produced by the VPU shows distorted on RK3288
> after win has been disabled when scaling is active.
>
> This issue can be reproduced using a 1080p modeset by:
> - Scale a 1280x720 NV12 framebuffer to
Lankhorst
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: linux-rockc...@lists.infradead.org
so I've looked up the patch2 that introduces __drm_atomic_helper_crtc_reset
in patchwork and compared results and everything looks as it should be
I thin
Hi Johan,
Am Mittwoch, 6. März 2019, 23:41:10 CET schrieb Johan Jonker:
> From: Zheng Yang
>
> The RK3066 HDMI TX serves as interface between a LCD Controller and
> a HDMI bus. A HDMI TX consists of one HDMI transmitter controller and
> one HDMI transmitter PHY. The interface has three (3) 8-bit
Hi,
Am Dienstag, 26. März 2019, 21:44:56 CET schrieb Sean Paul:
> From: Sean Paul
>
> Instead of rolling our own implementation for tracking when PSR should
> be [in]active, use the new self refresh helpers to do the heavy lifting.
I only got patches 3-5 and had to pull 1+2 from patchwork, the
Am Freitag, 29. März 2019, 20:00:10 CET schrieb Sean Paul:
> On Fri, Mar 29, 2019 at 07:51:51PM +0100, Heiko Stübner wrote:
> > Hi,
> >
> > Am Dienstag, 26. März 2019, 21:44:56 CET schrieb Sean Paul:
> > > From: Sean Paul
> > >
> > > Instead of
Am Donnerstag, 28. März 2019, 18:17:05 CET schrieb Douglas Anderson:
> From: Sean Paul
>
> This patch adds the ability to override the typical display timing for a
> given panel. This is useful for devices which have timing constraints
> that do not apply across the entire display driver (eg: to
Am Donnerstag, 28. März 2019, 18:17:07 CET schrieb Douglas Anderson:
> Convert the Innolux n116bge from using a fixed mode to specifying a
> display timing with min/typ/max values.
>
> Note that the n116bge's datasheet doesn't fit too well into DRM's way
> of specifying things. Specifically the p
Am Donnerstag, 28. März 2019, 18:17:09 CET schrieb Douglas Anderson:
> Let's document the display timings that jerry has been using out in
> the field. This uses the standard blankings but a slightly slower
> clock rate, thus getting a refresh rate 58.3 Hz.
>
> NOTE: this won't really do anything
Am Montag, 1. April 2019, 19:17:24 CEST schrieb Douglas Anderson:
> Just like we did for rk3288-veyron-chromebook, we want to be able to
> use one of the fixed PLLs in the system to make the pixel clock for
> minnie.
>
> Specifying these timings matches us with how the display is used on
> the dow
Am Montag, 1. April 2019, 19:17:23 CEST schrieb Douglas Anderson:
> Let's document the display timings that most veyron chromebooks (like
> jaq, jerry, mighty, speedy) have been using out in the field. This
> uses the standard blankings but a slightly slower clock rate, thus
> getting a refresh ra
Am Montag, 1. April 2019, 19:17:20 CEST schrieb Douglas Anderson:
> From: Sean Paul
>
> This patch adds an override mode for kevin devices. The mode increases
> both back porches to allow a pixel clock of 2kHz as opposed to the
> 'typical' value of 252750kHz. This is needed to avoid interfere
Am Donnerstag, 11. Juli 2019, 23:27:44 CEST schrieb Heiko Stübner:
> Am Montag, 1. April 2019, 19:17:23 CEST schrieb Douglas Anderson:
> > Let's document the display timings that most veyron chromebooks (like
> > jaq, jerry, mighty, speedy) have been using out in the field
Am Montag, 31. Januar 2022, 09:10:42 CET schrieb Sascha Hauer:
> On Sat, Jan 29, 2022 at 06:48:13PM +0100, Heiko Stübner wrote:
> > Am Mittwoch, 26. Januar 2022, 15:55:46 CET schrieb Sascha Hauer:
> > > The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or
&g
Am Mittwoch, 9. Februar 2022, 10:53:29 CET schrieb Sascha Hauer:
> The driver returns an error when devm_phy_optional_get() fails leaving
> the previously enabled clock turned on. Change order and enable the
> clock only after the phy has been acquired.
>
> Signed-off-by: Sascha Hauer
just a not
Am Mittwoch, 9. Februar 2022, 10:53:39 CET schrieb Sascha Hauer:
> From: Douglas Anderson
>
> The previous tables for mpll_cfg and curr_ctrl were created using the
> 20-pages of example settings provided by the PHY vendor. Those
> example settings weren't particularly dense, so there were places
Hi Michael,
Am Mittwoch, 9. Februar 2022, 16:46:28 CET schrieb Michael Riesch:
> Hi Rob,
>
> On 2/9/22 16:35, Rob Herring wrote:
> > On Wed, 09 Feb 2022 09:51:06 +0100, Michael Riesch wrote:
> >> From: Alex Bee
> >>
> >> The Bifrost GPU in Rockchip RK356x SoCs has a core and a bus clock.
> >> Re
Am Donnerstag, 10. Februar 2022, 14:37:59 CET schrieb Sascha Hauer:
> On Thu, Feb 10, 2022 at 02:15:17PM +0100, Johan Jonker wrote:
> >
> >
> > On 2/10/22 12:47, Sascha Hauer wrote:
> > > On Thu, Feb 10, 2022 at 01:10:32AM +0100, Johan Jonker wrote:
> > >> Hi Sascha,
> > >>
> > >> Something with
Am Montag, 14. Februar 2022, 07:08:09 CET schrieb Yong Wu:
> Use the common compare helper from component.
>
> Cc: Sandy Huang
> Cc: "Heiko St¨¹bner"
> Cc: linux-rockc...@lists.infradead.org
> Signed-off-by: Yong Wu
Acked-by: Heiko Stuebner
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_drv.
Am Donnerstag, 17. Februar 2022, 14:58:23 CET schrieb Sascha Hauer:
> Hi Andy,
>
> Please trim the context in your answers to the relevant parts, it makes
> it easier to find the things you said.
>
> On Thu, Feb 17, 2022 at 08:00:11PM +0800, Andy Yan wrote:
> > Hi Sascha:
> >
> > > +
> > > + drm
Am Freitag, 22. April 2022, 09:28:28 CEST schrieb Sascha Hauer:
> From: Douglas Anderson
>
> The previous tables for mpll_cfg and curr_ctrl were created using the
> 20-pages of example settings provided by the PHY vendor. Those
> example settings weren't particularly dense, so there were places
Am Freitag, 22. April 2022, 09:28:33 CEST schrieb Sascha Hauer:
> The VOP2 is the display output controller on the RK3568. Add the node
> for it to the dtsi file along with the required display-subsystem node
> and the iommu node.
>
> Signed-off-by: Sascha Hauer
> Acked-by: Rob Herring
> ---
>
Am Donnerstag, 5. Mai 2022, 08:41:31 CEST schrieb Sascha Hauer:
> On Thu, May 05, 2022 at 02:28:24AM +0200, Heiko Stübner wrote:
> > Am Freitag, 22. April 2022, 09:28:33 CEST schrieb Sascha Hauer:
> > > The VOP2 is the display output controller on the RK3568. Add the node
> &
Hi Sascha,
Am Montag, 9. Mai 2022, 10:37:35 CEST schrieb Sascha Hauer:
> This is not the full series, if you want that, look for v11.
>
> This series merely has a last-minute change: The VOP2 driver used
> platform_get_resource_byname() to get its registers, but the reg-names
> property hasn't be
Am Montag, 9. Mai 2022, 11:55:59 CEST schrieb Sascha Hauer:
> On Mon, May 09, 2022 at 10:44:17AM +0200, Heiko Stübner wrote:
> > Hi Sascha,
> >
> > Am Montag, 9. Mai 2022, 10:37:35 CEST schrieb Sascha Hauer:
> > > This is not the full series, if you want that, l
Hi Sascha,
Am Dienstag, 10. Mai 2022, 09:09:12 CEST schrieb Sascha Hauer:
> The VOP2 driver relies on reg-names properties, but these are not
> documented. Add the missing documentation, make reg-names mandatory
> and increase minItems to 2 as always both register spaces are needed.
>
> Signed-of
Am Dienstag, 17. Mai 2022, 11:02:06 CEST schrieb Krzysztof Kozlowski:
> On 14/05/2022 00:26, Heiko Stuebner wrote:
> > Hi Rob, Krzysztof,
> >
> > Am Mittwoch, 11. Mai 2022, 10:21:07 CEST schrieb Sascha Hauer:
> >> The VOP2 driver relies on reg-names properties, but these are not
> >> documented. A
Hi Conor,
Am Montag, 27. Juni 2022, 21:39:49 CEST schrieb Conor Dooley:
> From: Conor Dooley
>
> A dt-schema binding for the Ilitek ili9341 was created as
> panel/ilitek,ili9341.yaml but the txt binding was ignored in the
> process. Move the remaining items in the txt binding to the yaml one &
>
Am Dienstag, 28. Juni 2022, 17:00:56 CEST schrieb Heiko Stübner:
> Hi Conor,
>
> Am Montag, 27. Juni 2022, 21:39:49 CEST schrieb Conor Dooley:
> > From: Conor Dooley
> >
> > A dt-schema binding for the Ilitek ili9341 was created as
> > panel/ilitek,ili9341.yam
Am Donnerstag, 1. September 2022, 14:47:10 CEST schrieb Jani Nikula:
> Calling drm_connector_update_edid_property() should be done
> unconditionally instead of depending on the number of modes added. Also
> match the call order in inno_hdmi and rk3066_hdmi.
>
> Cc: Sandy Hua
Am Donnerstag, 1. September 2022, 14:47:11 CEST schrieb Jani Nikula:
> Prefer the parsed results for has_audio in display info over calling
> drm_detect_monitor_audio().
>
> Cc: Sandy Huang
> Cc: Heiko Stübner
> Signed-off-by: Jani Nikula
Reviewed-by: Heiko Stuebner
> -
Am Dienstag, 6. September 2022, 19:48:20 CEST schrieb Chris Morgan:
> From: Chris Morgan
>
> Add a compatible string for the rk3568 dsi-dphy.
>
> Signed-off-by: Chris Morgan
Reviewed-by: Heiko Stuebner
> ---
> .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 +
> 1 file
Am Dienstag, 6. September 2022, 19:48:22 CEST schrieb Chris Morgan:
> From: Chris Morgan
>
> Add support for the Rockchip RK3568 DSI-DPHY. Registers were taken from
> the BSP kernel driver and wherever possible cross referenced with the
> TRM.
With the amount of refactoring done below, I'd expec
Hi,
[it seems your Reply-To mail header is set strangely as
Reply-To: 20191107133851.GF63329@art_vandelay
which confuses my MTA]
Am Freitag, 8. November 2019, 13:46:30 CET schrieb Wambui Karuga:
> On Thu, Nov 07, 2019 at 08:38:51AM -0500, Sean Paul wrote:
> > On Thu, Nov 07, 2019 at 01:54:22AM -0
Hi Daniel, Sandy,
Am Mittwoch, 9. Oktober 2019, 16:50:08 CET schrieb Daniel Vetter:
> On Thu, Sep 26, 2019 at 04:24:47PM +0800, Sandy Huang wrote:
> > These new format is supported by some rockchip socs:
> >
> > DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10
> > DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10
> > D
Am Freitag, 13. Dezember 2019, 18:26:08 CET schrieb Daniel Vetter:
> Checking both is one too much, so wrap a WARN_ON around it to stope
> the copypasta.
>
> Signed-off-by: Daniel Vetter
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: linux-arm-ker...@lists.
Hi Miquel,
Am Freitag, 13. Dezember 2019, 19:10:49 CET schrieb Miquel Raynal:
> Add the display subsystem routes with the two available CRTCs: vopb
> and vopl (big and little). For each CRTC, add the LVDS endpoints. MIPI
> DSI endpoints will come later.
>
> Signed-off-by: Miquel Raynal
> ---
>
Hi Sam,
thanks for the thorough review :-)
Am Samstag, 14. Dezember 2019, 09:17:30 CET schrieb Sam Ravnborg:
> > +#define dsi_generic_write_seq(dsi, cmd, seq...) do {
> > \
> > + static const u8 d[] = { seq }; \
> > + int ret;
Am Dienstag, 17. Dezember 2019, 15:24:46 CET schrieb Maxime Ripard:
> Hi,
>
> On Tue, Dec 17, 2019 at 03:07:02PM +0100, Heiko Stuebner wrote:
> > From: Heiko Stuebner
> >
> > The XPP055C272 is a 5.5" 720x1280 DSI display.
> >
> > changes in v2:
> > - add size info into binding title (Sam)
> > - a
Hi Maxime,
Am Dienstag, 17. Dezember 2019, 17:01:22 CET schrieb Maxime Ripard:
> On Tue, Dec 17, 2019 at 04:08:49PM +0100, Heiko Stübner wrote:
> > Am Dienstag, 17. Dezember 2019, 15:24:46 CET schrieb Maxime Ripard:
> > > Hi,
> > >
> > > On Tue, Dec 17, 2019
Hi Yannick,
Am Freitag, 20. Dezember 2019, 16:52:47 CET schrieb Yannick FERTRE:
> Hello Heiko,
> I test with success your patch on a board stm32mp1 with a panel raydium
> rm68200.
> I need more time to test with a HDMI bridge like ad7533.
I guess this was too short before the holiday season, so
Am Sonntag, 5. Januar 2020, 15:05:26 CET schrieb Heiko Stuebner:
> Am Dienstag, 24. Dezember 2019, 15:38:49 CET schrieb Miquel Raynal:
> > Hello,
> >
> > This series aims at supporting LVDS on PX30.
> >
> > A first couple of patches update the documentation with the new
> > compatible and the pre
Hi Jonas,
Am Montag, 6. Januar 2020, 21:48:25 CET schrieb Jonas Karlman:
> Using a destination width that is more then 3840 pixels
> is not supported in scl_vop_cal_scl_fac().
>
> Work around this limitation by filtering all modes with
> a width above 3840 pixels.
could you try to send the whole
Am Montag, 6. Januar 2020, 21:50:02 CET schrieb Jonas Karlman:
> From: Algea Cao
>
> Adding the following freq cfg in 8-bit and 10-bit color depth:
>
> {
> 4000, 6500, 7100, 8350, 8575,
> 8875, 10800, 11900, 16200
> }
>
> New freq has been validated by
Am Mittwoch, 8. Januar 2020, 23:39:49 CET schrieb Tobias Schramm:
> commit 2589c4025f13 ("drm/rockchip: Avoid drm_dp_link helpers") changes
> the type of variables used to store the display port data rate and
> number of lanes to u8. However u8 is not sufficient to store the link
> data rate of the
Am Donnerstag, 10. Oktober 2019, 05:44:52 CEST schrieb Nickey Yang:
> Some VOP's (such as px30) dclk_pol bit is at the last.
> So it is necessary to distinguish dclk_pol and pin_pol.
>
> Signed-off-by: Nickey Yang
on
- px30 with dsi ... fixing the display issue I had
- rk3328 with hdmi
- rk3288
Am Donnerstag, 10. Oktober 2019, 21:43:48 CEST schrieb Ezequiel Garcia:
> New iteration, seems that we are finally converging.
>
> For this v5, we are only doing some changes on
> the gamma_set implementation. As a result, the code
> is more readable. See the changelog in patch 2 for more
> inform
Am Montag, 2. März 2020, 16:58:07 CET schrieb Miquel Raynal:
> Rockchip PX30 SoCs feature a Bifrost Mali GPU.
>
> Signed-off-by: Miquel Raynal
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 +
already in mainline ;-)
https://git.kernel.org/pub/scm/linux/kernel/git/torva
Hi Miquel,
Am Montag, 2. März 2020, 16:58:08 CET schrieb Miquel Raynal:
> PX30 SoCs feature an ARM Bifrost GPU.
>
> Signed-off-by: Miquel Raynal
> ---
>
> Hello, this change is just adding basic GPU support, more work is
> needed on the devfreq/opp side to be sure everything works and is
> prop
Hi Dafna,
Am Dienstag, 21. Januar 2020, 16:43:14 CET schrieb Dafna Hirschfeld:
> convert the binding file rockchip-drm.txt to yaml format.
> This was tested and verified on ARM and ARM64 with:
> make dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/rockchip/rockchip-dr
Am Montag, 25. November 2019, 10:28:12 CET schrieb Neil Armstrong:
> Hi,
>
> On 23/11/2019 21:51, Heiko Stuebner wrote:
> > Hi Neil,
> >
> > Am Samstag, 23. November 2019, 13:38:41 CET schrieb Neil Armstrong:
> >> Le 23/11/2019 à 11:39, Heiko Stuebner a écrit :
> >>> From: Heiko Stuebner
> >>>
>
Am Montag, 25. November 2019, 11:09:39 CET schrieb Neil Armstrong:
> Hi,
>
> On 25/11/2019 10:31, Heiko Stuebner wrote:
> > From: Heiko Stuebner
> >
> > The timing values for dw-dsi are often dependent on the used display and
> > according to Philippe Cornu will most likely also depend on the us
Hi Qiang,
Am Montag, 9. September 2019, 04:30:43 CEST schrieb Qiang Yu:
> Oh, I was miss leading by the drm_gem_reservation_object_wait
> comments. Patch is:
> Reviewed-by: Qiang Yu
>
> I'll apply this patch to drm-misc-next.
>
> Current kernel release is 5.3-rc8, is it too late for this fix to
Am Mittwoch, 3. Juli 2019, 11:51:11 CEST schrieb John Keeping:
> Commit 9a61c54b9bff ("drm/rockchip: vop: group vop registers") seems to
> have unintentionally changed the defintion of this macro. Since it is
> unused, this was not spotted but any attempt to use it results in
> compilation errors.
NXP Linux Team
> Cc: Philipp Zabel
> Cc: Paul Cercueil
> Cc: Chun-Kuang Hu
> Cc: Matthias Brugger
> Cc: Neil Armstrong
> Cc: Kevin Hilman
> Cc: Jerome Brunet
> Cc: Martin Blumenstingl
> Cc: Marek Vasut
> Cc: Stefan Agner
> Cc: Sandy Huang
> Cc:
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