Appears to match latest BSPEC
Reviewed-by: Clint Taylor
-Clint
On 9/3/21 5:35 PM, Matt Roper wrote:
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L
Reviewed-by: Clint Taylor
-Clint
On 11/2/21 3:25 PM, Matt Roper wrote:
The bspec's performance guide suggests programming specific values into
a few registers for optimal performance. Although these aren't
workarounds, it's easiest to handle them inside the GT workaround
f
Looks correct.
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the d
Correct,
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
Coarse power gating for render should not be enabled on some DG2
steppings.
Bspec: 52698
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++
1 file changed, 11
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Ramalingam C
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Matt Atwood
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza
Signed-off-by: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2
On 02/27/2017 09:41 AM, Ville Syrjälä wrote:
On Mon, Feb 27, 2017 at 09:21:09AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian onl
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is a copy of merged i915's
commit e918
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa
On 02/28/2017 03:56 AM, Ville Syrjälä wrote:
On Mon, Feb 27, 2017 at 02:57:58PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian onl
On 02/28/2017 02:58 AM, ayaka wrote:
On 02/28/2017 06:57 AM, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video f
comments of the V6 patch.
-Clint
Ander
Cc: Daniel Stone
Cc: Ville Syrjälä
Signed-off-by: Randy Li
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 21 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/d
attributes properly. Naturally, the workaround of reducing
main link attributes for all devices ended up in regressions for other
devices. So here we are.
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Tested-by: Clinton Taylor
Signed-off-by: J
On 05/11/2017 02:57 AM, Jani Nikula wrote:
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
Fixes
es for all devices ended up in regressions for other
devices. So here we are.
v2: Rebase on DRM DP desc read helpers
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_hel
main link attributes for all devices ended up in
regressions for other devices. So here we are.
v2: Rebase on DRM DP desc read helpers
v3: Fix the OUI memcmp blunder (Clint)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote:
On 05/26/2017 09:15 AM, Daniel Vetter wrote:
Did you look into also wiring this up for dp mst chain
On 05/29/2017 04:06 AM, Jani Nikula wrote:
On Thu, 18 May 2017, Clint Taylor wrote:
On 05/18/2017 04:10 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or
On 05/29/2017 11:53 PM, Hans Verkuil wrote:
For those who are interested in HDMI CEC support I made a little status
document that I intend to keep up to date:
https://hverkuil.home.xs4all.nl/cec-status.txt
My goal is to get CEC supported for any mainlined HDMI driver where
the hardware
supp
On 05/30/2017 09:49 AM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote:
On 05
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at
On 05/30/2017 02:29 PM, Hans Verkuil wrote:
On 05/30/2017 10:32 PM, Clint Taylor wrote:
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017
On 05/26/2017 12:18 AM, Daniel Vetter wrote:
On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote:
From: Hans Verkuil
This adds support for the DisplayPort CEC-Tunneling-over-AUX
feature that is part of the DisplayPort 1.3 standard.
Unfortunately, not all DisplayPort/USB-C to HDMI a
On 01/04/2017 06:00 PM, Ayaka wrote:
從我的 iPad 傳送
Daniel Stone 於 2017年1月5日 上午1:02 寫道：
Hi Randy,
On 4 January 2017 at 16:29, Randy Li wrote:
index 90d2cc8..23c8e99 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,9 @@ const struct drm_format_info
specific sink/branch device that would cover
similar issue.
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Lee, Shawn C (3):
drm: Add support for device_id based detection.
drm: Change limited M/N quirk to constant N quirk
put buffer %s\n",
+ enable ? "enabling" : "disabling");
+
+ return -EIO;
}
EXPORT_SYMBOL(drm_dp_dual_mode_set_tmds_output);
Appears to fix the issue seen on GLK with LSPCON and DMC firmware
loaded. Customer was concerned about the fix being in D
On 08/12/2014 04:07 AM, Ville Syrj?l? wrote:
> On Tue, Jul 29, 2014 at 02:58:23PM -0700, clinton.a.taylor at intel.com wrote:
>> From: Clint Taylor
>>
>> CEA SD interlaced modes use a horizontal 720 pixels that are pixel
>> replicated to 1440. The current driver repor
On 08/25/2014 06:02 AM, Daniel Vetter wrote:
> On Mon, Aug 18, 2014 at 02:02:14PM -0700, clinton.a.taylor at intel.com wrote:
>> From: Clint Taylor
>>
>> Pixel replicated modes should be 720 horizontal pixel and pixel
>> replicated by the HW across the HDMI cable
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