ntk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (6):
extcon: Add EXTCON_DISP_DP and the property for USB Type-C
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
phy: Add USB Type-C PHY driver for rk3399
arm64: dts: rock
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v9:
- modify the reference phy = <&tcphy0 0>, <&tcphy1 0>;
Changes in v8: None
Changes in v7: None
Changes in v6:
- add assigned
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v9:
- do not need reset the
escription
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
Documentation: bindings: add dt doc for Roc
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v10:
- add pclk_vio_grf clock
Changes in v9:
- modify the reference phy = <&tcphy0 0>, <&tcphy1 0>;
Changes in v8: None
Changes in
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v10:
- control the grf_clk
Hi Chanwoo
On 08/10/2016 08:37 AM, Chanwoo Choi wrote:
> Hi Chris,
>
> On 2016ë
08ì 10ì¼ 08:32, Chris Zhong wrote:
>> Hi all
>>
>> This series patch is for rockchip Type-C phy and DisplayPort controller
>> driver.
>>
>> The USB Type-C PHY is des
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v10.1:
- support read sink
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v10.2:
- remove best_encoder
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v11:
- add best_encoder back
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v11:
- add best_encoder back
se extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
phy: Add USB Type-C PHY driver for rk339
unc__ from dev_err
- return err number when get clk failed
- remove ADDR_ADJ define
- use devm_clk_get(&pdev->dev, "tcpdcore")
- add extcon node description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- p
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v12:
- use
rn err number when get clk failed
- remove ADDR_ADJ define
- use devm_clk_get(&pdev->dev, "tcpdcore")
- add extcon node description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_o
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v13:
- support suspend
rn err number when get clk failed
- remove ADDR_ADJ define
- use devm_clk_get(&pdev->dev, "tcpdcore")
- add extcon node description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_o
On 02/02/2017 02:12 AM, Sean Paul wrote:
On Tue, Jan 24, 2017 at 10:27:27AM +0800, Chris Zhong wrote:
Hi Sean
On 01/24/2017 01:48 AM, Sean Paul wrote:
On Fri, Jan 20, 2017 at 06:10:49PM +0800, Chris Zhong wrote:
The MIPI DSI do not need check the validity of resolution, the max
resolution
l.org/patch/9340251
[25/26] https://patchwork.kernel.org/patch/9340127
[26/26] https://patchwork.kernel.org/patch/9340139
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
C
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/rockchip
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 33 -
1 file changed, 16 insertions(+), 17
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16
1 file changed, 16 insertions(+)
diff --git a
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong
Signed-off-by: Mark Yao
that we can not
just call schedule_work conditionally in cdn_dp_pd_event() if the insertion
status changed. The problem would still be seen if a monitor is connected
for the first time during suspend.
Signed-off-by: Guenter Roeck
Signed-off-by: Sean Paul
Signed-off-by: Chris Zhong
---
Changes in
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
[seanpaul fixed up some races between the worker and modeset]
[seanpaul squashed ~15
/9442141/
https://patchwork.kernel.org/patch/9442151/
Changes in v17:
- Correct the clock check condition
- Correct the coding style
- change LANE_REF_CYC to 0x8000
Chris Zhong (4):
drm/rockchip: cdn-dp: add cdn DP support for rk3399
drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_event
drm
system crash. replace drm_helper_hpd_irq_event with
drm_kms_helper_hotplug_event, only update cdn-dp status.
Signed-off-by: Chris Zhong
Tested-by: Guenter Roeck
Reviewed-by: Guenter Roeck
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.c | 9 -
1 file changed, 8
-power on, and wait for a while until it is ready to
DPCD communication.
Signed-off-by: Chris Zhong
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.c | 91 +++---
drivers/gpu/drm/rockchip/cdn-dp-core.h | 1 +
2 files changed, 52 insertions(+), 40 deletions
With atomic modesetting the hardware will be powered off when the
mode_set function is called. We should configure the hardware in the
enable function.
Signed-off-by: Chris Zhong
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.c | 49 +-
1 file
[] ret_from_fork+0x10/0x40
Problem is two-fold: The worker should not run while suspended, and the
suspend function should not call cdn_dp_disable() while the worker is
running.
Signed-off-by: Guenter Roeck
Signed-off-by: Sean Paul
Signed-off-by: Chris Zhong
---
Changes in v17: None
drivers
From: Jeffy Chen
We're trying to lock mutex when cdn-dp shutdown, so we need to make
sure the mutex is inited in cdn-dp's probe.
Signed-off-by: Jeffy Chen
Reviewed-by: Guenter Roeck
Reviewed-by: Chris Zhong
Signed-off-by: Chris Zhong
---
Changes in v17: None
drivers/gpu/drm/ro
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16
1 file changed, 16 insertions
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 29 ++---
1 file changed, 14
https://patchwork.kernel.org/patch/9544109
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (6):
dt-bindings:
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong
Signed-off-by: Mark Yao
driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Chris Zhong (4):
Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY
arm64: dts: rockchip: add rockchip,uphy-dp-sel for Type-C phy
phy: rockchip-typec: support DP phy switch
drm
: Chris Zhong
---
drivers/phy/phy-rockchip-typec.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c
index 7cfb0f8..1604aaa 100644
--- a/drivers/phy/phy-rockchip-typec.c
+++ b/drivers/phy/phy-rockchip-typec.c
@@ -267,6
driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
Signed-off-by: Chris Zhong
---
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
b
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
Signed-off-by: Chris Zhong
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index
: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-
Hi John
On 01/17/2017 06:54 PM, John Keeping wrote:
On Tue, 17 Jan 2017 17:31:53 +0800, Chris Zhong wrote:
On 01/16/2017 08:44 PM, John Keeping wrote:
On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote:
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
drm/rockchip/dsi: dw-mipi: correct the coding style
drm/rockchip/ds
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong
Signed-off-by: Mark Yao
Hi John
On 02/15/2017 08:39 PM, John Keeping wrote:
On Wed, 15 Feb 2017 11:38:45 +0800, Chris Zhong wrote:
On 01/29/2017 09:24 PM, John Keeping wrote:
In order to fully reset the state of the MIPI controller we must assert
this reset.
This is slightly more complicated than it could be in
Hi John
On 02/01/2017 03:22 AM, Sean Paul wrote:
On Sun, Jan 29, 2017 at 01:24:42PM +, John Keeping wrote:
Reviewed-by: Sean Paul
Signed-off-by: John Keeping
Reviewed-by: Chris Zhong
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
Hi Rob
On 02/16/2017 10:20 AM, Rob Herring wrote:
On Fri, Feb 10, 2017 at 03:44:11PM +0800, Chris Zhong wrote:
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
"dt-bindings: phy:" is the preferred subject prefix.
OK, I will change the header next version.
d
enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support R
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 29 ++---
1 file changed, 14
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong
Signed-off-by: Mark Yao
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16
1 file changed, 16 insertions
Hi Sean
On 02/21/2017 11:39 PM, Sean Paul wrote:
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidt
+0800, Chris Zhong wrote:
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidth fix" patch back, since we really need it.
This patch serial is for RK3399 MIPI DSI
Hi John
I have test this v4 series on my RK3399 board, it works well, thanks.
Tested-by: Chris Zhong
On 02/24/2017 08:54 PM, John Keeping wrote:
This version is mostly small changes in response to review comments from
Sean and Chris, the details are in the individual patches.
I decided to
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong
---
.../bindings/display/panel/innolux,p079zca.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644
Documentation/devic
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-innolux-p079zca.c
In order to analyze some video config failed, add some useful
printouts.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
index 963d8ab
Hi all
This series is to correct some mistakes in clk_get_rate and the register
address. And in order to better develop, adding more prints.
Chris Zhong (3):
drm/rockchip: cdn-dp: return error code when clk_get_rate failed
drm/rockchip: cdn-dp: Correct PHY register address
drm/rockchip
Correct some DP register address for PHY Configuration according to
latest datasheet.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h
b/drivers/gpu/drm
instead of "u32" is better.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 5 +++--
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 2 +-
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/roc
Oh, a slip of the finger :(, the headline should be "RK3399 cdn-dp patches"
On 03/08/2017 10:27 AM, Chris Zhong wrote:
Hi all
This series is to correct some mistakes in clk_get_rate and the register
address. And in order to better develop, adding more prints.
Chris Zhong (3):
dr
Hi Heiko and Brain
On 03/09/2017 09:02 AM, Heiko Stübner wrote:
Am Mittwoch, 8. März 2017, 16:39:23 CET schrieb Brian Norris:
On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote:
There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
only one PHY can connect to DP
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong
---
Changes in v2: None
.../bindings/display/panel/innolux,p079zca.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 1
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong
---
Changes in v2:
- add some error check
- always use Low power mode to send commend
- add comments for all the sleep
- use DRM_DEV_ERROR instead of dev_err
drivers/gpu/drm/panel/Kc
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/rockchip
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu
Hi Heiko
On 03/15/2017 05:03 PM, Heiko Stübner wrote:
Am Mittwoch, 15. März 2017, 16:42:30 CET schrieb Chris Zhong:
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong
---
.../devicetree/bindings/display
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong
---
Changes in v2: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hi all
This series set the phy_cfg_clk to be a required clock for RK3399, and
add a grf clock control in dw-mipi-dsi driver. And then correct a
register name.
Changes in v2:
- check the grf_clk only for RK3399
Chris Zhong (4):
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
dt-bindings
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong
---
Changes in v2:
- check the grf_clk only for RK3399
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 +
1 file changed, 21
Hi John
On 03/16/2017 06:55 PM, John Keeping wrote:
On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote:
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata
only for RK3399
Chris Zhong (4):
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
dt-bindings: add the grf clock for dw-mipi-dsi
drm/rockchip/dsi: enable the grf clk before writing grf registers
drm/rockchip/dsi: correct the grf_switch_reg name
.../display/rockchip
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +-
1 file changed, 1 insertion(+), 1
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.
Signed-off-by: Chris Zhong
---
Changes in v3:
- add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399
Ch
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong
---
Changes in v3:
- add a DW_MIPI_NEEDS_GRF_CLK for RK3399
Changes in v2:
- check the grf_clk only for RK3399
drivers/gpu/drm/rockchip/dw-mipi
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong
Reviewed-by: Brian Norris
---
Changes in v3: None
Changes in v2: None
.../bindings/display/panel/innolux,p079zca.txt | 23 ++
1
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Tested-by: Brian Norris
---
Changes in v3:
- printk err after regulator_disable(innolux->supply)
Changes in v2:
- add some error check
- always use Low po
n v3:
- add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399
- add a DW_MIPI_NEEDS_GRF_CLK for RK3399
Changes in v2:
- check the grf_clk only for RK3399
Chris Zhong (4):
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
dt-bindings: add the grf clock for dw-mipi-dsi
drm/rockchip/dsi: enable the grf clk before writing
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v4:
- print the err after clk_prepare_enable(dsi->grf_clk)
Changes in v3:
- add a DW_MIPI_NEEDS_GRF_CLK
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v4: None
Changes in v3:
-
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v4:
- remove "additional"
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/displa
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong
Reviewed-by: Brian Norris
Reviewed-by: Sean Paul
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Tested-by: Brian Norris
---
Changes in v4:
- remove backlight check after probe
- add bpc info
Changes in v3:
- printk err after regulator_disable(innolux-&g
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong
Reviewed-by: Brian Norris
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../bindings/display/panel/innolux,p079zca.txt
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v14.2:
- Modify some
/8887261/
https://patchwork.kernel.org/patch/8887251/
Chris Zhong (2):
drm/rockchip: cdn-dp: support audio hot-plug
ASoC: rockchip: Add DP dai-links to the rk3399-gru machine driver
.../bindings/sound/rockchip,rk3399-gru-sound.txt | 13 +++---
drivers/gpu/drm/rockchip/cdn-dp-core.c
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