On 11/29/2016 02:34 PM, Laurent Pinchart wrote:
> Most drivers that use bridges forgot to detach them at cleanup time.
> Instead of fixing them one by one, detach the bridge in the core
> drm_encoder_cleanup() function.
>
> Signed-off-by: Laurent Pinchart
> ---
> drivers/gpu/drm/drm_encoder.c |
getting lost. Using the logic
> in __adv7511_power_on/off() which syncs and dirtys the cache
> avoids this issue.
>
> Thus this patch changes the EDID probing logic so that we
> re-use the __adv7511_power_on/off() calls.
>
> Cc: David Airlie
> Cc: Archit Taneja
> Cc: Wol
On 11/29/2016 11:27 PM, Laurent Pinchart wrote:
> Hi Archit,
>
> On Tuesday 29 Nov 2016 15:57:06 Archit Taneja wrote:
>> On 11/29/2016 02:34 PM, Laurent Pinchart wrote:
>>> Instead of linking encoders and bridges in every driver (and getting it
>>> wrong half of
On 06/06/2017 01:41 PM, Neil Armstrong wrote:
Hi Philippe,
On 06/02/2017 04:37 PM, Philippe CORNU wrote:
Add the STM32 DSI host driver that uses the Synopsys DesignWare
MIPI DSI DRM bridge.
Signed-off-by: Philippe CORNU
---
drivers/gpu/drm/stm/Kconfig | 8 +
drivers/gpu/drm/s
On 6/9/2017 6:31 PM, Rob Herring wrote:
On Fri, Jun 09, 2017 at 10:43:07AM +0100, Jose Abreu wrote:
Hello,
On 09-06-2017 05:11, Archit Taneja wrote:
Hi Philippe, Rob,
On 06/08/2017 09:10 PM, Rob Herring wrote:
Seems strange there's not also a pixel or bit clock? Or this
gets driven
On 6/10/2017 2:29 PM, Laurent Pinchart wrote:
The dw-hdmi driver switched to regmap-mmio, but lacks the dependency in
Kconfig. This can result in compilation breakages. Fix it by selecting
REGMAP_MMIO.
Fixes: 80e2f97968b5 ("drm: bridge: dw-hdmi: Switch to regmap for register
access")
Reported
On 06/06/2017 06:28 PM, Tomi Valkeinen wrote:
On 06/06/17 15:48, Boris Brezillon wrote:
Okay. Thanks for the clarification. Can you confirm that this version
is correct?
dsi@xxx {
#address-cells = <1>;
#size-cells = <0>;
ports {
On 06/06/2017 03:50 PM, Boris Brezillon wrote:
Hi Archit,
On Sun, 4 Jun 2017 00:20:06 +0530
Archit Taneja wrote:
+
+#define DPHY_CFG0 0x1b0
+#define DPHY_C_RSTBBIT(20)
+#define DPHY_D_RSTB(x) ((x) << 16)
+#
, make sure that
hdmi_audio_update is only called when we've detected that the monitor
supports HDMI.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 70 --
1 file changed, 67 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm
The display bindings for 8x96 aren't in yet, so it's okay to have these
for 4.13.
Archit Taneja (3):
drm/msm/hdmi: 8996 PLL: Populate unprepare
drm/msm/hdmi: Updated generated headers
drm/msm/hdmi: Fix HDMI pink strip issue seen on 8x96
drivers/gpu/drm/msm/hdmi/hdmi.xm
Without doing anything in unprepare, the HDMI driver isn't able to
switch modes successfully. Calling set_rate with a new rate results
in an un-locked PLL.
If we reset the PLL in unprepare, the PLL is able to lock with the
new rate.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm
idths > 4095 anyway.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 59 -
1 file changed, 38 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 0a97
Signed-off-by: Archit Taneja
---
rnndb/hdmi/hdmi.xml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/rnndb/hdmi/hdmi.xml b/rnndb/hdmi/hdmi.xml
index 2bbae43..76d88a1 100644
--- a/rnndb/hdmi/hdmi.xml
+++ b/rnndb/hdmi/hdmi.xml
@@ -94,6 +94,12 @@ xsi:schemaLocation="
Signed-off-by: Archit Taneja
---
rnndb/hdmi/hdmi.xml | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/rnndb/hdmi/hdmi.xml b/rnndb/hdmi/hdmi.xml
index 69b4828..2bbae43 100644
--- a/rnndb/hdmi/hdmi.xml
+++ b/rnndb/hdmi/hdmi.xml
@@ -457,25 +457,25
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference the NULL in the hotplug path. We also need to register
the connector, so that userspace can get at it.
On 06/15/2017 11:24 PM, Eric Anholt wrote:
ERR_PTR() needs a negative errno argument.
Thanks, I'll queue it to drm-misc-next-fixes once it's opened.
Archit
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/bridge/panel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference the NULL in the hotplug
On 06/19/2017 03:42 PM, Boris Brezillon wrote:
On Tue, 13 Jun 2017 11:02:47 +0200
Andrzej Hajda wrote:
Hi,
Just spotted this thread.
On 06.06.2017 14:58, Tomi Valkeinen wrote:
On 06/06/17 15:48, Boris Brezillon wrote:
Okay. Thanks for the clarification. Can you confirm that this versi
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the
Archit Taneja wrote:
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set
On 06/24/2017 03:20 AM, Eric Anholt wrote:
Boris Brezillon writes:
On Thu, 22 Jun 2017 13:47:43 +0530
Archit Taneja wrote:
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote
On 06/19/2017 09:58 PM, Philippe CORNU wrote:
Add the panel-bridge support for both panels & bridges (used by DSI host &
HDMI/LVDS bridges).
Reviewed-by: Archit Taneja
Signed-off-by: Philippe CORNU
---
drivers/gpu/drm/stm/Kconfig | 2 +-
drivers/gpu/drm/stm/ltdc.
On 06/19/2017 09:58 PM, Philippe CORNU wrote:
Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
Signed-off-by: Philippe CORNU
---
drivers/gpu/drm/bridge/synopsys/Kconfig | 6 +
drivers/gpu/dr
On 06/19/2017 09:58 PM, Philippe CORNU wrote:
Add the STM32 DSI host driver that uses the Synopsys DesignWare
MIPI DSI DRM bridge.
Signed-off-by: Philippe CORNU
Reviewed-by: Neil Armstrong
Reviewed-by: Archit Taneja
---
drivers/gpu/drm/stm/Kconfig | 7 +
drivers/gpu/drm
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel drivers are mipi_dsi_drivers that attach to those nodes.
There is one special case currently
On 06/28/2017 02:35 PM, Andrzej Hajda wrote:
On 28.06.2017 08:44, Archit Taneja wrote:
On 06/19/2017 09:58 PM, Philippe CORNU wrote:
Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
Signed-of
On 06/29/2017 08:13 PM, Philippe CORNU wrote:
On 06/28/2017 08:44 AM, Archit Taneja wrote:
On 06/19/2017 09:58 PM, Philippe CORNU wrote:
Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
Si
On 06/29/2017 04:09 PM, Andrzej Hajda wrote:
On 29.06.2017 07:03, Archit Taneja wrote:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel
On 07/03/2017 02:12 PM, Inki Dae wrote:
This patch removes unnecessary checking of return value.
Ps. this patch depends on below one,
http://www.spinics.net/lists/dri-devel/msg145687.html
Will this one^ go via the exynos pull req or drm-misc? If there won't
be any conflicts, we could
On 07/03/2017 02:12 PM, Inki Dae wrote:
This patch removes unnecessary checking of return value.
Can I get an ack from the maintainers to get this pulled in
via drm-misc?
Thanks,
Archit
Signed-off-by: Inki Dae
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 6 +-
1 file changed, 1 inser
On 07/05/2017 02:35 PM, Inki Dae wrote:
2017년 07월 05일 18:00에 Archit Taneja 이(가) 쓴 글:
On 07/03/2017 02:12 PM, Inki Dae wrote:
This patch removes unnecessary checking of return value.
Ps. this patch depends on below one,
http://www.spinics.net/lists/dri-devel/msg145687.html
Will
On 07/05/2017 04:42 PM, Emil Velikov wrote:
On 5 July 2017 at 10:14, Archit Taneja wrote:
On 07/05/2017 02:35 PM, Inki Dae wrote:
2017년 07월 05일 18:00에 Archit Taneja 이(가) 쓴 글:
On 07/03/2017 02:12 PM, Inki Dae wrote:
This patch removes unnecessary checking of return value.
Ps
On 07/03/2017 02:12 PM, Inki Dae wrote:
This patch series changes return type of drm_bridge_add
function to void one and also removes unnecessary checking
of the return type from relevant drivers.
Ps. I had just build test so each maintainer may need to check this.
I pushed all the bridge dr
On 07/03/2017 02:11 PM, Philippe CORNU wrote:
Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
The patch looks good now. One thing that needs to be updated is to make
drm_bridge_add() not return anyth
On 02/27/2017 07:10 PM, Peter Senna Tschudin wrote:
On Wed, Feb 01, 2017 at 04:17:21PM +0530, Archit Taneja wrote:
Hi Archit,
Hi,
Some minor comments:
Thank you for the review!
On 01/28/2017 07:51 PM, Peter Senna Tschudin wrote:
The video processing pipeline on the second output on
c: David Airlie
Cc: Thierry Reding
Cc: Thierry Reding
Cc: Archit Taneja
Cc: Enric Balletbo
Signed-off-by: Peter Senna Tschudin
---
Changes from V1:
- Updated copyright year
- Fixed blank line issues
- Updated ge_b850v3_lvds_remove() to not rely on ge_b850v3_lvds_ptr->edid and
added a
Hi Peter,
On 3/1/2017 4:08 PM, Peter Senna Tschudin wrote:
Hi Archit,
Thank you for the review!
On Wed, Mar 01, 2017 at 09:38:48AM +0530, Archit Taneja wrote:
On 02/28/2017 07:58 PM, Peter Senna Tschudin wrote:
The video processing pipeline on the second output on the GE B850v3:
Host
Hi,
On 3/2/2017 4:17 PM, Laurent Pinchart wrote:
The LVDS encoder driver is a DRM bridge driver that supports the
parallel to LVDS encoders that don't require any configuration. The
driver thus doesn't interact with the device, but creates an LVDS
connector for the panel and exposes its size and
Hi,
On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote:
The video processing pipeline on the second output on the GE B850v3:
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
Each bridge has a dedicated flash containing firmware for supporting the
custom design. The resul
On 3/3/2017 10:49 PM, Laurent Pinchart wrote:
Hello,
This patch series refactors all the PHY handling code in order to allow
support of vendor PHYs and Synopsys DWC HDMI 2.0 TX PHYs.
The series starts with a few cleanups and small fixes. Patch 01/10 just
removes unused code, patch 02/10 moves
On 3/7/2017 10:12 PM, Neil Armstrong wrote:
This patch adds a new DRM documentation entry and links to the input
format table added in the dw_hdmi header.
Signed-off-by: Neil Armstrong
---
Documentation/gpu/dw-hdmi.rst | 15 +++
Documentation/gpu/index.rst | 1 +
Maybe we cre
On 3/7/2017 10:12 PM, Neil Armstrong wrote:
Add documentation for added Bus Formats to describe RGB and YUS formats used
s/YUS/YUV
as input to the Synopsys DesignWare HDMI TX Controller.
Signed-off-by: Neil Armstrong
---
Documentation/media/uapi/v4l/subdev-formats.rst | 4992
: Archit Taneja
Signed-off-by: Neil Armstrong
---
include/uapi/linux/media-bus-format.h | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/media-bus-format.h
b/include/uapi/linux/media-bus-format.h
index 2168759..7cc820b 100644
--- a/include/uapi
'SSPP_MAX + 1' is the max number of hwpipes that can be present on a
MDP5 platform. Recently, 2 new cursor hwpipes were added, which
caused overflows in arrays that used SSPP_MAX to represent the number
of elements. Update the SSPP_MAX value to incorporate the extra
hwpipes.
Signed-off-
On 03/20/2017 08:27 AM, Nickey Yang wrote:
"I2C Master Interface Extended Read Mode" implements a segment
pointer-based read operation using the Special Register configuration.
This patch fix https://patchwork.kernel.org/patch/7098101/ mentioned
"The current implementation does not support "I2
On 03/21/2017 01:17 PM, Andrzej Hajda wrote:
On 20.03.2017 07:10, Nickey Yang wrote:
Vendor specific infoframe is mandatory for 4K2K resolution.
Without this, the HDMI protocol compliance fails.
Signed-off-by: Nickey Yang
---
drivers/gpu/drm/bridge/dw-hdmi.c | 50 +++
currently done for
pipes and layer mixers. Pass around the interface pointers to
mdp5_encoder and mdp5_ctl. This simplifies the code, and allows
us to decouple encoders from INTFs in the future if needed.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 8 +--
d
on't need to compare anything
with the old state at the moment.
The only LM capability we care about at the moment is whether the mixer
instance can be used to display stuff (i.e, connect to an INTF
downstream).
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 31 +
Create a struct to represent MDP5 Layer Mixer instances. This will
eventually allow us to detach CRTCs from the Layer Mixers, and
generally clean things up a bit.
This is very similar to how hwpipes were previously abstracted away
from drm planes.
Signed-off-by: Archit Taneja
---
drivers/gpu
n try out the changes on a DB820c:
https://github.com/boddob/linux/tree/mixer_virt_v1_4.11
Archit Taneja (24):
drm/msm/mdp5: Bring back pipe_lock to mdp5_plane struct
drm/msm/mdp5: describe LM instances in mdp5_cfg
drm/msm/mdp5: Add structs for hw Layer Mixers
drm/msm/mdp5: Start
than trying to take individual locks per hwpipe when committing a
configuration.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c | 2 --
drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h | 1 -
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 9 +++--
3 files changed, 7 insertions(
r example, INTF0 and CTL0 will always be assigned
to one drm_encoder. This can change later when we implement writeback and
want a CRTC to use a CTL for a while, and then release it for others to use
it. Or, when a drm_encoder can switch between using a single INTF vs
2 INTFs.
Signed-off-by: Archit T
sed for display or
writeback.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 72 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 8
drivers/gpu/drm/msm/mdp/mdp_kms.h | 4 ++
3 files changed, 84 insertions(+)
diff --git a/driv
PingPong ID for a Layer Mixer is already contained in
mdp5_hw_mixer.
This avoids the need to retrieve PP ID using macros
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 6 +++---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 5 ++---
drivers/gpu/drm/msm
ers directly in
mdp5_ctl. This will help avoid confusion later when I introduce
my own verion of a mdp5 pipeline :)
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 42 +
1 file changed, 17 insertions(+), 25 deletions(-)
diff --git a/driv
Use the mdp5_hw_mixer struct in the mdp5_crtc and mdp5_ctl instead of
using the LM index.
Like before, the Layer Mixers are assigned statically to the CRTCs.
The hwmixer(s) will later be dynamically assigned to CRTCs.
For now, ignore the hwmixers that can only do WB.
Signed-off-by: Archit
to a clean state.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 19 +++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 7 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/mdp
w, we just
introduce mdp5_crtc_state and the crtc funcs needed to manage the
subclassed state.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 72 +---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 14 +++
2 files changed, 80 insertions(+), 6
, but it doesn't seem to cause much trouble.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 15 +++---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 32
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 68 ++---
drive
simply
return an error if they're called when the right mixer is assigned to
the CRTC state. With source split is enabled, we're expected to only
SSPP cursors.
This commit adds code that configures the right mixer, but the r_mixer
itself isn't assigned at the moment.
Signed-off-by:
xer to the CRTC, we can also remove
the static assignment to it in mdp5_crtc_init, and also drop the code that
skipped init-ing WB bound mixers (those will now be rejected by
mdp5_mixer_assign()).
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 122
lit mode.
- Since we now have 2 places where REG_MDP5_LM_BLEND_COLOR_OUT is
configured, do a read-update-store for the register instead of
directly writing a value to it.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 39 ++--
1 file ch
LM. For example, the priority order for VIG pipes
in decreasing order of priority is VIG0, VIG1, VIG2, and VIG3. So, VIG0
on left and VIG1 on right is a correct configuration, but VIG1 on left
and VIG0 on right isn't. These scenarios are ignored for now for the
sake of simplicity.
Signed-off-by: Ar
comprised of 2 hwpipes, this func
allow us to configure each pipe without adding redundant code.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 227 +-
1 file changed, 130 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/msm
split mode (and generate the 'left' part of the display
output).
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 21 +++--
drivers/gpu/drm/msm/mdp/mdp_kms.h | 2 ++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drive
gning planes.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 45 +---
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index cf6d41c
used by the crtc code
to set up LM stages.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 46 ++-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5
Now that our mdp5_planes can consist of 2 hwpipes, update the
blend_setup() code to stage the right hwpipe to the left and
right LMs
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 12
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 12
2 files
case, each LM feeds to a
separae INTF, so the 3D mux isn't needed.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_
mplified logic.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 49 +---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.c | 97 +++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.h | 5 +-
3 files changed, 129 insertions(+), 22 deletions(-)
igured are configured later
in this func.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 15d78b218935..fddde84af
Hi,
On 03/07/2017 03:21 AM, Christopher Spinrath wrote:
Hi Fabio,
On 03/06/2017 10:46 PM, Fabio Estevam wrote:
Hi Christopher,
On Mon, Mar 6, 2017 at 6:40 PM, wrote:
From: Christopher Spinrath
On some boards the hpd pin of a hdmi connector is wired up to a gpio
pin. Since in the DRM worl
Hi,
On 03/10/2017 03:01 PM, Romain Perier wrote:
Currently, the irq handler that monitores changes for HPD anx RX_SENSE
relies on the status of the bridge for updating the status of the HPD.
The update is done only when the bridge is enabled.
However, on Rockchip platforms we have found use cas
) so that we can
make sure that the mode will be accepted in every components.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Alexey Brodkin
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Andrzej Hajda
Cc: Archit Taneja
---
Changes v1->v2:
- Removed call to connec
idge_mode_set(struct drm_bridge *bridge,
void drm_bridge_pre_enable(struct drm_bridge *bridge);
void drm_bridge_enable(struct drm_bridge *bridge);
+#ifdef CONFIG_DRM_PANEL
+struct drm_bridge *drm_panel_bridge_add(struct drm_panel *panel,
+ u3
mode_valid() callback
for all bridges in an encoder chain.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Alexey Brodkin
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Andrzej Hajda
Cc: Archit Taneja
---
drivers/gpu/drm/drm_bridge.c | 33 +
include/drm
On 05/12/2017 04:31 PM, Laurent Pinchart wrote:
Hi Archit,
On Friday 12 May 2017 16:20:07 Archit Taneja wrote:
On 05/12/2017 03:08 PM, Laurent Pinchart wrote:
On Wednesday 10 May 2017 17:14:33 Daniel Vetter wrote:
On Wed, May 10, 2017 at 04:41:09PM +0300, Ville Syrjälä wrote:
On Tue, May
Hi,
On 05/15/2017 04:03 PM, Philippe CORNU wrote:
Hi Neil,
Many thanks for your comments.
The PHY part of the MIPI DSI is the main difference between all chipsets
based on the Synopsys DesignWare MIPI DSI.
There is no "generic DSI PHY interface" and that is probably why all soc
vendors have imp
APQ8096 SoC).
Tested-by: Archit Taneja
v3: move size checks back to drivers (Ville Syrjälä)
v2: move fb setting to core and use new state (Eric Anholt)
Cc: Rob Clark
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 151 +-
1 file
On 5/13/2017 12:40 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
After converting legacy cursor updates to atomic async commits
mdp5_cursor_plane_funcs just duplicates mdp5_plane_funcs now.
Tested-by: Archit Taneja
Thanks,
Archit
Cc: Rob Clark
Signed-off-by: Gustavo Padovan
Hi,
On 05/16/2017 08:14 PM, Archit Taneja wrote:
On 5/13/2017 12:40 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
Add support to async updates of cursors by using the new atomic
interface for that. Basically what this commit does is do what
mdp5_update_cursor_plane_legacy() did but
table twice.
Don't call free_duped_table() in ion_map_dma_buf() to avoid this.
Signed-off-by: Archit Taneja
---
drivers/staging/android/ion/ion.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/android/ion/ion.c
b/drivers/staging/android/ion/i
A few members in ion_buffer struct are unused after features
like page faulting, ion_handle and ion_client were removed.
Remove these members and the leftover references to them.
Signed-off-by: Archit Taneja
---
drivers/staging/android/ion/ion.c | 2 --
drivers/staging/android/ion/ion.h | 14
The recent ION clean ups introduced some leftover code that can be
removed, and a bug that comes up if the call to dma_buf_map_attachment()
from an importer fails. Fix these.
Archit Taneja (3):
staging: android: ion: Remove unused members from ion_buffer
staging: android: ion: Remove
The flag ION_FLAG_CACHED_NEEDS_SYNC isn't used anymore. Remove it.
Signed-off-by: Archit Taneja
---
drivers/staging/android/uapi/ion.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/staging/android/uapi/ion.h
b/drivers/staging/android/uapi/ion.h
index b76db1b
On 05/18/2017 09:59 AM, Masahiro Yamada wrote:
With the include directives under include/drm/ fixed, this flag is
no longer needed.
Acked-by: Archit Taneja
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
drivers/gpu/drm/i2c/Makefile | 2 --
1 file changed, 2 deletions(-)
diff
Hi,
On 05/17/2017 12:16 AM, Eric Anholt wrote:
Laurent Pinchart writes:
Hi Eric,
On Tuesday 16 May 2017 09:47:49 Eric Anholt wrote:
Rob Herring writes:
On Mon, May 15, 2017 at 7:03 PM, Eric Anholt wrote:
Laurent Pinchart writes:
Hi Eric,
Thank you for the patch.
On Thursday 11 May 2
On 05/17/2017 05:05 PM, Daniel Vetter wrote:
On Wed, May 17, 2017 at 10:56:25AM +0530, Archit Taneja wrote:
Hi,
On 05/16/2017 08:14 PM, Archit Taneja wrote:
On 5/13/2017 12:40 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
Add support to async updates of cursors by using the new
On 05/18/2017 08:25 PM, Laurent Pinchart wrote:
Hi Archit,
On Thursday 18 May 2017 13:56:19 Archit Taneja wrote:
On 05/17/2017 12:16 AM, Eric Anholt wrote:
[snip]
In terms of physical connections:
[15-pin "DSI" connector on 2835]
| I2C | DSI
/ \
Hi Philippe,
Thanks a lot for creating a bridge driver for this.
Copying some Hisilicon and Rockchip folks so that they can consider adapting to
this.
Some comments below.
On 05/19/2017 08:50 PM, Philippe CORNU wrote:
Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Ro
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device includes both
Video/Sound, like HDMI.
As far as I
On 05/26/2017 09:46 AM, Archit Taneja wrote:
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device
On 05/25/2017 07:49 PM, Jose Abreu wrote:
Introduce a new helper function which calls mode_valid() callback
for all bridges in an encoder chain.
Reviewed-by: Archit Taneja
Signed-off-by: Jose Abreu
Reviewed-by: Daniel Vetter
Cc: Carlos Palminha
Cc: Ville Syrjälä
Cc: Dave Airlie
Cc
mode_valid()
will handle the mode validation.
Reviewed-by: Archit Taneja
NOTE: Only compile tested.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 13
On 05/26/2017 01:21 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
Add support to async updates of cursors by using the new atomic
interface for that. Basically what this commit does is do what
mdp5_update_cursor_plane_legacy() did but through atomic.
Tested-by: Archit Taneja
v4: add
On 05/26/2017 01:21 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
After converting legacy cursor updates to atomic async commits
mdp5_cursor_plane_funcs just duplicates mdp5_plane_funcs now.
Tested-by: Archit Taneja
Cc: Rob Clark
Cc: Archit Taneja
Signed-off-by: Gustavo Padovan
through all atomic steps in
drm_atomic_helper_commit(). We take this path for legacy cursor updates.
For now only single plane updates are supported, but we plan to support
multiple planes updates and async PageFlips through this interface as well
in the near future.
Reviewed-by: Archit Taneja
been tested on Meson by Neil.
Since this also touches rockchip/imx drm driver files, can I get an
OK from the maintainers to pull the changes via drm-misc?
Thanks,
Archit
Signed-off-by: Jose Abreu
Acked-by: Neil Armstrong
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej
need to use mode_fixup() callback as mode_valid()
will handle the mode validation.
NOTE: Only compile tested.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
---
drivers/gpu/drm/bridge/analogix
Hi Boris,
On 05/31/2017 11:56 AM, Boris Brezillon wrote:
Hi Philippe,
Le Tue, 30 May 2017 16:55:42 +,
Philippe CORNU a écrit :
Hi Eric,
I took your patch for the panel-bridge and it works perfectly in both
DPI mode (panel RGB //) and DSI mode (bridge dw mipi dsi), bravo :-)
I still do
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