On Wed, Mar 26, 2014 at 1:22 PM, Ben Skeggs wrote:
> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
> wrote:
>> Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
>> run from non-prepadded firmware files.
>>
>> Signed-off-by: Alexandre C
On Wed, Mar 26, 2014 at 1:24 PM, Ben Skeggs wrote:
> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
> wrote:
>> Add a GR device for GK20A based on NVE4, with the correct classes
>> definitions (GK20A's 3D class is 0xa297).
>>
>> Most of the NVE4 code can
On Wed, Mar 26, 2014 at 1:27 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 9:10 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
>>> GK20A does not embed a dedicated COPY engine and thus cannot allocate
>
On Wed, Apr 2, 2014 at 11:18 PM, Ilia Mirkin wrote:
> On Wed, Apr 2, 2014 at 9:52 AM, Alexandre Courbot wrote:
>> On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding
>> wrote:
>>> On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
>>> [...]
>>
On Wed, Mar 26, 2014 at 1:28 PM, Ben Skeggs wrote:
> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
> wrote:
>> Set the correct subdev/engine classes when GK20A (0xea) is probed.
>>
>> Signed-off-by: Alexandre Courbot
>> ---
>> drivers/gpu/drm/no
On 04/11/2014 04:31 PM, Ben Skeggs wrote:
> On Fri, Apr 11, 2014 at 12:46 PM, Alexandre Courbot
> wrote:
>> On Wed, Mar 26, 2014 at 1:19 PM, Ben Skeggs wrote:
>>> On Tue, Mar 25, 2014 at 7:54 AM, Thierry Reding
>>> wrote:
>>>> On Mon, Mar 24, 2014 at
On Wed, Mar 26, 2014 at 1:19 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 7:54 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:24PM +0900, Alexandre Courbot wrote:
>>> GK20A's timer is directly attached to the system timer and cannot be
>>> cal
On Mon, Apr 14, 2014 at 5:35 PM, Ben Skeggs wrote:
> On Fri, Apr 11, 2014 at 5:34 PM, Alexandre Courbot
> wrote:
>> On 04/11/2014 04:31 PM, Ben Skeggs wrote:
>>>
>>> On Fri, Apr 11, 2014 at 12:46 PM, Alexandre Courbot
>>> wrote:
>>>>
>
On Wed, Mar 26, 2014 at 1:27 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 9:10 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
>>> GK20A does not embed a dedicated COPY engine and thus cannot allocate
>
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau
about BAR initialization code factorization
- Removed non-essential code which only purpose was to avoid warnings
- Use nv_wait in ibus driver
Alexandre Courbot (10):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A su
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu
Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
Skip the creation of a software channel for GK20A as software methods
are not yet supported.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu
On 04/22/2014 08:48 AM, Ben Skeggs wrote:
> On Tue, Apr 22, 2014 at 4:03 AM, Ilia Mirkin wrote:
>> On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot
>> wrote:
>>> Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
>>
>> bytes or u32'
On 04/22/2014 03:07 AM, Ilia Mirkin wrote:
> On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot
> wrote:
>> Skip the creation of a software channel for GK20A as software methods
>> are not yet supported.
>
> How is GK20A different from a nvc0+ card that lacks PDI
On 11/12/2014 09:39 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> dma_alloc_coherent() returns a kernel virtual address that is part of
> the linear range. Passing such an address to virt_to_page() is illegal
> on non-coherent architectures. This causes the kernel to oops on 64-bit
> ARM be
On 12/08/2014 04:14 PM, Alexandre Courbot wrote:
> On 11/12/2014 09:39 PM, Thierry Reding wrote:
>> From: Thierry Reding
>>
>> dma_alloc_coherent() returns a kernel virtual address that is part of
>> the linear range. Passing such an address to virt_to_page() is
On 12/08/2014 04:14 PM, Alexandre Courbot wrote:
> On 11/12/2014 09:39 PM, Thierry Reding wrote:
>> From: Thierry Reding
>>
>> dma_alloc_coherent() returns a kernel virtual address that is part of
>> the linear range. Passing such an address to virt_to_page() is
On 12/08/2014 05:11 PM, Alexandre Courbot wrote:
> On 12/08/2014 04:14 PM, Alexandre Courbot wrote:
>> On 11/12/2014 09:39 PM, Thierry Reding wrote:
>>> From: Thierry Reding
>>>
>>> dma_alloc_coherent() returns a kernel virtual address that is part of
>>&
On Mon, Dec 8, 2014 at 4:14 PM, Alexandre Courbot
wrote:
> On 11/12/2014 09:39 PM, Thierry Reding wrote:
>>
>> From: Thierry Reding
>>
>> dma_alloc_coherent() returns a kernel virtual address that is part of
>> the linear range. Passing such an address to vi
On Wed, Dec 17, 2014 at 1:15 AM, Thierry Reding
wrote:
> From: Thierry Reding
>
> Page-flip completion could race with page-flip submission, so extend the
> critical section to include all accesses to page-flip related data.
>
> Reported-by: Alexandre Courbot
> Signed-o
On Sun, Feb 2, 2014 at 8:58 AM, Lucas Stach wrote:
> Am Samstag, den 01.02.2014, 18:28 -0500 schrieb Ilia Mirkin:
>> On Sat, Feb 1, 2014 at 8:40 AM, Lucas Stach wrote:
>> > Am Samstag, den 01.02.2014, 12:16 +0900 schrieb Alexandre Courbot:
>> >> Add a clumsy-bu
On Sun, Feb 2, 2014 at 3:35 PM, Ilia Mirkin wrote:
> Some very trivial comments below:
>
> On Fri, Jan 31, 2014 at 10:16 PM, Alexandre Courbot
> wrote:
>> Add support for initializing the priv ring of GK20A. This is done by the
>> BIOS on desktop GPUs, but needs to
On 02/03/2014 04:10 AM, Ilia Mirkin wrote:
> Hi Alexandre,
>
> On Fri, Jan 31, 2014 at 10:16 PM, Alexandre Courbot
> wrote:
>> I guess my email address might surprise some of you, so let me anticipate
>> some
>> questions you might have. :P Yes, this work
On 02/03/2014 08:25 PM, David Herrmann wrote:
> Hi
>
> [..snip..]
>> Finally, support for probing GK20A is added in the last 2 patches. It should
>> be
>> noted that contrary to what Nouveau currently expects, GK20A does not embed
>> any
>> display hardware (that part being handled by tegradrm).
On 02/04/2014 12:54 PM, Ben Skeggs wrote:
> On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot
> wrote:
>> Adapt the NVC0 BAR driver to make it able to support chips that do not
>> expose a BAR3. When this happens, BAR1 is then used for USERD mapping
>> and the BAR alloc
On 02/04/2014 12:55 PM, Ben Skeggs wrote:
> On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot
> wrote:
>> GK20A's timer is directly attached to the system timer and cannot be
>> calibrated. Skip the calibration phase on that chip since the
>> corresponding reg
On 02/04/2014 12:53 PM, Ben Skeggs wrote:
> On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot
> wrote:
>> Hello everyone,
> Hey Alex,
>
> The series looks pretty good to me. I'll reply to the relevant
> patches with any minor nit-picks on top of what's already
Hi Daniel,
On 02/04/2014 06:15 PM, Daniel Vetter wrote:
> On Sat, Feb 01, 2014 at 12:16:54PM +0900, Alexandre Courbot wrote:
>> GK20A's FIFO is compatible with NVE0, but only features 128 channels and
>> 1 runlist.
>>
>> Signed-off-by: Alexandre Courbot
>
Address of the ENG_RUNLIST register should be 0x002284 + (engine * 8),
not 0x002284 + (engine * 4).
Signed-off-by: Alexandre Courbot
---
Stumbled upon this one and I'm quite certain the offset was not correct.
This is inconsequential for GK20A which only features one runlist, but
other
On Sun, Feb 2, 2014 at 10:43 PM, Alexandre Courbot wrote:
> On Sun, Feb 2, 2014 at 8:58 AM, Lucas Stach wrote:
>> Am Samstag, den 01.02.2014, 18:28 -0500 schrieb Ilia Mirkin:
>>> On Sat, Feb 1, 2014 at 8:40 AM, Lucas Stach wrote:
>>> > Am Samstag, den 01.02.2014,
Declare 'struct device' explicitly in ttm_page_alloc.h as this file
does not include any file declaring it. This removes the following
warning:
warning: 'struct device' declared inside parameter list
Signed-off-by: Alexandre Courbot
---
This warning was visible when
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should now at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot
---
Sending this ahead since this has received no objections in the RFC and
should be a no-op for PCI
Memory was always allocated for 4096 channels. Change this to allocate
what we actually need according to the number of channels we use.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
pm_runtime_get*() may return -EACCESS to indicate a device does not have
runtime PM enabled. This is the case when the nouveau.runpm parameter is
set to 0, and is not an error in that context. Handle this case without
failure.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
On Mon, Feb 10, 2014 at 8:50 PM, Thierry Reding
wrote:
> On Mon, Feb 10, 2014 at 02:53:00PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c
>> b/drivers/gpu/drm/nouveau/core/engine/device/base.c
> [...
On Mon, Feb 10, 2014 at 9:34 PM, Thierry Reding
wrote:
> On Mon, Feb 10, 2014 at 02:58:12PM +0900, Alexandre Courbot wrote:
>> pm_runtime_get*() may return -EACCESS to indicate a device does not have
>
> s/-EACCESS/-EACCES/
Oops.
>> runtime PM enabled. This is the case w
pm_runtime_get*() may return -EACCES to indicate a device does not have
runtime PM enabled. This is currently the case with platform devices
on Nouveau, and is not an error in that context. Handle this case
without failure.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- Fixed typo and
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- Refactored nouveau_device_create_() to take an additional bus type
argument
Hi Emil,
On 02/12/2014 11:18 PM, Emil Velikov wrote:
> On 12/02/14 05:38, Alexandre Courbot wrote:
>> Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead
>> of PCI to which Nouveau is tightly dependent. This patch allows Nouveau
>> to handl
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot
---
Changes since v2:
- Moved MSI code under PCI-conditioned blocks in mc/base.c, as suggested by
Emil
Ping, David?
On Mon, Feb 10, 2014 at 9:37 PM, Thierry Reding
wrote:
> On Sun, Feb 09, 2014 at 06:43:18PM +0900, Alexandre Courbot wrote:
>> Declare 'struct device' explicitly in ttm_page_alloc.h as this file
>> does not include any file declaring it. This removes
Use the new GPIO descriptor interface to handle the panel's enable GPIO.
This considerably simplifies the code.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/panel/panel-simple.c | 69 ++--
1 file changed, 18 insertions(+), 51 deletions(-)
diff --
regulator_disable() is already performed by panel_simple_disable(),
which is called by panel_simple_remove().
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/panel/panel-simple.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm
These patches add support for the panels used on the NVIDIA SHIELD and
Tegra Note 7 using the simple-panel driver, as both platforms are to be proposed
for inclusion into mainline soon.
Alexandre Courbot (2):
drm/panel: add support for LG LH500WX1-SD03 panel
drm/panel: add support for LG
This panel is used by the NVIDIA SHIELD and supported by the
simple-panel driver.
Signed-off-by: Alexandre Courbot
---
.../devicetree/bindings/panel/lg,lh500wx1-sd03.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 28 ++
2 files changed, 35 insertions
This panel is used by Tegra Note 7 and supported by the simple-panel
driver.
Signed-off-by: Alexandre Courbot
---
.../devicetree/bindings/panel/lg,ld070wx3-sl01.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 28 ++
2 files changed, 35 insertions
Remove PCI-dependent code so the FIFO engine can also handle platform
devices.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/fifo/base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
b/drivers/gpu
pm_runtime_get*() may return -EACCESS to indicate a device does not have
runtime PM enabled. This is the case when the nouveau.runpm parameter is
set to 0, and is not an error in that context. Handle this case without
failure.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
Memory was always allocated for 4096 channels. Change this to allocate
what we actually need according to the number of channels we use.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
bring and improve Tegra K1 support into Nouveau! :)
Alexandre Courbot (16):
drm/nouveau: handle -EACCES runtime PM return code
drm/nouveau: basic support for platform devices
drm/nouveau: add platform device probing function
drm/nouveau/fifo: support platform devices
drm/nouveau/bar: suppor
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 7
a large,
contiguous pool.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core/include/subdev/fb.h | 1 +
drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c| 28 ++
drivers/gpu/drm/nouveau/core/subdev/fb/priv.h| 1
Use abstracted resource query functions to allow FB core to handle
both PCI and platform devices.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev
Add a nouveau_drm_platform_probe() function that probes a Nouveau
platform device and registers it using drm_platform_init().
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/base.c | 34 ++
.../gpu/drm/nouveau/core/include/engine/device.h
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h| 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Use abstracted resource query functions, and obtain the IRQ from the
correct bus.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/include/subdev/mc.h | 1 +
drivers/gpu/drm/nouveau/core/subdev/mc/base.c| 43 +++-
2 files changed, 29 insertions(+), 15
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
Remove PCI-dependent code so the BAR core can also handle platform
devices.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | 15
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +--
1 file ch
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
devices.
Commonly-used PCI functions include resource range query and page
mapping. These functions are abstracted so the correct bus type is used
to perform them. Some PCI-dependent code is also disabled when probing a
non-PCI device.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
o the panel embedded in NVIDIA SHIELD, which allows
us to finally enable the panel in its device tree.
Alexandre Courbot (4):
drm/dsi: Add flag for continuous clock behavior
drm/tegra: dsi - Handle continuous clock flag
drm/panel: LG LH500WX1-SD03 uses continuous clock
ARM: tegra: roth: add di
: Alexandre Courbot
---
include/drm/drm_mipi_dsi.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..5913ef4 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -94,6 +94,8 @@ void
Handle the MIPI_DSI_MODE_CLOCK_CONTINUOUS flag and only set TX-only
clock behavior when this flag is not present for the DSI device.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/tegra/dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/dsi.c
This panel can only operate in continuous clock behavior, so set the
appropriate flag to inform host drivers of this fact.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/panel/panel-simple.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel
DSI support has been fixed to support continuous clock behavior that the
panel used on SHIELD requires, so finally add its device tree node since
it is functional.
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra114-roth.dts | 23 ---
1 file changed, 20
On Thu, Jun 26, 2014 at 2:33 PM, Alexandre Courbot
wrote:
> This series adds support for probing platform devices on Nouveau, as well as
> the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since
> a few extra things need to be supported before that.
>
On 07/03/2014 12:55 AM, Stephen Warren wrote:
> On 07/02/2014 06:19 AM, Alexandre Courbot wrote:
>> DSI support has been fixed to support continuous clock behavior that the
>> panel used on SHIELD requires, so finally add its device tree node since
>> it is functional.
>
DSI support has been fixed to support continuous clock behavior that the
panel used on SHIELD requires, so finally add its device tree node since
it is functional.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- Removed unneeded regulator-always-on property for vdd_lcd regulator
Only
objects
and only falls back to using the DMA API for kernel-only objects
(fences & PBs basically). Will push it shortly but wanted to signal
this revision as deprecated in the meantime.
On Fri, Jun 27, 2014 at 8:22 PM, Alexandre Courbot
wrote:
> v2 was doing some pretty nasty things with
Hi Andrejz,
On Thu, Jul 3, 2014 at 5:23 PM, Andrzej Hajda wrote:
>
> Hi Alexandre,
>
> Thanks for the patch.
>
> On 07/02/2014 02:19 PM, Alexandre Courbot wrote:
>> As per section 5.6.1 of the DSI specification, all DSI transmitters must
>> support continuous cl
On Fri, Jul 4, 2014 at 6:53 PM, Andrzej Hajda wrote:
> On 07/04/2014 07:57 AM, Alexandre Courbot wrote:
>> Hi Andrejz,
>>
>> On Thu, Jul 3, 2014 at 5:23 PM, Andrzej Hajda wrote:
>>> Hi Alexandre,
>>>
>>> Thanks for the patch.
>>>
>>
should be requested to be
coherent (page 6).
Changes since v3:
- Only use the DMA allocator for BOs that strictly require to be coherent
- Fixed the way pages are mapped to the GPU on platform devices
- Thoroughly checked with CONFIG_DMA_API_DEBUG that there were no API violations
Alexandre Courbot
Pages allocated using the DMA API have a coherent memory mapping. Make
this mapping visible to drivers so they can decide to use it instead of
creating their own redundant one.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 2 ++
drivers/gpu/drm/ttm/ttm_tt.c
page_to_phys() is not the correct way to obtain the DMA address of a
buffer on a non-PCI system. Use the DMA API functions for this, which
are portable and will allow us to use other DMA API functions for
buffer synchronization.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core
: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/base.c | 6 ++
drivers/gpu/drm/nouveau/core/include/core/device.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c
b/drivers/gpu/drm/nouveau/core/engine/device/base.c
.
Based on the TTM DMA cache helper patches by Lucas Stach.
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 56 +++
drivers/gpu/drm/nouveau/nouveau_bo.h | 2 ++
drivers/gpu/drm/nouveau/nouveau_gem.c | 12
pushbuffers.
A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent
architecture will be populated using the DMA API, and accesses to it
performed using the coherent mapping performed by dma_alloc_coherent().
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c
Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to
allow them to be safely accessed by the kernel without being synced
on non-coherent architectures.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +-
drivers/gpu/drm/nouveau/nv84_fence.c | 4
continuous behavior
is the default
Changes since v1:
- Removed unneeded regulator-always-on property for vdd_lcd regulator
Alexandre Courbot (4):
drm/dsi: Flag for non-continuous clock behavior
drm/panel: Set non-continuous clock flag on supporting panels
drm/tegra: dsi - Handle non
behavior accordingly.
Signed-off-by: Alexandre Courbot
---
include/drm/drm_mipi_dsi.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..efa1b55 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
The LG LD070WX3-SL01 and Panasonic VVX10F004B00 are DSI support
non-continuous clock mode. Set the MIPI_DSI_CLOCK_NON_CONTINUOUS
to their definition so host drivers become aware of this capability.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/panel/panel-simple.c | 5 +++--
1 file
Handle the MIPI_DSI_CLOCK_NONCONTINUOUS flag and only set TX-only
clock behavior when this flag is present to allow panels requiring
continuous clock mode to operate with this driver.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/tegra/dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1
Tegra DSI support has been fixed to support continuous clock behavior that
the panel used on SHIELD requires, so finally add its device tree node
since it is functional.
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra114-roth.dts | 22 +++---
1 file changed, 19
Ping Ben, how do these two patches look like?
On Fri, Jun 27, 2014 at 7:28 PM, Alexandre Courbot
wrote:
> Some BARs (like GK20A's) do not support being ioremapped write-combined.
> Add a boolean property to the BAR structure and handle that case in the
> Nouveau BO implementati
2 for clocks. I would like to make sure this
approach is approved because applying it to other subdevs.
Alexandre Courbot (3):
drm/nouveau/clk: make therm and volt devices optional
drm/nouveau/clk: support for non-BIOS pstates
drm/gk20a: reclocking support
drivers/gpu/drm/nouveau/Mak
Allow the clock subsystem to operate even if voltage and thermal devices
are not set for the device (for people with watercooling! ;))
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/clock/base.c | 36 +++-
1 file changed, 22 insertions(+), 14
-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/include/subdev/clock.h | 8 +---
drivers/gpu/drm/nouveau/core/subdev/clock/base.c| 16
drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c| 4 ++--
drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c| 4
Add support for reclocking on GK20A, using a statically-defined pstates
table. The algorithms for calculating the coefficients and setting the
clocks are directly taken from the ChromeOS kernel.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1
Hi Ben,
On 07/11/2014 10:07 AM, Ben Skeggs wrote:
> On Thu, Jul 10, 2014 at 5:34 PM, Alexandre Courbot
> wrote:
>> This series adds support for reclocking on GK20A. The first two patches touch
>> the clock subsystem to allow GK20A to operate, by making the presence of the
>
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