From: Lucas Stach
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 1df856f78568..30e5d90cb7bc
From: Lucas Stach
On arches with non-coherent PCI, we need to flush caches ourselfes at
the appropriate places. Introduce two small helpers to make things easy
for TTM based drivers.
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_tt.c| 25
From: Lucas Stach
Signed-off-by: Lucas Stach
[acourbot at nvidia.com: make conditional and platform-friendly]
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 32
drivers/gpu/drm/nouveau/nouveau_bo.h | 20
architectures, and uses it when
writing to in-memory BOs. It will also be useful for implementations of
instmem that access shared memory directly instead of going through
PRAMIN.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/os.h| 17 +
drivers/gpu/drm/nouveau
rather intended for Tegra.
Alexandre Courbot (3):
drm/nouveau: support for probing platform devices
ARM: tegra: of: add GK20A device tree binding
ARM: tegra: jetson-tk1: enable GK20A GPU
Thierry Reding (2):
ARM: tegra: add GK20A GPU to Tegra124 DT
ARM: tegra: venice2: enable GK20A GPU
really needs to do is to make sure the module is powered and
its clocks active before calling nouveau_drm_platform_probe().
Heavily based on work done by Thierry Reding.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Kconfig| 8
Add the device tree binding documentation for the GK20A GPU used in
Tegra K1 SoCs.
Signed-off-by: Alexandre Courbot
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu
From: Thierry Reding
Add the GK20A device node to Tegra124's device tree.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm
From: Thierry Reding
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124-venice2.dts | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
index
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index e31fb61a81d3..15a194d1277f 100644
--- a/arch/arm
through the BAR.
Any idea about the origin of this behavior? Does ARM forbid cached
mappings over IO regions?
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm
On 05/19/2014 06:57 PM, Lucas Stach wrote:
> Am Montag, den 19.05.2014, 18:46 +0900 schrieb Alexandre Courbot:
>> This patch is not meant to be merged, but rather to try and understand
>> why this is needed and what a more suitable solution could be.
>>
>> Allowing BOs
The kerneldoc header of ttm_bo_create() was referring to another
(nonexisting) function and had a few obsolete or incorrect arguments.
Signed-off-by: Alexandre Courbot
---
include/drm/ttm/ttm_bo_api.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/drm/ttm
ttm_tt_cache_flush's implementation was removed in 2009 by commit
c9c97b8c, but its declaration has been hiding in ttm_bo_driver.h since
then.
It has been surviving in the dark for too long now ; give it the mercy
blow.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
in
On 05/23/2014 06:24 PM, Lucas Stach wrote:
> Am Freitag, den 23.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
>> On Mon, May 19, 2014 at 7:16 PM, Lucas Stach
>> wrote:
>>> Am Montag, den 19.05.2014, 19:06 +0900 schrieb Alexandre Courbot:
>>>> On 05/19/2014 0
On 05/23/2014 06:59 PM, Lucas Stach wrote:
> Am Freitag, den 23.05.2014, 18:43 +0900 schrieb Alexandre Courbot:
>> On 05/23/2014 06:24 PM, Lucas Stach wrote:
>>> Am Freitag, den 23.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
>>>> On Mon, May 19, 2014 at 7:1
On Mon, May 19, 2014 at 5:46 PM, Thierry Reding
wrote:
> On Mon, May 19, 2014 at 04:10:57PM +0900, Alexandre Courbot wrote:
>> From: Lucas Stach
>>
>> Signed-off-by: Lucas Stach
>> [acourbot at nvidia.com: make conditional and platform-friendly]
>> Signed-off-b
On Mon, May 19, 2014 at 6:31 PM, Lucas Stach wrote:
> Am Montag, den 19.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
>> From: Lucas Stach
>>
>> Signed-off-by: Lucas Stach
>> [acourbot at nvidia.com: make conditional and platform-friendly]
>>
On Mon, May 19, 2014 at 7:03 PM, Thierry Reding
wrote:
> On Mon, May 19, 2014 at 11:22:11AM +0200, Lucas Stach wrote:
>> Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding:
>> > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote:
>> > > Some
On Mon, May 19, 2014 at 7:16 PM, Lucas Stach wrote:
> Am Montag, den 19.05.2014, 19:06 +0900 schrieb Alexandre Courbot:
>> On 05/19/2014 06:57 PM, Lucas Stach wrote:
>> > Am Montag, den 19.05.2014, 18:46 +0900 schrieb Alexandre Courbot:
>> >> This patch is not mea
On Tue, May 20, 2014 at 6:14 AM, Stephen Warren
wrote:
> On 05/19/2014 03:24 AM, Alexandre Courbot wrote:
>> Add the device tree binding documentation for the GK20A GPU used in
>> Tegra K1 SoCs.
>
> A few minor nits, but otherwise,
> Acked-by: Stephen Warren
>
&g
On Mon, May 19, 2014 at 5:33 PM, Thierry Reding
wrote:
> On Mon, May 19, 2014 at 04:10:56PM +0900, Alexandre Courbot wrote:
>> From: Lucas Stach
>>
>> On arches with non-coherent PCI,
>
> I guess since this applies to gk20a
>
>> we need to flush caches ours
On Fri, May 23, 2014 at 6:24 PM, Lucas Stach wrote:
>> The best way to solve this issue would be to not use the BAR at all
>> since the memory behind these objects can be directly accessed by the
>> CPU. As such it would better be mapped using ttm_bo_kmap_ttm()
>> instead. But right now this is cl
On Mon, May 26, 2014 at 6:21 PM, Lucas Stach wrote:
> Am Montag, den 26.05.2014, 09:45 +0300 schrieb Terje Bergstr?m:
>> On 23.05.2014 17:40, Alex Courbot wrote:
>> > On 05/23/2014 06:59 PM, Lucas Stach wrote:
>> > So after checking with more knowledgeable people, it turns out this is
>> > the exp
On Tue, May 27, 2014 at 10:07 AM, St?phane Marchesin
wrote:
> On Mon, May 26, 2014 at 5:02 PM, Alexandre Courbot
> wrote:
>> On Mon, May 26, 2014 at 6:21 PM, Lucas Stach
>> wrote:
>>> Am Montag, den 26.05.2014, 09:45 +0300 schrieb Terje Bergstr?m:
>>>>
Ben, I am withdrawing this series as it will be superseeded by a new
version. You probably did not intend to merge it, but just in case. :)
On Mon, May 19, 2014 at 3:51 PM, Alexandre Courbot
wrote:
> Fix a very shameful memory leak and a compilation error due to the use of
> non-export
ocate memory at finer
granularity, but that's what CMA is here for and it also simplifies the
driver.
This driver is to be replaced by an IOMMU-based one in the future ;
until then, its current form will allow it to do its job.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/c
>
> While at it, get rid of the legacy drm_vblank_pre_modeset() and
> drm_vblank_post_modeset() calls that are replaced by drm_vblank_on()
> and drm_vblank_off().
>
> Reported-by: Alexandre Courbot
> Signed-off-by: Thierry Reding
Tested-by: Alexandre Courbot
I also think
On Thu, Oct 23, 2014 at 6:46 PM, Andrzej Hajda wrote:
> On 10/23/2014 10:16 AM, Alexandre Courbot wrote:
>> Add the new flags argument to calls of (devm_)gpiod_get*() and
>> remove any direction setting code afterwards.
>>
>> Currently both forms (with or without the f
On Thu, Oct 23, 2014 at 6:45 PM, Andrzej Hajda wrote:
> On 10/23/2014 10:16 AM, Alexandre Courbot wrote:
>> Add the new flags argument to calls of (devm_)gpiod_get*() and
>> remove any direction setting code afterwards.
>>
>> Currently both forms (with or without the f
On Thu, Oct 23, 2014 at 5:16 PM, Alexandre Courbot
wrote:
> Add the new flags argument to calls of (devm_)gpiod_get*() and
> remove any direction setting code afterwards.
>
> Currently both forms (with or without the flags argument)
> are valid thanks to transitional macros in
&
tement S;
> @@
>
> *e = iommu_domain_alloc(...);
> if (IS_ERR(e)) S
>
> Signed-off-by: Amitoj Kaur Chawla
Reviewed-by: Alexandre Courbot
On Fri, Dec 2, 2016 at 12:23 PM, Ilia Mirkin wrote:
> That's right -- nouveau currently requires 4k page sizes to work. This is a
> software limitation, not a hardware one though.
Looking at the trace I wonder - is the limitation in Nouveau or in TTM?
>
>
> On Dec 1, 2016 5:13 PM, "Jeremy Linton
On Wed, Dec 7, 2016 at 6:53 PM, Michel Dänzer wrote:
> On 07/12/16 06:39 PM, Alexandre Courbot wrote:
>> On Fri, Dec 2, 2016 at 12:23 PM, Ilia Mirkin wrote:
>>> That's right -- nouveau currently requires 4k page sizes to work. This is a
>>> software limit
Hi Matthew,
Trying the latest -next on the Jetson TK1 board (with two different DRM
devices and display and render), I noticed that the GPU device probe
always failed with error -ENOSPC. After investigating I figured out that
this was due to the minor device allocation failing when a second DRM
de
Forgot to add the most relevant list for this issue (linux-next).
Stephen, maybe you will want to temporarily revert this patch until this
is cleared? This probably affects other users than DRM.
On 12/13/2016 04:14 PM, Alexandre Courbot wrote:
> Hi Matthew,
>
> Trying the latest -ne
On 12/17/2016 01:16 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Wed, Dec 14, 2016 at 11:08:20PM +0900, Alexandre Courbot wrote:
>> Forgot to add the most relevant list for this issue (linux-next).
>>
>> Stephen, maybe you will want to temporarily r
On Wed, Aug 12, 2015 at 6:59 PM, Afzal Mohammed
wrote:
> Hi,
>
> On Wed, Aug 12, 2015 at 04:40:57PM +0900, Alexandre Courbot wrote:
>
>> Great, thanks. Are you also on an optimus configuration with the
>> NVIDIA card being the secondary GPU?
>
> Spec says graph
Patch has landed in -rc7, thanks David!
On Fri, Aug 14, 2015 at 12:49 PM, Alexandre Courbot wrote:
> On Wed, Aug 12, 2015 at 6:59 PM, Afzal Mohammed
> wrote:
>> Hi,
>>
>> On Wed, Aug 12, 2015 at 04:40:57PM +0900, Alexandre Courbot wrote:
>>
>>> Gr
Hi everyone,
I know, it's about f**king time and I apologize for the time it took us
to finally put this together. m(__)m
I have pushed two git branches which enable GM200 and GM204 (GM206 to
follow soon) owners to finally load NVIDIA-provided signed firmware and
start GR:
- https://github.co
On 09/26/2014 12:48 AM, Stephen Warren wrote:
> On 09/25/2014 07:27 AM, Sjoerd Simons wrote:
>> Playing a bit with todays linux-next on my jetson, it seems this patch is
>> still required for enabling the GPU. Is there anything blocking it
>> (firmware
>> not available yet in liux-firmware?)
>
> I
Hi Robin,
On 04/07/2016 08:50 PM, Robin Murphy wrote:
> Hello,
>
> With 4.6-rc2 (and -rc1) I'm seeing Nouveau blowing up at boot, from the
> look of it by dereferencing some offset from NULL inside
> nouveau_fbcon_imageblit(). My setup is an old XFX 7600GT card plugged
> into an ARM Juno r1 board,
Hi Robin,
On 04/09/2016 03:46 AM, Robin Murphy wrote:
> Hi Alex,
>
> On 08/04/16 05:47, Alexandre Courbot wrote:
>> Hi Robin,
>>
>> On 04/07/2016 08:50 PM, Robin Murphy wrote:
>>> Hello,
>>>
>>> With 4.6-rc2 (and -rc1) I'm se
On 04/11/2016 04:22 PM, Alexandre Courbot wrote:
> ... or maybe we could just unconditionally sync all buffers and let the
> DMA API abstract this away. My concern is that on coherent architectures
> we would still need to loop over all the pages for nothing, as I don't
> think
On 04/11/2016 04:22 PM, Alexandre Courbot wrote:
> Hi Robin,
>
> On 04/09/2016 03:46 AM, Robin Murphy wrote:
>> Hi Alex,
>>
>> On 08/04/16 05:47, Alexandre Courbot wrote:
>>> Hi Robin,
>>>
>>> On 04/07/2016 08:50 PM, Robin Murphy wrote:
&g
Some BARs (like GK20A's) do not support being ioremapped write-combined.
Add a boolean property to the BAR structure and handle that case in the
Nouveau BO implementation.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/include/subdev/bar.h | 3 +++
drivers/gpu/drm/no
GK20A's BAR is functionally identical to NVC0's, but do not support
being ioremapped write-combined. Create a BAR instance for GK20A that
reflect that state.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/eng
second leverages this work to select the DMA allocator to populate TTs
on ARM.
Doing this solves all our coherency problems with Nouveau on Tegra, and
hopefully makes the code easier to read in the process.
Alexandre Courbot (2):
drm/nouveau: cleanup TTM population logic
drm/nouveau: use DMA TT
nouveau_ttm_init() instead of all over nouveau_bo.c
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 63 ++-
drivers/gpu/drm/nouveau/nouveau_drm.h | 11 ++
drivers/gpu/drm/nouveau/nouveau_ttm.c | 15 +
3 files changed, 59 insertions
Cached memory accesses between the CPU and the GPU are not coherent on
ARM. Use the DMA TTM allocator on this architecture to obtain coherent
memory.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
From: Lucas Stach
Nouveau can now be used on ARM, so add an ioprot handler for this
architecture.
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm
GK20A's BAR is functionally identical to NVC0's, but do not support
being ioremapped write-combined. Create a BAR instance for GK20A that
reflect that state.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- Fix compilation warning due to missing cast
Patch 1 of the series
lag.
Tested-by: Alexandre Courbot
For the 4 patches. The first one has a trivial conflict on drm.h when
applied on today's -next.
s and relying on BAR mappings for kernel access and exposure to
user-space, as it fits better with existing code and keeps us safe from most of
the CPU/GPU memory coherency issues (at the cost of some performance).
Looking forward to your review of these few patches! :)
Cheers,
Alex.
Alexandre Courbo
Add a missing newline at the end of a DRM_INFO message.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +--
1 file ch
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 7
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h| 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu
Hi Lucas,
On Mon, Mar 24, 2014 at 10:19 PM, Lucas Stach wrote:
> Hi Alexandre,
>
> Am Montag, den 24.03.2014, 17:42 +0900 schrieb Alexandre Courbot:
>> Hi everyone,
> [...]
>>
>> A few lines of hacks (not included here) are still needed to deal with cached
>>
On Wed, Mar 26, 2014 at 7:33 PM, Lucas Stach wrote:
>> > It does so by doing the necessary manual cache flushes/invalidates on
>> > buffer access, so costs some performance. To avoid this you really want
>> > to get writecombined mappings into the kernel<->userspace interface.
>> > Simply mapping
On 05/01/2014 04:11 PM, Ben Skeggs wrote:
> On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot
> wrote:
>> Changes since v2:
>> - Enabled software class
>> - Removed unneeded changes to nouveau_accel_init()
>> - Replaced use of architecture-private pfn_to_dma() a
class (instead of only relying on the NvGrUseFW parameter).
Alexandre Courbot (9):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
drm/nouveau/fb: add GK20A support
drm/nouveau/fifo: add GK20A support
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
also include the case
where an external firmware has also been loaded.
Also switch to external firmware if the graph class has no microcode
linked to it.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 10 +++---
1 file changed, 7 insertions(+), 3
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu/drm
ttm_tt_cache_flush's implementation was removed in 2009 by commit
c9c97b8c, but its declaration has been hiding in ttm_bo_driver.h since
then.
It has been surviving in the dark for too long now ; give it the coup
de gr?ce.
Signed-off-by: Alexandre Courbot
---
include/drm/ttm/ttm_bo_dri
gk20a_ram_put() can be called with a NULL nouveau_mem in case of error.
Handle that case the way is it done in other RAM drivers.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/nouveau
On 04/22/2014 07:40 PM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Apr 21, 2014 at 03:02:16PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
>> b/drivers/gpu/drm/nouveau/c
On Wed, Apr 23, 2014 at 11:07 AM, Alexandre Courbot
wrote:
> On 04/22/2014 07:40 PM, Thierry Reding wrote:
>>
>> * PGP Signed by an unknown key
>>
>>
>> On Mon, Apr 21, 2014 at 03:02:16PM +0900, Alexandre Courbot wrote:
>> [...]
>>>
>>
looks good! Once this gets merged the next set will be to use this
driver on Jetson and Venice2 boards.
Cheers,
Alexandre Courbot (9):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
drm/nouveau/fb: add
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu/drm
On Mon, Apr 28, 2014 at 8:44 PM, Thierry Reding
wrote:
> On Wed, Apr 23, 2014 at 03:11:01PM +0900, Alexandre Courbot wrote:
>> On Wed, Apr 23, 2014 at 11:07 AM, Alexandre Courbot
>> wrote:
>> > On 04/22/2014 07:40 PM, Thierry Reding wrote:
>> >>
On Mon, Apr 28, 2014 at 11:10 AM, Ben Skeggs wrote:
> On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot
> wrote:
>> nvc0_graph_ctor() would only let the graphics engine be enabled if its
>> oclass has a proper microcode linked to it. This prevents GR from being
>> enab
Pages allocated using the DMA API have a coherent memory mapping. Make
this mapping visible to drivers so they can decide to use it instead of
creating their own redundant one.
Signed-off-by: Alexandre Courbot
Acked-by: David Airlie
---
Changes since v1:
- Perform only one allocation for pages
Ping, Thierry?
On Fri, Jul 25, 2014 at 11:47 PM, Alexandre Courbot
wrote:
> Use the new devm_gpiod_get_optional() to simplify the probe code.
>
> Signed-off-by: Alexandre Courbot
> ---
> drivers/gpu/drm/panel/panel-simple.c | 12 +---
> 1 file changed, 5 insertio
On Tue, Mar 25, 2014 at 7:10 AM, Thierry Reding
wrote:
> On Mon, Mar 24, 2014 at 05:42:26PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
>> b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
> [...]
>> static i
On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding
wrote:
> On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
>> b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
> [...]
>>
On Wed, Mar 26, 2014 at 1:21 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 8:58 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:30PM +0900, Alexandre Courbot wrote:
>> [...]
>>> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
>>
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