On Wed, Feb 17, 2021 at 1:20 AM Diego Viola wrote:
>
> This code times out on GP108, probably because the BIOS puts it into a
> bad state.
>
> Since we reset the PMU on driver load anyway, we are at no risk from
> missing a response from it since we are not waiting for one to begin
> with.
This l
This driver requires imported PRIME buffers to appear contiguously in
its IO address space. Make sure this is the case by setting the maximum
DMA segment size to a better value than the default 64K on the DMA
device, and use said DMA device when importing PRIME buffers.
Signed-off-by: Alexandre
This driver requires imported PRIME buffers to appear contiguously in
its IO address space. Make sure this is the case by setting the maximum
DMA segment size to a more suitable value than the default 64KB.
Signed-off-by: Alexandre Courbot
Reviewed-by: Tomasz Figa
---
drivers/gpu/drm/mediatek
) Using the correct DMA device when importing PRIME buffers,
2) Setting a more suitable DMA segment size on the DMA device than the
default 64KB.
Changes since v1:
- Split into two patches,
- Fixed an error path that would have returned 0.
Alexandre Courbot (2):
drm/mediatek: use correct device
PRIME buffers should be imported using the DMA device. To this end, use
a custom import function that mimics drm_gem_prime_import_dev(), but
passes the correct device.
Fixes: 119f5173628aa ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Alexandre Courbot
---
d
On Wed, Jul 24, 2019 at 2:49 PM CK Hu wrote:
>
> Hi, Alexandre:
>
> On Tue, 2019-07-23 at 14:34 +0900, Alexandre Courbot wrote:
> > This driver requires imported PRIME buffers to appear contiguously in
> > its IO address space. Make sure this is the case by setting the
On Fri, Sep 20, 2019 at 9:11 AM Dave Airlie wrote:
>
> > Hmm. My merge isn't identical to that. It's close though. Different
> > order for one #define which might be just from you and me merging
> > different directions.
> >
> > But I also ended up removing the .gem_prime_export initialization to
On Mon, Sep 26, 2016 at 9:32 PM, Ard Biesheuvel
wrote:
> Some subdevices (i.e., fb/nv50.c and fb/gf100.c) map a scratch page using
> dma_map_page() way before the TTM layer has had a chance to set the DMA
> mask. This may prevent the driver from loading at all on platforms whose
> system memory is
On Mon, Sep 26, 2016 at 9:32 PM, Ard Biesheuvel
wrote:
> The 100c10 scratch page is mapped using dma_map_page() before the TTM
> layer has had a chance to set the DMA mask. This means we are still
> running with the default of 32 when this code executes, and this causes
> problems for platforms wi
On Mon, Sep 26, 2016 at 9:32 PM, Ard Biesheuvel
wrote:
> The 100c08 scratch page is mapped using dma_map_page() before the TTM
> layer has had a chance to set the DMA mask. This means we are still
> running with the default of 32 when this code executes, and this causes
> problems for platforms wi
E references, which is not
> defined on all architectures
> v2: replace incorrect comparison of dma_addr_t type var against NULL
>
> Ard Biesheuvel (3):
> drm/nouveau: set streaming DMA mask early
> drm/nouveau/fb/gf100: defer DMA mapping of scratch page to oneinit()
> hook
> drm/nouveau/fb/nv50: defer DMA mapping of scratch page to oneinit()
> hook
The series,
Reviewed-by: Alexandre Courbot
Thanks!
On Mon, Oct 17, 2016 at 5:12 AM, Ard Biesheuvel
wrote:
> On 7 October 2016 at 09:12, Alexandre Courbot wrote:
>> On Fri, Oct 7, 2016 at 12:49 AM, Ard Biesheuvel
>> wrote:
>>> This v4 is now a 3 piece series (since v4), after Alexandre pointed out that
>>> bot
it
seems to work like a charm.
Reviewed-by: Alexandre Courbot
Tested-by: Alexandre Courbot
Thanks,
Thierry
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
index a6a7fa0d7679..7f5244d57d2f 100644
--- a/drivers/gpu/d
On Mon, Oct 31, 2016 at 3:35 PM, Christophe JAILLET
wrote:
> 'iommu_domain_alloc()' returns NULL in case of error, not an error pointer.
> So test it accordingly.
>
> Signed-off-by: Christophe JAILLET
Reviewed-by: Alexandre Courbot
Indeed. Thanks for the fix!
is intended to replace the dedicated IOCTL enabled
by TEGRA_STAGING and to provide a non-staging alternative to that
solution.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/tegra/drm.c | 2 ++
drivers/gpu/drm/tegra/fb.c| 23 +++---
include/uapi/drm/drm_fourcc.h | 45
On 11/08/2016 06:07 PM, Erik Faye-Lund wrote:
> On Tue, Nov 8, 2016 at 8:50 AM, Alexandre Courbot
> wrote:
>> Add FB modifiers to allow user-space to specify that a surface is in one
>> of the two tiling formats supported by Tegra chips, and add support in
>> the tegrad
On Sat, Mar 11, 2017 at 5:55 AM, Dan Carpenter wrote:
> Hello Alexandre Courbot,
>
> The patch 5429f82f3415: "drm/nouveau/secboot: add
> gp102/gp104/gp106/gp107 support" from Jan 26, 2017, leads to the
> following static checker warning:
>
> drivers/gpu/
On Mon, Oct 31, 2016 at 1:34 AM, Ilia Mirkin wrote:
> Hi Alex,
>
> As you're well-aware, your commit
> 8539b37acef73949861a16808b60cb8b5b9b3bab (drm/nouveau/gr: use
> NVIDIA-provided external firmwares) broke tons of existing setups for
> people who were using extracted firmware files (stored in t
Patch 3d50d4dcb0 exposed the CPU address of DMA-allocated pages as
returned by dma_alloc_coherent because Nouveau on Tegra needed it.
This is not required anymore - as there were no other users for it,
remove it and save some memory for everyone.
Signed-off-by: Alexandre Courbot
---
drivers
On 09/14/2016 07:07 AM, Kristian H. Kristensen wrote:
> The only current user of this open codes the ioctl. Let's add an entry
> point for this to libdrm.
Tested-by: Alexandre Courbot
Replaced one custom (staging) ioctl on Tegra with FB modifiers, noticed
this was missing!
>
&
On Sat, Sep 24, 2016 at 6:06 AM, Christophe JAILLET
wrote:
> If 'ioremap()' returns 0, 'gm20b_tegra_read_wpr()' will return 0 as well,
> which means success.
> Return -ENOMEM instead
Reviewed-by: Alexandre Courbot
>
> Signed-off-by: Christophe JAILLET
> -
gt; to take precedence, so revert this change until the real underlying
> problem can be fixed.
>
> Signed-off-by: Robin Murphy
> ---
>
> Alex, Ben, Dave,
>
> I know Alex was looking into this, but since we're nearly at -rc6 already
> it looks like the only thing to do for 4.6 is pick the lesser of two evils...
Hi Robin,
Sorry for the delayed reply - I was offline last week.
You are right, so let's pick this patch for now.
Reviewed-by: Alexandre Courbot
The default DMA mask covers a 32 bits address range, but tegradrm can
address more than that. Set the DMA mask to the actual addressable range
to avoid the use of unneeded bounce buffers.
Signed-off-by: Alexandre Courbot
---
Thierry, I am not absolutely sure whether the size is correct and
() is called and sets the default ioswtlb DMA ops.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/tegra/drm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index d347188bf8f4..bc0555adecaf 100644
--- a/drivers/gpu/drm/tegra/drm.c
On 02/24/2016 01:04 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Feb 23, 2016 at 03:25:54PM +0900, Alexandre Courbot wrote:
>> The default DMA mask covers a 32 bits address range, but tegradrm can
>> address more than that. Set the DMA mask to the act
On 02/24/2016 12:28 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Feb 23, 2016 at 03:25:53PM +0900, Alexandre Courbot wrote:
>> The current settings leaves the DRM device's dma_ops field NULL, which
>> makes it use the dummy DMA ops on arm64 and r
operations are set.
Suggested-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
drivers/gpu/host1x/bus.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index c2e7fba370bb..c27858ae0552 100644
--- a/drivers/gpu/host1x/bus.c
+++ b/drivers
On Thu, Feb 25, 2016 at 2:34 AM, Thierry Reding
wrote:
> From: Thierry Reding
>
> The error cleanup paths aren't quite correct and will crash upon
> deferred probe.
>
> Cc: stable at vger.kernel.org # v4.3+
> Signed-off-by: Thierry Reding
Reviewed-by: Alexandre Courbot
operations are set.
Suggested-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
Changes since v2:
- Re-roll with patch 2/2 for completeness
drivers/gpu/host1x/bus.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index c2e7fba370bb
The default DMA mask covers a 32 bits address range, but devices can
address more than that. Set the DMA mask to the actual addressable range
to avoid the use of unneeded bounce buffers.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- set the mask at the bus level so of_dma_configure
dma_alloc_coherent() can return memory in the vmalloc range.
virt_to_page() cannot handle such addresses and crashes. This
patch detects such cases and obtains the struct page * using
vmalloc_to_page() instead.
Signed-off-by: Alexandre Courbot
---
This patch is a follow-up of the following
Re-pinging Marteen on an email address that still exists :P
On Wed, Apr 22, 2015 at 6:08 PM, Alexandre Courbot wrote:
> On Sun, Mar 15, 2015 at 5:41 PM, Alexandre Courbot
> wrote:
>> On 03/14/2015 04:33 AM, Maarten Lankhorst wrote:
>>>
>>> Hey,
>>>
>
On 05/16/2015 04:55 AM, Konrad Rzeszutek Wilk wrote:
> On Fri, May 15, 2015 at 04:09:54PM +0900, Alexandre Courbot wrote:
>> dma_alloc_coherent() can return memory in the vmalloc range.
>> virt_to_page() cannot handle such addresses and crashes. This
>> patch detects such
On 05/19/2015 09:53 PM, Arnd Bergmann wrote:
> The recently added iommu code in the nouveau driver fails to build
> when the IOMMU support is disabled:
>
> drivers/gpu/drm/nouveau/nouveau_platform.c: In function
> 'nouveau_platform_probe_iommu':
> drivers/gpu/drm/nouveau/nouveau_platform.c:113:41:
On Fri, May 15, 2015 at 8:39 PM, Maarten Lankhorst
wrote:
> Op 15-05-15 om 09:11 schreef Alexandre Courbot:
>> Re-pinging Marteen on an email address that still exists :P
>>
>> On Wed, Apr 22, 2015 at 6:08 PM, Alexandre Courbot
>> wrote:
>>> On Sun, Mar 15
0xa0) that are to be recycled as staging IOCTLs become stable and are assigned
a final number.
Alexandre Courbot (1):
drm: add staging module option
Ari Hirvonen (1):
drm/nouveau: Set tile mode
drm/nouveau/nouveau_drm.c | 19 +
drm/nouveau/nouveau
Add a module option allowing to enable staging/unstable APIs. This will
allow us to experiment freely with experimental APIs for a while before
setting them in stone.
Signed-off-by: Alexandre Courbot
---
drm/nouveau/nouveau_drm.c | 18 ++
drm/nouveau/uapi/drm
From: Ari Hirvonen
Add new NOUVEAU_GEM_SET_TILING ioctl to set correct tiling
mode for imported dma-bufs. This ioctl is staging for now.
Signed-off-by: Ari Hirvonen
[acourbot at nvidia.com: carry upstream, fix style]
Signed-off-by: Alexandre Courbot
---
drm/nouveau/nouveau_drm.c
The lack of IOMMU API support can make nouveau_platform_probe_iommu()
fail to compile because struct iommu_ops is then empty. Fix this by
skipping IOMMU probe in that case - lack of IOMMU on platform devices
is sub-optimal, but is not an error.
Signed-off-by: Alexandre Courbot
---
This is an
On Wed, May 20, 2015 at 9:01 PM, Arnd Bergmann wrote:
> On Wednesday 20 May 2015 13:32:33 Thierry Reding wrote:
>>
>> Since these are all static functions, perhaps an "if (IS_ENABLED(...))"
>> would work here? That way you'd get compile coverage of the code in all
>> cases.
>
> I had the same thou
On Thu, May 21, 2015 at 1:48 PM, Ben Skeggs wrote:
> On 20 May 2015 at 15:56, Alexandre Courbot wrote:
>> Add a module option allowing to enable staging/unstable APIs. This will
>> allow us to experiment freely with experimental APIs for a while before
>> setting them in st
On Thu, May 21, 2015 at 2:55 PM, Ben Skeggs wrote:
> On 21 May 2015 at 15:49, Alexandre Courbot wrote:
>> On Thu, May 21, 2015 at 1:48 PM, Ben Skeggs wrote:
>>> On 20 May 2015 at 15:56, Alexandre Courbot wrote:
>>>> Add a module option allowing to enable st
architectures for which coherency is not guaranteed by the bus.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
None, just added Martin so he can merge the patch. R-b and A-b wanted. :)
include/drm/nouveau_drm.h | 1 +
nouveau/abi16.c | 3 +++
nouveau/nouveau.h | 1 +
3 files
On Wed, May 20, 2015 at 3:53 PM, Martin Peres wrote:
> On 20/05/15 08:11, Alexandre Courbot wrote:
>>
>> On Fri, May 15, 2015 at 8:39 PM, Maarten Lankhorst
>> wrote:
>>>
>>> Op 15-05-15 om 09:11 schreef Alexandre Courbot:
>>>>
>>>&
On Thu, May 21, 2015 at 5:35 PM, Ben Skeggs wrote:
> On 21 May 2015 at 16:04, Alexandre Courbot wrote:
>> On Thu, May 21, 2015 at 2:55 PM, Ben Skeggs wrote:
>>> On 21 May 2015 at 15:49, Alexandre Courbot wrote:
>>>> On Thu, May 21, 2015 at 1:48 PM, Ben Skeggs wro
On Fri, May 22, 2015 at 3:23 AM, Martin Peres wrote:
> On 21/05/2015 11:47, Ben Skeggs wrote:
>>
>> On 21 May 2015 at 16:08, Alexandre Courbot wrote:
>>>
>>> Add a flag allowing Nouveau to specify that an object should be coherent
>>> at allocatio
On Wed, May 20, 2015 at 4:07 PM, Arnd Bergmann wrote:
> On Wednesday 20 May 2015 15:10:24 Alexandre Courbot wrote:
>> The lack of IOMMU API support can make nouveau_platform_probe_iommu()
>> fail to compile because struct iommu_ops is then empty. Fix this by
>> skipping IOM
On Sun, May 24, 2015 at 3:26 PM, Maarten Lankhorst
wrote:
> Op 23-05-15 om 08:45 schreef Alexandre Courbot:
>> On Fri, May 22, 2015 at 3:23 AM, Martin Peres
>> wrote:
>>> On 21/05/2015 11:47, Ben Skeggs wrote:
>>>> On 21 May 2015 at 16:08, Alexandre Courb
we call the SET_TILING ioctl.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/tegra/drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index cc48334ef164..c0ae89865958 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/driv
On Fri, Jul 1, 2016 at 8:50 AM, Markus Mayer wrote:
> Call strtolower() rather than walking the string explicitly to convert
> it to lowercase.
>
> Signed-off-by: Markus Mayer
> ---
> drivers/gpu/drm/nouveau/nvkm/core/firmware.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> d
On Sun, Jul 3, 2016 at 12:21 AM, Markus Mayer
wrote:
> On 1 July 2016 at 18:18, Alexandre Courbot wrote:
>> On Fri, Jul 1, 2016 at 8:50 AM, Markus Mayer wrote:
>>> Call strtolower() rather than walking the string explicitly to convert
>>> it to lowercase.
>>
On Sun, Jul 3, 2016 at 3:18 PM, Christophe JAILLET
wrote:
> This is likely that checking 'gr3d->clk_secondary' instead of 'gr3d->clk'
> is expected here.
Very likely indeed.
Reviewed-by: Alexandre Courbot
Thanks!
On Mon, Jul 4, 2016 at 10:37 AM, Alexandre Courbot wrote:
> On Sun, Jul 3, 2016 at 12:21 AM, Markus Mayer
> wrote:
>> On 1 July 2016 at 18:18, Alexandre Courbot wrote:
>>> On Fri, Jul 1, 2016 at 8:50 AM, Markus Mayer wrote:
>>>> Call strtolower() rather than
On Wed, Jul 6, 2016 at 9:23 PM, wrote:
> From: Wei Yongjun
>
> In case of error, the function iommu_domain_alloc() returns NULL
> pointer not ERR_PTR(). The IS_ERR() test in the return value check
> should be replaced with NULL test.
Reviewed-by: Alexandre Courbot
Thanks!
On Mon, Jul 4, 2016 at 4:45 PM, Dan Carpenter
wrote:
> "brick" is allocated with devm_kzalloc() so freeing it with kfree()
> leads to a double free. We can just delete it.
That makes perfect sense.
Reviewed-by: Alexandre Courbot
On Mon, Jul 4, 2016 at 4:19 PM, wrote:
> From: Wei Yongjun
>
> data allocated with devm_kzalloc should not be freed using kfree,
> because doing so causes a dangling pointer, and a subsequent
> double free, use devm_kfree instead.
>
> Signed-off-by: Wei Yongjun
> ---
> drivers/gpu/drm/tegra/so
On Wed, Jul 6, 2016 at 7:56 AM, Joe Perches wrote:
> On Tue, 2016-07-05 at 15:36 -0700, Markus Mayer wrote:
>> On 5 July 2016 at 15:14, Joe Perches wrote:
>> > On Tue, 2016-07-05 at 13:47 -0700, Markus Mayer wrote:
>> > > This series introduces a family of generic string case conversion
>> > > fu
On Fri, Jul 8, 2016 at 1:59 AM, Ard Biesheuvel
wrote:
> The 100c08 scratch page is mapped using dma_map_page() before the TTM
> layer has had a chance to set the DMA mask. This means we are still
> running with the default of 32 when this code executes, and this causes
> problems for platforms wit
On Sat, Jul 16, 2016 at 4:45 AM, Ard Biesheuvel
wrote:
> On 15 July 2016 at 07:52, Alexandre Courbot wrote:
>> On Fri, Jul 8, 2016 at 1:59 AM, Ard Biesheuvel
>> wrote:
>>> The 100c08 scratch page is mapped using dma_map_page() before the TTM
>>> layer has had a
On Fri, Jul 11, 2014 at 10:14 PM, Thierry Reding
wrote:
> On Tue, Jul 08, 2014 at 09:32:14PM +0900, Alexandre Courbot wrote:
>> Tegra DSI support has been fixed to support continuous clock behavior that
>> the panel used on SHIELD requires, so finally add its device tree node
with different protection.
The mapping provided by dma_alloc_coherent() and exposed by this patch is
guaranteed to be safe, but subsequent mappings performed by drivers are
not. Thus drivers using the DMA page allocator should use this mapping
instead of creating their own.
Signed-off-by: Alexandre
On Fri, Jul 11, 2014 at 10:38 AM, Alexandre Courbot
wrote:
> Hi Ben,
>
>
> On 07/11/2014 10:07 AM, Ben Skeggs wrote:
>>
>> On Thu, Jul 10, 2014 at 5:34 PM, Alexandre Courbot
>> wrote:
>>>
>>> This series adds support for reclocking on GK20
On Fri, Jul 11, 2014 at 7:54 PM, Peter De Schrijver
wrote:
> On Fri, Jul 11, 2014 at 03:49:06AM +0200, Alex Courbot wrote:
>> On 07/10/2014 06:43 PM, Peter De Schrijver wrote:
>> > On Thu, Jul 10, 2014 at 09:34:34AM +0200, Alexandre Courbot wrote:
>> >> This series
DRM maintainers, could I have a comment about this patch? A bunch of
Nouveau changes depend on it.
Thanks,
Alex.
On Tue, Jul 15, 2014 at 11:10 AM, Alexandre Courbot
wrote:
> Pages allocated using the DMA API have a coherent memory mapping. Make
> this mapping visible to drivers so th
On Tue, Jul 22, 2014 at 7:51 AM, Mark Brown wrote:
> On Mon, Jul 21, 2014 at 11:16:32PM +0200, Thierry Reding wrote:
>> On Mon, Jul 21, 2014 at 09:35:27AM -0600, Stephen Warren wrote:
>
>> > > vdd-2v8-display needs to remain always-on however. Here we may hit a
>> > > limitation of the simple-pane
On Tue, Jul 22, 2014 at 2:07 PM, Dave Airlie wrote:
> On 22 July 2014 14:21, Alexandre Courbot wrote:
>> DRM maintainers, could I have a comment about this patch? A bunch of
>> Nouveau changes depend on it.
>
> I'm not sure we really have anyone who is in a great p
gpiod getters to 16 (!).
The drawback of this approach is that all gpiod clients need to be
updated, but there aren't that many and the moment and this results in
smaller (and hopefully safer) code.
Signed-off-by: Alexandre Courbot
---
This change will be difficult to apply without bre
On Fri, Jul 25, 2014 at 1:23 AM, Laurent Pinchart
wrote:
>> diff --git a/Documentation/gpio/consumer.txt
>> b/Documentation/gpio/consumer.txt index 7ff30d2..a3fb1d7 100644
>> --- a/Documentation/gpio/consumer.txt
>> +++ b/Documentation/gpio/consumer.txt
>> @@ -29,13 +29,24 @@ gpiod_get() functions
On Fri, Jul 25, 2014 at 1:10 AM, Arnd Bergmann wrote:
> On Friday 25 July 2014 00:04:58 Alexandre Courbot wrote:
>> I'm not sure how this could be applied harmlessly though - maybe through
>> a dedicated branch for -next? Problem is that a lot of new code is not
>> yet
Use the new devm_gpiod_get_optional() to simplify the probe code.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/panel/panel-simple.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel
The DMA API is the recommended way to map pages no matter what the
underlying bus is. Use the DMA functions for page mapping and remove
currently existing wrappers.
Signed-off-by: Alexandre Courbot
Cc: Daniel Vetter
---
Changes since v4:
- Patch against the Nouveau tree instead of the kernel
mapping.
This patch fixes this issue by detecting when such mappings occur and by
skipping the required number of pages in the list to ensure a correct
linear mapping.
Signed-off-by: Alexandre Courbot
---
Ben, how does this look? This issue has been highlighted by the GK20A
RAM driver which makes use
On Mon, May 19, 2014 at 6:22 PM, Lucas Stach wrote:
> Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding:
>> On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote:
>> > Some architectures (e.g. ARM) need the CPU buffers to be explicitely
>> > fl
On Mon, Jun 9, 2014 at 7:41 PM, Alexandre Courbot wrote:
> On Mon, May 19, 2014 at 6:22 PM, Lucas Stach
> wrote:
>> Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding:
>>> On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote:
>>> > Some
using the platform helpers, which is made
possible by drm_dev_set_unique(). This allows us to catch and register the
DRM device during platform probe.
* Fixed the clock names in the DT bindings.
* Removed the patches enabling GK20A on Venice2 and Jetson TK1 as support
is not complete yet.
Alex
really needs to do is to make sure the module is powered and
its clocks active before calling nouveau_drm_platform_probe().
Heavily based on work done by Thierry Reding.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Kconfig| 8
Add the device tree binding documentation for the GK20A GPU used in
Tegra K1 SoCs.
Signed-off-by: Alexandre Courbot
Acked-by: Stephen Warren
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644 Documentation
From: Thierry Reding
Add the GK20A device node to Tegra124's device tree.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm
ttm_tt_cache_flush's implementation was removed in 2009 by commit
c9c97b8c, but its declaration has been hiding in ttm_bo_driver.h since
then.
It has been surviving in the dark for too long now ; give it the mercy
blow.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
Review
For this v2 I have fixed the patches that are non-controversial (all Lucas' :))
and am resubmitting them in the hope that they will get merged. This will
just leave the issue of Nouveau system-memory buffers mapping to be solved.
This issue is quite complex, so let me summarize the situation and t
From: Lucas Stach
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 1df856f78568..30e5d90cb7bc
From: Lucas Stach
On architectures for which access to GPU memory is non-coherent,
caches need to be flushed and invalidated explicitly at the
appropriate places. Introduce two small helpers to make things
easy for TTM-based drivers.
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
From: Lucas Stach
Use the newly-introduced TTM cache sync functions in Nouveau.
Signed-off-by: Lucas Stach
[acourbot at nvidia.com: rearrange code, make platform-friendly]
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 47
On 06/24/2014 07:02 PM, Russell King - ARM Linux wrote:
> On Tue, Jun 24, 2014 at 06:54:26PM +0900, Alexandre Courbot wrote:
>> From: Lucas Stach
>>
>> On architectures for which access to GPU memory is non-coherent,
>> caches need to be flushed and invalidated expli
On 06/24/2014 07:33 PM, Alexandre Courbot wrote:
> On 06/24/2014 07:02 PM, Russell King - ARM Linux wrote:
>> On Tue, Jun 24, 2014 at 06:54:26PM +0900, Alexandre Courbot wrote:
>>> From: Lucas Stach
>>>
>>> On architectures for which access to GPU memory is
On Tue, Jun 24, 2014 at 10:58 PM, Lucas Stach wrote:
> Am Dienstag, den 24.06.2014, 22:52 +0900 schrieb Alexandre Courbot:
>> On Tue, Jun 24, 2014 at 10:25 PM, Lucas Stach
>> wrote:
>> > Am Dienstag, den 24.06.2014, 14:27 +0200 schrieb Maarten Lankhorst:
>> &
On Tue, Jun 24, 2014 at 7:55 PM, Alexandre Courbot
wrote:
> On 06/24/2014 07:33 PM, Alexandre Courbot wrote:
>>
>> On 06/24/2014 07:02 PM, Russell King - ARM Linux wrote:
>>>
>>> On Tue, Jun 24, 2014 at 06:54:26PM +0900, Alexandre Courbot wrote:
>>
On Tue, Jun 24, 2014 at 10:09 PM, Russell King - ARM Linux
wrote:
> On Tue, Jun 24, 2014 at 09:23:05PM +0900, Alexandre Courbot wrote:
>> On Tue, Jun 24, 2014 at 7:55 PM, Alexandre Courbot
>> wrote:
>> > The only alternative I see here is to flush the CPU caches when syn
On Tue, Jun 24, 2014 at 10:25 PM, Lucas Stach wrote:
> Am Dienstag, den 24.06.2014, 14:27 +0200 schrieb Maarten Lankhorst:
>> op 24-06-14 14:23, Alexandre Courbot schreef:
>> > On Tue, Jun 24, 2014 at 7:55 PM, Alexandre Courbot > > nvidia.com> wrote:
>> >
names in the DT bindings.
* Removed the patches enabling GK20A on Venice2 and Jetson TK1 as support
is not complete yet.
Alexandre Courbot (2):
drm/nouveau: support for probing platform devices
ARM: tegra: of: add GK20A device tree binding
Thierry Reding (1):
ARM: tegra: add GK20A G
really needs to do is to make sure the module is powered and
its clocks active before calling nouveau_drm_platform_probe().
Heavily based on work done by Thierry Reding.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Kconfig| 8
Add the device tree binding documentation for the GK20A GPU used in
Tegra K1 SoCs.
Signed-off-by: Alexandre Courbot
Acked-by: Stephen Warren
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644 Documentation
From: Thierry Reding
Add the GK20A device node to Tegra124's device tree.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm
On Wed, Jun 25, 2014 at 1:00 PM, St?phane Marchesin
wrote:
> On Tue, Jun 24, 2014 at 6:25 AM, Lucas Stach
> wrote:
>> Am Dienstag, den 24.06.2014, 14:27 +0200 schrieb Maarten Lankhorst:
>>> op 24-06-14 14:23, Alexandre Courbot schreef:
>>> > On Tue, Jun 24, 2
On Tue, Jun 24, 2014 at 10:58 PM, Lucas Stach wrote:
> Am Dienstag, den 24.06.2014, 22:52 +0900 schrieb Alexandre Courbot:
>> On Tue, Jun 24, 2014 at 10:25 PM, Lucas Stach
>> wrote:
>> > Am Dienstag, den 24.06.2014, 14:27 +0200 schrieb Maarten Lankhorst:
>> &
On Fri, Jun 27, 2014 at 1:10 AM, Russell King - ARM Linux
wrote:
> On Thu, Jun 26, 2014 at 11:53:20PM +0900, Alexandre Courbot wrote:
>> We don't plan to rely on CMA for too long. IOMMU support is on the way
>> and should make our life easier, although no matter the source o
situation
(compile error).
Alexandre Courbot (2):
drm/gk20a/fb: fix huge memory leak
drm/gk20a/fb: fix compile error whith CMA and module
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 95 ---
1 file changed, 67 insertions(+), 28 deletions(-)
--
1.9.2
.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 74 ++-
1 file changed, 46 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
index
, but at least won't produce a compile
error.
This is a temporary fix until a better memory allocation scheme is
devised.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 25 +--
1 file changed, 23 insertions(+), 2 deletions(-)
diff
/nouveau/2013-August/014026.html
Another patch takes care of flushing the CPU write-buffer when writing BOs
through a non-BAR path.
Alexandre Courbot (1):
drm/nouveau: introduce CPU cache flushing macro
Lucas Stach (3):
drm/ttm: recognize ARM arch in ioprot handler
drm/ttm: introduce dma
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