On Wed, 2012-11-28 at 18:24 -0500, Jerome Glisse wrote:
> On Wed, Nov 28, 2012 at 6:18 PM, Thomas Hellstrom
> wrote:
> > On 11/28/2012 04:58 PM, j.glisse at gmail.com wrote:
> >>
> >> From: Jerome Glisse
> >>
> >> This patch add a minimum residency time configurable for each memory
> >> pool (VR
On Wed, 2012-11-28 at 18:24 -0500, Jerome Glisse wrote:
> On Wed, Nov 28, 2012 at 6:18 PM, Thomas Hellstrom wrote:
> > On 11/28/2012 04:58 PM, j.gli...@gmail.com wrote:
> >>
> >> From: Jerome Glisse
> >>
> >> This patch add a minimum residency time configurable for each memory
> >> pool (VRAM, GT
On Tue, 2012-01-31 at 13:16 +, Simon Farnsworth wrote:
> Hello,
>
> When profiling my workload on an AMD E-350 (PALM GPU) to see why it still
> wasn't performing well with Jerome's WIP macrotiling patches, I noticed that
> r600_fence_finish was taking 10% of my CPU time. I determined experimen
Radeon power management restricts the maximum engine clock to the initial
default clock. However, on APUs the default clock usually is not the fastest
allowed by their defined power states. Change restriction to the fastest
engine clock found in power states.
Signed-off-by: Alan Swanson
On Tue, 2012-01-31 at 13:16 +, Simon Farnsworth wrote:
> Hello,
>
> When profiling my workload on an AMD E-350 (PALM GPU) to see why it still
> wasn't performing well with Jerome's WIP macrotiling patches, I noticed that
> r600_fence_finish was taking 10% of my CPU time. I determined experimen
Radeon power management restricts the maximum engine clock to the initial
default clock. However, on APUs the default clock usually is not the fastest
allowed by their defined power states. Change restriction to the fastest
engine clock found in power states.
Signed-off-by: Alan Swanson
On 2014-10-09 07:02, Michel D?nzer wrote:
> From: Michel D?nzer
>
> The radeon driver uses placement range restrictions for several
> reasons,
> in particular to make sure BOs in VRAM can be accessed by the CPU, e.g.
> during a page fault.
>
> Without this change, TTM could evict other BOs whil
On Fri, 2014-10-10 at 12:20 +0900, Michel D?nzer wrote:
> On 09.10.2014 19:22, Alan Swanson wrote:
> > On 2014-10-09 07:02, Michel D?nzer wrote:
> >> From: Michel D?nzer
> >>
> >> The radeon driver uses placement range restrictions for several reasons,
> &g
