The timeout is 64bit but the maths against it is done 32bit wrapped. Force
64bit.
Signed-off-by: Alan Cox
---
drivers/gpu/drm/i915/i915_gem.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index
Otherwise a pde_shift big enough to overflow a u32 will be truncated before
assignment
Signed-off-by: Alan Cox
---
drivers/gpu/drm/i915/i915_gem_gtt.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915
Shifting 1 into a u64 doesn't do what you might expect. Force the width
before shifting.
Signed-off-by: Alan Cox
---
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
b/dr
From: Alan Cox
This is a left over from the great clean ups in the past. It's confusing as
it returns an int, yet has one caller that never uses it. The caller already
has all the right private variables local so the entire function can be
replaced by a simple if call.
Signed-off-by: Ala
From: Alan
Both cases produce the same result. Kill the junk code.
Signed-off-by: Alan Cox
---
drivers/gpu/drm/gma500/mdfld_dsi_dpi.c |6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c
b/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c
If you feed the tool a suitable bogus register map you can break it
in arbitary (code executing) ways. While this isn't a particularly
exciting or probable attack vector we still ought to fix it.
One of a set of sscanf issues reported by Jackie Chang
Signed-off-by: Alan Cox
---
drivers/gp
If you feed the tool a suitable bogus register map you can break it
in arbitary (code executing) ways. While this isn't a particularly
exciting or probable attack vector we still ought to fix it.
One of a set of sscanf issues reported by Jackie Chang
Signed-off-by: Alan Cox
---
drivers/gp
ll
communication with a USB device has to go through a USB host controller,
and many (though not all) host controllers _can_ do DMA and _do_ have a
DMA mask.
The USB mass-storage and uas drivers in particular make heavy use of
this mechanism.
Alan Stern
___
On Fri, Feb 19, 2021 at 04:56:16PM +0100, Christian König wrote:
>
>
> Am 19.02.21 um 16:53 schrieb Alan Stern:
> > On Fri, Feb 19, 2021 at 02:45:54PM +0100, Christian König wrote:
> > > Well as far as I can see this is a relative clear NAK.
> > >
> > >
shouldn't
> that be done in the USB core itself?
>
> {hint, yes}
>
> There shouldn't be anything "special" about a DRM driver that needs this
> vs. any other driver that might want to know about DMA things related to
> a specific USB device. Why isn't this an issue with the existing
> storage or v4l USB devices?
If Thomas finds that the approach I outlined above works, then the rest
of this email thread becomes moot. :-)
Alan Stern
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ad of messing around with USB
internals, drm_gem_prime_import_usb could just call this new function.
Adding such a utility function would be a sufficiently small change that
it could go into the -stable kernels with no trouble.
Alan Stern
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struct usb_interface
or (even better) a pointer to a usb_interface's embedded struct device.
Then you wouldn't need to compute udev, and the same would be true for
other callers.
Alan Stern
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On Thu, Feb 25, 2021 at 09:23:05AM +0100, Takashi Iwai wrote:
> On Thu, 25 Feb 2021 08:57:14 +0100,
> Thomas Zimmermann wrote:
> >
> > Hi
> >
> > Am 24.02.21 um 16:21 schrieb Alan Stern:
> > > On Wed, Feb 24, 2021 at 10:23:04AM +0100, Thomas Zimmermann w
so the actual
> DMA device is not important.
>
> Drivers should use DRM_GEM_SHMEM_DROVER_OPS_USB to initialize their
> instance of struct drm_driver.
>
> Tested by joining/mirroring displays of udl and radeon un der Gnome/X11.
>
> v5:
> * provide a helper for USB in
> +
> + return err;
> +}
> +
> static const struct tegra_ehci_soc_config tegra30_soc_config = {
> .has_hostpc = true,
> };
> @@ -431,6 +505,11 @@ static int tegra_ehci_probe(struct platform_device *pdev)
> goto cleanup_hcd_create;
> }
>
.
v2: - Fix build issue: uninitialized var
Reported-by: kernel test robot
Alan Previn (1):
drm/i915/reset: Fix error_state_read ptr + offset use
drivers/gpu/drm/i915/i915_sysfs.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
--
2.25.1
inconsistent
sysfs reads as per review comment from John Harrison.
- Add the "fixes" tag referencing the previous patch
of the same function.
v2: - Fix build issue: uninitialized var
Reported-by: kernel test robot
Alan Previn (1):
drm/i915/reset: Fix error_stat
mp
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (13):
drm/i915/guc: Update GuC ADS size for error capture lists
drm/i915/guc: Add XE_LP static registers for GuC error cap
ed
error capture information matches the i915_gpu_coredump
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (13):
drm/i915/guc: Update GuC ADS size for error capture list
batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (13):
drm/i915/guc: Update GuC ADS size for error capture lists
drm/i915/guc: Add XE_LP static registers for GuC error capture.
drm/i915/guc: Add XE_LP steered register lists support
drm/i915/guc: Add DG2 registers for G
int out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (13):
drm/i915/guc: Update GuC ADS size for error capture lists
drm/i915/guc: Add XE_LP static registers for GuC error capture.
drm/i915/guc: Add XE_LP steered register
triggered the reset.
For now, introduce an empty printing function that can
filled in on a subsequent patch just to handle formatting.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../drm/i915/gt/intel_execlists_submission.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c
in the midst of a reset. That said, we can never
dynamically allocate the output nodes in this handler. Thus, we
shall pre-allocate a fixed number of empty nodes up front (at the
time of ADS registration) that we can consume from or return to
an internal cached list of nodes.
Signed-off-by: Alan Pr
e 'engine-capture-group-output' vs a
copy of that same info taken during i915_gpu_coredump. If
they match, then print those vma's as well (such as the batch
buffers).
NOTE: the output format was verified using the gem_exec_capture
IGT test.
Signed-off-by: Alan Previn
Reviewed-by
as independent ring buffers. Each guc-log subregion
(general-logs, crash-dump and error- capture) has it's own
guc_log_buffer_state that contain independent read and write
pointers.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/abi/guc_
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
drivers/gpu/drm/i915/gt
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm
ered registers.
- Add additional checks to ensure that the GuC reported
error capture information matches the i915_gpu_coredump
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 inser
e the
io_sys_map wrapper functions to access the various GuC log
buffer regions.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 59 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 3 +-
2 files changed, 37 insertions(+
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_f
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc
le of register lists to
layout the framework before adding real registers in subsequent
patch. This static register tables are a different format from
the ADS populated list.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gp
hen reporting extended steered registers.
- Add additional checks to ensure that the GuC reported
error capture information matches the i915_gpu_coredump
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 inser
in the midst of a reset. That said, we can never
dynamically allocate the output nodes in this handler. Thus, we
shall pre-allocate a fixed number of empty nodes up front (at the
time of ADS registration) that we can consume from or return to
an internal cached list of nodes.
Signed-off-by: Alan Pr
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 112 ++
drivers/gpu/drm/i915/gt
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_f
le of register lists to
layout the framework before adding real registers in subsequent
patch. This static register tables are a different format from
the ADS populated list.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gp
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm
e 'engine-capture-group-output' vs a
copy of that same info taken during i915_gpu_coredump. If
they match, then print those vma's as well (such as the batch
buffers).
NOTE: the output format was verified using the gem_exec_capture
IGT test.
Signed-off-by: Alan Previn
Reviewed-by
e the
io_sys_map wrapper functions to access the various GuC log
buffer regions.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 59 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 3 +-
2 files changed, 37 insertions(+
triggered the reset.
For now, introduce an empty printing function that can
filled in on a subsequent patch just to handle formatting.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../drm/i915/gt/intel_execlists_submission.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c
as independent ring buffers. Each guc-log subregion
(general-logs, crash-dump and error- capture) has it's own
guc_log_buffer_state that contain independent read and write
pointers.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/abi/guc_
Fix pointer offset usage in error_state_read
when there is no i915_gpu_coredump but buf offset
is non-zero.
Alan Previn (1):
drm/i915/reset: Fix error_state_read ptr + offset use
drivers/gpu/drm/i915/i915_sysfs.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
--
2.25.1
out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (13):
drm/i915/guc: Update GuC ADS size for error capture lists
drm/i915/guc: Add XE_LP static registers for GuC error capture.
drm/i915/guc: Add XE_LP steered register
Fix pointer offset usage in error_state_read
when there is no i915_gpu_coredump but buf offset
is non-zero.
This is the 2nd rev of this series.
Changes from prior revs:
v2: - Fix build issue: uninitialized var
Reported-by: kernel test robot
Alan Previn (1):
drm/i915/reset: Fix
such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (13):
drm/i915/guc: Update GuC ADS size for error capture lists
drm/i915/guc: Add XE_LP static registers for GuC error capture.
drm/i915/guc: Add XE_LP steered register lists support
drm/i915/guc: Add DG2 registers
_PXP off
- Patch #11 - increase timeout when waiting in intel_pxp_start
as firmware session startup is slower right after boot.
Tested with: https://patchwork.freedesktop.org/series/87570/
Cc: Gaurav Kumar
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: Juston Li
Cc: Alan Previn
Cc: L
1. verify that buffer sharing works across testing pxp context.
2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
3. verify display plane decryption of protected buffers.
Alan Previn (14):
Add PXP UAPI support in i915_drm.h
Add basic PXP testin
v10
- Fixed checkpatch errors.
Tested with: https://patchwork.freedesktop.org/series/87570/
Cc: Gaurav Kumar
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: Juston Li
Cc: Alan Previn
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
Anshuman Gupta (2):
drm/i915/pxp
: Needed a rebase to latest drm-tip for merging.
Tested with: https://patchwork.freedesktop.org/series/87570/
Cc: Gaurav Kumar
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: Juston Li
Cc: Alan Previn
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
Anshuman Gupta (2):
drm
Kumar
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: Juston Li
Cc: Alan Previn
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
Anshuman Gupta (2):
drm/i915/pxp: Add plane decryption support
drm/i915/pxp: black pixels on pxp disabled
Daniele Ceraolo Spurio (9):
drm
3d state offsets that batchbuffer has no visibility.
- Added these additional subtests:
1. verify that buffer sharing works across testing pxp context.
2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
3. verify display p
ontexts via DRM_IOCTL_I915_GET_RESET_STAT.
3. verify display plane decryption of protected buffers.
Alan Previn (15):
i915_drm.h sync PXP default session
i915_drm.h sync PXP object creation
Add basic PXP testing of buffer and context alloc
Perform a regular 3d copy as a
2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
3. verify display plane decryption of protected buffers.
Alan Previn (14):
i915_drm.h sync
Add basic PXP testing of buffer and context alloc
Perform a regular 3d copy as a control checkpoint
Add PXP att
Replace private helper with call to ioctl_wrapper for
DRM_IOCTL_PRIME_HANDLE_TO_FD.
Signed-off-by: Alan Previn
---
tests/i915/gem_pxp.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 79040165..0430f4b8
ing extended steered registers.
- Add additional checks to ensure that the GuC reported
error capture information matches the i915_gpu_coredump
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI ret
registers.
- Add additional checks to ensure that the GuC reported
error capture information matches the i915_gpu_coredump
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn
circular buffer store
to copy snapshots of new GuC reported error-state-capture
dumps in response to the G2H notification.
6. Connects the i915_gpu_coredump reporting function
to the GuC error capture module to print all GuC
error state capture dumps that is reported.
Alan Previn
d out what size/resolution information i915 is getting and passing to
Wayland? If it's wrong, how can I fix it?
Thanks,
Alan Stern
additional checks to ensure that the GuC reported
error capture information matches the i915_gpu_coredump
that is being printed before we print out the corresponding
VMA dumps such as the batch buffer.
v2:
- Ignore - failed CI retest.
Alan Previn (6):
drm/i915/guc:
the dinosaurs but yes any vesa bios code will
not be speculatively hardened. I'd also doubt anyone is actually using
vesafb in the first place but it should use nospec
Alan
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This series remove unnecessary GuC err capture noise.
Alan Previn (1):
drm/i915/guc: Remove unnecessary GuC err capture noise
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 77 +--
1 file changed, 2 insertions(+), 75 deletions(-)
--
2.25.1
GuC error capture blurts some debug messages about empty
register lists for certain register types on engines during
firmware initialization.
These are not errors or warnings, so get rid of them.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 77
ly pretty reliable. Sometimes there are
transient errors, but they are relatively rare. No one would criticize
a driver for giving up the first time it gets an error (especially if
there was an easy way to reset it) -- but people will get annoyed if a
ton of error messages shows up on the cons
On 9/10/19 5:55 AM, Eric Engestrom wrote:
On Monday, 2019-09-09 16:51:16 -0700, Alan Coopersmith wrote:
On Solaris, sys/sysmacros.h has long-deprecated copies of major() & minor()
but not makedev(). sys/mkdev.h has all three and is the preferred choice.
So we check for sys/mkdev.h first
OpenMinor’:
../xf86drm.c:454:30: error: implicit declaration of function ‘makedev’
[-Werror=implicit-function-declaration]
454 | return drmOpenDevice(makedev(DRM_MAJOR, minor), minor, type);
| ^~~
Signed-off-by: Alan Coopersmith
---
meson.build | 6
debugging.
Signed-off-by: Alan Previn
---
.../i915/pxp/intel_pxp_cmd_interface_cmn.h| 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 52 ++-
3 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/dr
a drm_debug) or else cusomer
apps that really needs to know that content protection failed won't
be aware of it.
Fixes: b762787bf767 ("drm/i915/pxp: Use drm_dbg if arb session failed due to fw
version")
Signed-off-by: Alan Previn
---
.../i915/pxp/intel_pxp_cmd_interface_cmn.h
urces during gsccs-fini
- on Patch#5: add dispatching of arb session termination
firmware cmd during session teardown (as per latest
upstream flows)
Alan Previn (8):
drm/i915/pxp: Add GSC-CS back-end resource init and cleanup
drm/i915/pxp: Add MTL hw-plumbing enabling
#x27; send-message function.
Do this one time allocation of gsccs specific resources in
a new gsccs source file with intel_pxp_gsccs_init / fini functions
and hook them up from the PXP front-end.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile
header file for PXP
to be consistent with other i915 global subsystems.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32
drivers/gpu/drm/i915/pxp/intel_pxp
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the timeouts for new GSC-CS + firmware specs.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +-
2 files changed, 2 insertions(+), 1
freeing of these buffers in gsccs
init and fini.
Signed-off-by: Alan Previn
---
.../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 +
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c| 223 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 7 +
3 files changed, 232 insertions(+), 2
e for uncore when touching
IRQ registers despite the pxp->ctrl_gt being the media-tile.
No difference for legacy of course.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 24 +---
drivers/gpu/
27;s init,
fini and resume.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 19 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 3 ++-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/g
example, requiring a retry).
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 110 ++
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 76 +
7;s
pending-bit which means the GSC firmware is busy and we should
resubmit.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +-
.../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 21 +
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c| 92 +++
drivers/g
urces during gsccs-fini
- on Patch#5: add dispatching of arb session termination
firmware cmd during session teardown (as per latest
upstream flows)
v4 : - Added proper initialization and cleanup of host-session-handle
that the gsc firmware expects.
header file for PXP
to be consistent with other i915 global subsystems.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32
drivers/gpu/drm/i915/pxp/intel_pxp
27;s init,
fini and resume.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 19 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 3 ++-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/g
7;s
pending-bit which means the GSC firmware is busy and we should
resubmit.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +-
.../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 21 +
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c| 92 +++
drivers/g
freeing of these buffers in gsccs
init and fini.
Signed-off-by: Alan Previn
---
.../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 +
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c| 224 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 6 +
3 files changed, 232 insertions(+), 2
e for uncore when touching
IRQ registers despite the pxp->ctrl_gt being the media-tile.
No difference for legacy of course.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 24 +---
drivers/gpu/
example, requiring a retry).
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 108 ++
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 76 +
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the timeouts for new GSC-CS + firmware specs.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +-
2 files changed, 2 insertions(+), 1
#x27; send-message function.
Do this one time allocation of gsccs specific resources in
a new gsccs source file with intel_pxp_gsccs_init / fini functions
and hook them up from the PXP front-end.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile
and new code comments for detail.
This is new direction from HW architecture folks.
v2: - Add error message for the teardown timeout (Anshuman)
- Don't duplicate code in comments (Jani)
Signed-off-by: Alan Previn
Fixes: 5a44fcd73498 ("drm/i915/gsc: Do a driver-FLR on unload if GS
g unload, its so the uncore
doesn't complain.
Signed-off-by: Alan Previn
Fixes: 5a44fcd73498 ("drm/i915/gsc: Do a driver-FLR on unload if GSC was
loaded")
---
drivers/gpu/drm/i915/intel_uncore.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-
- Bit 31 of GU_CNTL should be DRIVERFLR instead of
DRIVERFLR_STATUS (Daniele).
Signed-off-by: Alan Previn
Tested-by: Vinay Belgaumkar
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uncore.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
#x27; send-message function.
Do this one time allocation of gsccs specific resources in
a new gsccs source file with intel_pxp_gsccs_init / fini functions
and hook them up from the PXP front-end.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile
we need a single handle that is already initialized during
execution_resource init in Patch #4.
- In Patch #8, increase the wait timeout for termination to
align with the same SLA.
Alan Previn (8):
drm/i915/pxp: Add GSC-CS back-end resource init and cleanup
drm/i915/pxp: Ad
e for uncore when touching
IRQ registers despite the pxp->ctrl_gt being the media-tile.
No difference for legacy of course.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 24 +---
drivers/gpu/
7;s
pending-bit which means the GSC firmware is busy and we should
resubmit.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 34 --
.../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 21 +++
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c| 62 +
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