On 7/23/2021 3:51 AM, Rob Clark wrote:
From: Rob Clark
This adds a few things to try and make frequency scaling better match
the workload:
1) Longer polling interval to avoid whip-lashing between too-high and
too-low frequencies in certain workloads, like mobile games which
throttle th
Add the missing scache_cntl0 register programing which is required for
a660 gpu.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ---
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno
0x06030500 as the gpu id of this gpu to communicate
to the userspace driver.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++
drivers/gpu/drm/msm
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
This patch has dependency on the GPUCC bindings patch here:
https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-t...@codeaurora.org/
arch/arm64/boot/dts/qcom/sc7280
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
This patch has dependency on the GPUCC bindings patch here:
https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-t...@codeaurora.org/
Changes in v2:
- formatting update
On 7/24/2021 11:42 PM, Rob Clark wrote:
()
On Fri, Jul 23, 2021 at 3:38 AM Akhil P Oommen wrote:
This patch adds support for the gpu found in the Snapdragon 7c Gen 3
compute platform. This gpu is similar to the exisiting a660 gpu with
minor delta in the programing sequence. As the Adreno
On 7/27/2021 5:46 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2021-07-24 10:29:00)
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
This patch has dependency on the GPUCC bindings patch here:
https://patchwork.kernel.org/project/linux-arm-msm/patch
From: Manaf Meethalavalappu Pallikunhi
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 29
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
This has dependency on the below GPUCC bindings patch which is already
accepted in clk-next:
https://patchwork.kernel.org/project/linux-clk/list/?series=514831&state=%2A&archive=both
Changes in
Add the missing scache_cntl0 register programing which is required for
a660 gpu.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ---
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu
0x06030500 as the gpu id of this gpu to communicate
to the userspace driver.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Introduce adreno_is_a660_family() (Rob)
- Remove revn for 7c3 (Rob)
- Remove CPR register programing since they are not required for 7c3
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
Use rev instead of revn to identify the SKU. This is in
preparation to the introduction of 7c3 gpu which won't have a
revn.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
0x06030500 as the gpu id of this gpu to communicate
to the userspace driver.
Changes in v3:
- Add a cover letter.
Changes in v2:
- Use rev to identify SKU
- Introduce adreno_is_a660_family() (Rob)
- Remove revn for 7c3 (Rob)
- Remove CPR register programing since they are not required for 7c3
Akhil P
Use rev instead of revn to identify the SKU. This is in
preparation to the introduction of 7c3 gpu which won't have a
revn.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
Add the missing scache_cntl0 register programing which is required for
a660 gpu.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ---
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu
0x06030500 as the gpu id of this gpu to communicate
to the userspace driver.
Signed-off-by: Akhil P Oommen
---
(no changes since v2)
Changes in v2:
- Introduce adreno_is_a660_family() (Rob)
- Remove revn for 7c3 (Rob)
- Remove CPR register programing since they are not required for 7c3
drivers/gpu/drm
Introduce a feature flag in gpulist to easily identify the capabilities
of each gpu revision. This will help to avoid a lot of adreno_is_axxx()
check when we add new features. In the current patch, HW APRIV feature
is converted to a feature flag.
Signed-off-by: Akhil P Oommen
---
This patch is
On 7/29/2021 8:57 PM, Rob Clark wrote:
On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen wrote:
Use rev instead of revn to identify the SKU. This is in
preparation to the introduction of 7c3 gpu which won't have a
revn.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
driver
On 7/29/2021 9:08 PM, Rob Clark wrote:
On Thu, Jul 29, 2021 at 8:21 AM Akhil P Oommen wrote:
This patch adds support for the gpu found in the Snapdragon 7c Gen 3
compute platform. This gpu is similar to the exisiting a660 gpu with
minor delta in the programing sequence. As the Adreno GPUs are
On 7/29/2021 9:26 PM, Rob Clark wrote:
On Thu, Jul 29, 2021 at 8:31 AM Akhil P Oommen wrote:
Introduce a feature flag in gpulist to easily identify the capabilities
of each gpu revision. This will help to avoid a lot of adreno_is_axxx()
check when we add new features. In the current patch, HW
On 7/29/2021 10:46 PM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2021-07-28 00:17:45)
On 7/27/2021 5:46 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2021-07-24 10:29:00)
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
This patch has dependency on
)
- Remove revn for 7c3 (Rob)
- Remove CPR register programing since they are not required for 7c3
Akhil P Oommen (3):
drm/msm/a6xx: Fix llcc configuration for a660 gpu
drm/msm/a6xx: Use rev to identify SKU
drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpu
drivers/gpu/drm/msm/adreno
Add the missing scache_cntl0 register programing which is required for
a660 gpu.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ---
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu
Use rev instead of revn to identify the SKU. This is in
preparation to the introduction of 7c3 gpu which won't have a
revn.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Move adreno_cmp_rev() here to fix compilation
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +--
driver
0x06030500 as the chip id of this gpu to communicate
to the userspace driver.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Move out adreno_cmp_rev() to patch-2/3 to fix compilation
Changes in v2:
- Introduce adreno_is_a660_family() (Rob)
- Remove revn for 7c3 (Rob)
- Remove CPR register programing
On 7/30/2021 5:38 AM, Rob Clark wrote:
On Sat, Jul 24, 2021 at 8:21 PM Bjorn Andersson
wrote:
This patch adds a Adreno 680 entry to the gpulist.
Looks reasonable, but I wonder if we should just go ahead and add
adreno_is_a640_family() in a similar vein to
adreno_is_a650_familiy()/adreno_is_a
Add a few new registers for a6xx gpu.
Signed-off-by: Akhil P Oommen
---
registers/adreno/a6xx.xml | 2 ++
registers/adreno/a6xx_gmu.xml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/registers/adreno/a6xx.xml b/registers/adreno/a6xx.xml
index 15314fb..3b04565 100644
--- a/registers
Add a few new registers for a6xx gpu.
Signed-off-by: Akhil P Oommen
---
registers/adreno/a6xx.xml | 2 ++
registers/adreno/a6xx_gmu.xml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/registers/adreno/a6xx.xml b/registers/adreno/a6xx.xml
index 15314fb..3b04565 100644
--- a/registers
On 8/8/2021 10:22 PM, Rob Clark wrote:
On Sun, Aug 8, 2021 at 7:33 AM Caleb Connolly wrote:
On 07/08/2021 21:04, Rob Clark wrote:
On Sat, Aug 7, 2021 at 12:21 PM Caleb Connolly
wrote:
Hi Rob, Akhil,
On 29/07/2021 21:53, Rob Clark wrote:
On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
w
On 8/9/2021 9:48 PM, Caleb Connolly wrote:
On 09/08/2021 17:12, Rob Clark wrote:
On Mon, Aug 9, 2021 at 7:52 AM Akhil P Oommen
wrote:
On 8/8/2021 10:22 PM, Rob Clark wrote:
On Sun, Aug 8, 2021 at 7:33 AM Caleb Connolly
wrote:
On 07/08/2021 21:04, Rob Clark wrote:
On Sat, Aug 7, 2021
From: Manaf Meethalavalappu Pallikunhi
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 29
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Removed the dependency on gpucc bindings (Stephen)
- Reordered GPU's opp table
Changes in v3:
- Re-ordered the nodes based on address (Stephen)
- Added the patch for gpu cooling t
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
Changes in v5:
- Added Stephen's reviewed-by tag to patch-2
Changes in v4:
- Removed the dependency on gpucc bindings (Stephen)
- Reordered GPU's opp table
Changes in v3:
- Re-ordered the node
From: Manaf Meethalavalappu Pallikunhi
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi
Signed-off-by: Akhil P Oommen
Reviewed-by: Stephen Boyd
---
(no changes since v1)
arch/arm64
On 4/2/2021 3:19 AM, Rob Clark wrote:
On Thu, Apr 1, 2021 at 2:03 PM Dmitry Baryshkov
wrote:
On Thu, 1 Apr 2021 at 23:09, Rob Clark wrote:
On Mon, Feb 22, 2021 at 8:06 AM Rob Clark wrote:
On Mon, Feb 22, 2021 at 7:45 AM Akhil P Oommen wrote:
On 2/19/2021 9:30 PM, Rob Clark wrote:
On
We were not programing the correct bit while clearing the perfcounter oob.
So, clear it correctly using the new 'clear' bit. This fixes the below
error:
[drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set PERFCOUNTER:
0x8000
Signed-off-by: Akhil P Oommen
---
drivers/g
The speedbin support requires nvmem driver api. So lets explicitly
enable CONFIG_NVMEM to have this support.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index dabb4a1
On 2/3/2021 4:22 AM, Bjorn Andersson wrote:
On Fri 08 Jan 12:15 CST 2021, Akhil P Oommen wrote:
Please align the $subject prefix with other changes in the same file.
I fixed it up while picking up the patch this time.
Will take of this in future. Thanks, Bjorn.
-Akhil.
Regards,
Bjorn
Add
gem_submit_reloc));
/* check for overflow: */
Reviewed-by: Akhil P Oommen
-Akhil.
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
On 2/10/2021 6:22 AM, Jordan Crouse wrote:
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error messages
On 2/11/2021 9:32 PM, Jordan Crouse wrote:
On Thu, Feb 11, 2021 at 06:50:28PM +0530, Akhil P Oommen wrote:
On 2/10/2021 6:22 AM, Jordan Crouse wrote:
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to
On 2/18/2021 2:05 AM, Jonathan Marek wrote:
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse
wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek
On 2/18/2021 9:41 PM, Rob Clark wrote:
On Thu, Feb 18, 2021 at 4:28 AM Akhil P Oommen wrote:
On 2/18/2021 2:05 AM, Jonathan Marek wrote:
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse
wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen
On 2/19/2021 9:30 PM, Rob Clark wrote:
On Fri, Feb 19, 2021 at 2:44 AM Akhil P Oommen wrote:
On 2/18/2021 9:41 PM, Rob Clark wrote:
On Thu, Feb 18, 2021 at 4:28 AM Akhil P Oommen wrote:
On 2/18/2021 2:05 AM, Jonathan Marek wrote:
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021
On 11/16/2020 9:52 PM, Rob Clark wrote:
On Mon, Nov 16, 2020 at 6:34 AM Akhil P Oommen wrote:
On 11/12/2020 10:07 PM, Rob Clark wrote:
On Thu, Nov 12, 2020 at 7:49 AM Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed
Extend speed-bin support to a618 gpu.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index e0ff16c..21db7ae 100644
--- a
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend speed-bin support to a6x family.
Signed-off-by: Akhil P Oommen
---
Changes from v1:
1. Added
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
On 11/16/2020 10:44 PM, Jordan Crouse wrote:
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote:
On 11/12/2020 10:05 PM, Jordan Crouse wrote:
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a
On 11/30/2020 10:32 PM, Jordan Crouse wrote:
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation
<< Resending since Jordan wasn't in the CC list >>
On 11/30/2020 10:32 PM, Jordan Crouse wrote:
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch m
On 12/2/2020 10:00 PM, Jordan Crouse wrote:
On Wed, Dec 02, 2020 at 08:53:51PM +0530, Akhil P Oommen wrote:
On 11/30/2020 10:32 PM, Jordan Crouse wrote:
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618 gpu.
Signed-off-by: Akhil P Oommen
---
Changes
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
On 11/5/2020 2:28 AM, Rob Clark wrote:
On Wed, Nov 4, 2020 at 12:03 PM Rob Herring wrote:
On Fri, 30 Oct 2020 16:17:12 +0530, Akhil P Oommen wrote:
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend speed-bin support to a6x family.
Signed-off-by: Akhil P Oommen
---
This patch is rebased on top of
On 11/12/2020 10:05 PM, Jordan Crouse wrote:
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation
On 11/12/2020 10:07 PM, Rob Clark wrote:
On Thu, Nov 12, 2020 at 7:49 AM Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend
On 3/11/2022 5:16 AM, Rob Clark wrote:
From: Rob Clark
The mutex wasn't really protecting anything before. Before the previous
patch we could still be racing with the scheduler's kthread, as that is
not necessarily frozen yet. Now that we've parked the sched threads,
the only race is with job
://patchwork.freedesktop.org/series/99048/
Akhil P Oommen (5):
drm/msm: Use generic name for gpu resources
drm/msm/adreno: Generate name from chipid for 7c3
drm/msm/a6xx: Add support for 7c3 SKUs
drm/msm/adreno: Expose speedbin to userspace
arm64: dts: qcom: sc7280: Support gpu speedbin
arch
Use generic name for resources like irq and kthread instead of hardware
specific name to make it easier to grep.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu
Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of
hardcoding one. This helps to avoid code churn in case of a gpu rename.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 -
drivers/gpu/drm/msm/adreno/adreno_gpu.c
Add support for 7c3 SKU detection using speedbin fuse.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 17cfad64
Add speedbin fuse and additional OPPs for gpu to support sc7280 SKUs.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts
Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
identify the sku.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
3
On 2/23/2022 6:28 AM, Rob Clark wrote:
On Mon, Feb 21, 2022 at 6:41 AM Akhil P Oommen wrote:
Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of
hardcoding one. This helps to avoid code churn in case of a gpu rename.
Signed-off-by: Akhil P Oommen
---
drivers/gp
://patchwork.freedesktop.org/series/99048/
Changes in v2:
- use devm_kasprintf() to generate gpu name (Rob)
Akhil P Oommen (5):
drm/msm: Use generic name for gpu resources
drm/msm/adreno: Generate name from chipid for 7c3
drm/msm/a6xx: Add support for 7c3 SKUs
drm/msm/adreno: Expose speedbin to
Use generic name for resources like irq and kthread instead of hardware
specific name to make it easier to grep.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/msm_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm
Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of
hardcoding one. This helps to avoid code churn in case of a gpu rename.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- use devm_kasprintf() to generate gpu name (Rob)
drivers/gpu/drm/msm/adreno/adreno_device.c
Add support for 7c3 SKU detection using speedbin fuse.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
identify the sku.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 +
drivers/gpu/drm/msm/adreno
Add speedbin fuse and additional OPPs for gpu to support sc7280 SKUs.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b
the related code.
Akhil P Oommen (10):
drm/msm/a6xx: Add helper to check smmu is stalled
drm/msm/a6xx: Send NMI to gmu when it is hung
drm/msm/a6xx: Avoid gmu lock in pm ops
drm/msm/a6xx: Enhance debugging of gmu faults
drm/msm: Do recovery on hw_init failure
drm/msm/a6xx: Propagate
Add a helper function to check for stalled smmu and also avoid reading
RBBM_STATUS3 register which is in GX domain before ensuring GX is
ON.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers
While capturing gmu state, first send an NMI to gmu when it is hung.
This helps to move gmu to a safe state.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm
ed to capture the gmu states inline before it is
collapsed.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 +++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 60 +
drivers/gp
We don't really need gmu lock in runtime pm ops because these operations
are serialized anyway and also with other paths where we take this lock.
This patch will help to simplify the locking order when we introduce
crashstate_lock in the upcoming patch.
Signed-off-by: Akhil P O
Schedule the recover worker when there is hw init failure in
msm_gpu_submit(). The recover worker will take care of capturing
coredump, gpu recovery and resubmission of pending IBs.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gpu.c | 5 -
1 file changed, 4 insertions(+), 1
Retry infinitely on resume failure because there is nothing much we can
do if GPU is not ON. Also, this helps us to avoid checking for the
return value of pm_runtime_get() to see if GPU is ON.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 10 +-
1 file
Remove vote on clks on gpu resume failure.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 66ae509..e90359f 100644
--- a/drivers/gpu
We do pm_runtime_get() within msm_gpu_submit(). So remove the redundant
pm_runtime_get/put from msm_job_run().
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_ringbuffer.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c
b/drivers/gpu/drm
Free gmu_debug bo while destroying the gpu crashstate.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 4d4588a
Propagate OOB set error to higher level so that a coredump is captured
followed by recovery sequence.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 33 -
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 19 ---
drivers/gpu/drm
On 3/3/2022 2:51 PM, AngeloGioacchino Del Regno wrote:
Il 02/03/22 18:27, Akhil P Oommen ha scritto:
Retry infinitely on resume failure because there is nothing much we can
do if GPU is not ON. Also, this helps us to avoid checking for the
return value of pm_runtime_get() to see if GPU is ON
)adreno_gpu->rev.core << 24);
if (!adreno_gpu->info->revn)
*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
return 0;
Reviewed-by: Akhil P Oommen
-Akhil
RRAY_SIZE(a6xx_protect);
+ count_max = 32;
+ BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
}
/*
Reviewed-by: Akhil P Oommen
-Akhil.
eue.c | 39 +
include/uapi/drm/msm_drm.h| 28 +-
35 files changed, 1058 insertions(+), 1130 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h
For the whole series except " drm/msm: Update generated headers",
Reviewed-by: Akhil P Oommen
-Akhil.
On 9/9/2021 9:42 PM, Amit Pundir wrote:
On Thu, 9 Sept 2021 at 17:47, Amit Pundir wrote:
On Wed, 8 Sept 2021 at 07:50, Bjorn Andersson
wrote:
On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
On 8/9/2021 9:48 PM, Caleb Connolly wrote:
On 09/08/2021 17:12, Rob Clark wrote:
On Mon
On 9/10/2021 11:04 PM, Caleb Connolly wrote:
On 10/09/2021 18:18, Rob Clark wrote:
On Tue, Sep 7, 2021 at 7:20 PM Bjorn Andersson
wrote:
On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
On 8/9/2021 9:48 PM, Caleb Connolly wrote:
On 09/08/2021 17:12, Rob Clark wrote:
On Mon, Aug 9
On 9/27/2021 8:59 PM, Rob Clark wrote:
From: Rob Clark
I've seen a few crashes like:
Internal error: synchronous external abort: 9610 [#1] PREEMPT SMP
Modules linked in: snd_seq_dummy snd_seq snd_seq_device bridge stp llc tun
nf_nat_tftp nf_conntrack_tftp nf_nat_ftp nf_conntrack
.gpu_set_freq = a6xx_gmu_set_freq,
+ .gpu_set_freq = a6xx_gpu_set_freq,
#if defined(CONFIG_DRM_MSM_GPU_STATE)
.gpu_state_get = a6xx_gpu_state_get,
.gpu_state_put = a6xx_gpu_state_put,
I think I overlooked this because every hw access is serialized in the
downstream driver.
Reviewed-by: Akhil P Oommen
-Akhil
On 1/13/2022 12:43 PM, Dmitry Baryshkov wrote:
On Thu, 13 Jan 2022 at 00:19, Rob Clark wrote:
On Tue, Jan 11, 2022 at 1:31 PM Akhil P Oommen wrote:
Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
identify the sku.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm
Add support for "Adreno 8c Gen 3" gpu along with the necessary speedbin
support.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Fix a bug in adreno_cmp_rev()
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 21 ++
drivers/gpu/drm/msm/adreno/adreno_dev
Add the speedbin fuse and the required opps to support gpu sku.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch
Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
identify the sku.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Use SKU in chipid PARAM only in new targets (Rob)
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions
Update the name in the gpulist for 7c3 gpu as per the latest
recommendation.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b
static int msm_devfreq_target(struct device *dev, unsigned
long *freq,
*/
if (gpu->devfreq.idle_freq) {
gpu->devfreq.idle_freq = *freq;
+ dev_pm_opp_put(opp);
return 0;
}
Reviewed-by: Akhil P Oommen
-Akhil
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