On 11/4/24 11:16, Boris Brezillon wrote:
Hi Akash,
On Thu, 31 Oct 2024 21:42:27 +
Akash Goel wrote:
I assume you also reckon that there is a potential problem here for arm64.
It impacts any system that's not IO-coherent I would say, and this
comment seems to prove this is a
that there are dirty cachelines in the CPU cache
for the BOs, when they are accessed from the CPU side through uncached
CPU mapping, and the eviction of cachelines overwrites the data of BOs.
This commit tries to avoid the potential overwrite scenario.
v2:
- no change
Signed-off-by: Akash Goel
feature/enable register is
required to avoid potential misalignment on certain platforms.
- The third fix, regarding the potential overwrite of buffer objects,
has been prepared speculatively & it may not be required in practice.
v2:
- Added r-b tags for the first 2 patches
Akash Goel (3):
protocal and is required by the Userspace driver to
ensure coherency between the shader cores.
v2:
- Added R-b tags
Signed-off-by: Akash Goel
Reviewed-by: Boris Brezillon
Reviewed-by: Liviu Dudau
Reviewed-by: Steven Price
---
drivers/gpu/drm/panthor/panthor_mmu.c | 23 +++
1 f
OHERENCY_ENABLE
register is implementation defined, so it may not be always aligned with
the "dma-coherent" property value.
The commit also checks the COHERENCY_FEATURES register to confirm that
the coherency protocol is actually supported or not.
v2:
- Added R-b tags
Signed-off-by: Akash
feature/enable register is
required to avoid potential misalignment on certain platforms.
- The third fix, regarding the potential overwrite of buffer objects,
has been prepared speculatively & it may not be required in practice.
Please provide feedback on it.
Akash Goel (3):
drm/panthor: Up
OHERENCY_ENABLE
register is implementation defined, so it may not be always aligned with
the "dma-coherent" property value.
The commit also checks the COHERENCY_FEATURES register to confirm that
the coherency protocol is actually supported or not.
Signed-off-by: Akash Goel
---
drivers/gpu/drm
the pages didn't get map at the expected virtual address and
consequently there were kernel warnings on unmap.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/panthor/panthor_mmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c
b/drivers/gpu/drm/pantho
lock")
Reviewed-by: Liviu Dudau
Reviewed-by: Steven Price
Signed-off-by: Akash Goel
---
drivers/gpu/drm/panthor/panthor_mmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c
b/drivers/gpu/drm/panthor/panthor_mmu.c
index d8cc9e7d064e..8d051
that there are dirty cachelines in the CPU cache
for the BOs, when they are accessed from the CPU side through uncached
CPU mapping, and the eviction of cachelines overwrites the data of BOs.
This commit tries to avoid the potential overwrite scenario.
Signed-off-by: Akash Goel
---
drivers/gpu
protocal and is required by the Userspace driver to
ensure coherency between the shader cores.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/panthor/panthor_mmu.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c
b/
On 10/24/24 16:39, Boris Brezillon wrote:
On Thu, 24 Oct 2024 15:54:32 +0100
Akash Goel wrote:
All CPU mappings are forced as uncached for Panthor buffer objects when
system(IO) coherency is disabled. Physical backing for Panthor BOs is
allocated by shmem, which clears the pages also after
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