Am 09.05.25 um 13:06 schrieb Fabio Estevam:
Hi Javier and Thomas,
On Tue, Apr 22, 2025 at 6:53 PM Javier Martinez Canillas
wrote:
Fabio Estevam writes:
Hello Fabio,
From: Fabio Estevam
Since commit 559358282e5b ("drm/fb-helper: Don't use the preferred depth
for the BPP default"), RGB5
Hi André,
[...]
> @@ -582,6 +584,14 @@ int drm_dev_wedged_event(struct drm_device *dev,
> unsigned long method)
> drm_info(dev, "device wedged, %s\n", method == DRM_WEDGE_RECOVERY_NONE ?
>"but recovered through reset" : "needs recovery");
>
> + if (info) {
> +
From: Dave Airlie
Discrete and Integrated GPUs can use system RAM instead of
VRAM for all or some allocations. These allocations happen
via drm/ttm subsystem and are currently not accounted for
in cgroups.
Add a gpu statistic to allow a place to visualise allocations
once they are supported.
Si
From: Dave Airlie
As per the socket hooks, just adds two APIs to charge GPU pages
to the memcg and uncharge them.
Suggested by Waiman.
Signed-off-by: Dave Airlie
---
include/linux/memcontrol.h | 5 +
mm/memcontrol.c| 34 ++
2 files changed, 39
Hey,
This is my 3rd attempt to try and integrate ttm and memcg accounting.
I've tried to take on board the feedback given on the last series, and
made some compromises to try and close in on the solution.
Feedback:
1. memcg folks didn't really like the gpu specific stats due to a lack
of global
From: Dave Airlie
These will be used to track pages actively allocated to the GPU,
and unused pages in pools that can be reclaimed by the shrinker.
Signed-off-by: Dave Airlie
---
Documentation/filesystems/proc.rst | 6 ++
drivers/base/node.c| 5 +
fs/proc/meminfo.c
From: Dave Airlie
This uses the per-node stats to track GPU memory allocations,
across nodes when available. It also tracks the memory in the
pool.
---
drivers/gpu/drm/ttm/ttm_pool.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/tt
From: Dave Airlie
This adds the memcg object for any user allocated objects,
add uses the MEMCG placement flags in the correct places.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 2 ++
drivers/gpu/drm/amd/a
From: Dave Airlie
Doing proper integration of TTM system memory allocations with
memcg is a difficult ask, primarily due to difficulties around
accounting for evictions properly.
However there are systems where userspace will be allocating
objects in system memory and they won't be prone to migr
From: Dave Airlie
This just adds the memcg init and memcg placement flag support.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 5 +++--
drivers/gpu/drm/nouveau/nouveau_gem.c | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau
Hello fbdev maintainers/developers,
This is a 31-day syzbot report for the fbdev subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/fbdev
During the period, 0 new issues were detected and 0 were fixed.
In total, 6 issues are still open and 25 have
Hi
Am 09.05.25 um 16:26 schrieb André Almeida:
Replace open-coded mutex handling with cleanup.h guard(mutex). This
simplifies the code and removes the "goto unlock" pattern.
Tested with igt tests core_auth and core_setmaster.
Signed-off-by: André Almeida
Reviewed-by: Thomas Zimmermann
but
Add a section about "App information" for the wedge API.
Signed-off-by: André Almeida
---
Documentation/gpu/drm-uapi.rst | 15 +++
1 file changed, 15 insertions(+)
diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst
index 69f72e71a96e..826abe265a24 100644
--
To notify userspace about which app (if any) made the device get in a
wedge state, make use of drm_wedge_app_info parameter, filling it with
the app PID and name.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +--
drivers/gpu/drm/amd/amdgpu/amdg
When a device get wedged, it might be caused by a guilty application.
For userspace, knowing which app was the cause can be useful for some
situations, like for implementing a policy, logs or for giving a chance
for the compositor to let the user know what app caused the problem.
This is an optiona
This patchset implements a request made by Xaver Hugl about wedge events:
"I'd really like to have the PID of the client that triggered the GPU
reset, so that we can kill it if multiple resets are triggered in a
row (or switch to software rendering if it's KWin itself) and show a
user-friendly not
On Sun, 20 Apr 2025 17:12:42 +0200, Luca Weiss wrote:
> Since the interconnect driver for msm8953 is already upstream, let's add
> the nodes which are required for it to enable interconnect on MSM8953.
>
>
Applied, thanks!
[2/2] arm64: dts: qcom: msm8953: Add interconnects
commit: 6aeda
From: Vinod Polimera
[ Upstream commit c0cd12a5d29fa36a8e2ebac7b8bec50c1a41fb57 ]
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewe
On Thu, 8 May 2025 15:06:07 +0200
Markus Burri wrote:
> The buffer is set to 80 character. If a caller write more characters,
> count is truncated to the max available space in "simple_write_to_buffer".
> But afterwards a string terminator is written to the buffer at offset count
> without bound
On Fri, May 09, 2025 at 02:28:55PM +0200, Konrad Dybcio wrote:
> On 5/8/25 10:12 PM, Connor Abbott wrote:
> > On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
> >>
> >> From: Konrad Dybcio
> >>
> >> Add a file that will serve as a single source of truth for UBWC
> >> configuration data for var
From: Abhinav Kumar
[ Upstream commit aedf02e46eb549dac8db4821a6b9f0c6bf6e3990 ]
For cases where the crtc's connectors_changed was set without enable/active
getting toggled , there is an atomic_enable() call followed by an
atomic_disable() but without an atomic_mode_set().
This results in a NUL
In DCN401 pre-blending degamma LUT isn't affecting cursor as in previous
DCN version. As this is not the behavior close to what is expected for
CRTC degamma LUT, disable CRTC degamma LUT property in this HW.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/4176
Signed-off-by: Melissa Wen
---
From: Jernej Skrabec
The Allwinner DE2 and DE3 display engine mixers are currently identified
by a simple boolean flag. This will not scale to support additional DE
variants.
Convert the boolean flag to an enum.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Reviewed-by: Andre Przy
From: Jernej Skrabec
Use the new blender register lookup function where required in the layer
commit and update code.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
---
Changelog v2..v3:
- Refactor for 6.11 layer init/modesetting changes
---
drivers/gpu/drm/sun4i/sun8i_mixer.c
The Allwinner H616 and variants have a new display engine revision
(DE33).
The mixer configuration registers are significantly different to the DE3
and DE2 revisions, being split into separate top and display blocks,
therefore a fallback for the mixer compatible is not provided.
Note that the DE3
From: Jernej Skrabec
The vi_scaler appears to be used in preference to the ui_scaler module
for hardware video scaling in the DE33.
Enable support for this scaler.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
---
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 20
From: Jernej Skrabec
The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.
Notable features (from the H616 datasheet and implemented):
- 4096 x 2048 (4K) output support
Other f
From: Jernej Skrabec
The DE2 and DE3 engines have a blender register range within the
mixer engine register map, whereas the DE33 separates this out into
a separate display group.
Prepare for this by adding a function to look the blender reference up,
with a subsequent patch to add a conditional
Hi all,
v10 of this patch series adding support for the Allwinner DE33 display engine.
This version is largely based on the previous v8 patch, with Chris's changes to
the mixer bindings in particular from v9 to add names for the new register
blocks. As discussed, the H616 LCD support patchset (
The Allwinner H616 and variants have a new display engine revision
(DE33).
Add a clock binding for the DE33.
Signed-off-by: Ryan Walklin
Acked-by: Conor Dooley
Reviewed-by: Chen-Yu Tsai
---
Changelog v2..v3:
- Separate content into three patches for three separate subsystems
---
.../devicetr
From: Jernej Skrabec
Now that the DE variant can be selected by enum, take the oppportunity
to factor out some common initialisation code to a separate function.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Reviewed-by: Andre Przywara
---
Changelog v1..v2:
- Combine base registe
From: Jernej Skrabec
The H616 (and related SoC packages sharing the same die) carry the new
DE33 display engine.
Add the mixer configuration and a compatible string for the H616 to the
mixer.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
--
Changelog v7..v8:
- Separate DE33 suppo
The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.
The DE33 in the H616 has mixer0 and writeback units. The clocks
and resets required are identical to the H3 and H5 respective
The Allwinner H616 and variants have a new display engine revision
(DE33).
Add a display engine bus binding for the DE33.
Signed-off-by: Ryan Walklin
Acked-by: Conor Dooley
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Chris Morgan
---
Changelog v1..v2:
- Correct DE2 bus enum to reflect fallback
* Christophe JAILLET (christophe.jail...@wanadoo.fr) wrote:
> Le 18/04/2025 à 02:21, li...@treblig.org a écrit :
> > From: "Dr. David Alan Gilbert"
> >
> > radeon_doorbell_free() was added in 2013 by
> > commit 75efdee11b5d ("drm/radeon: implement simple doorbell page
> > allocator")
> > but neve
On 5/1/2025 9:23 PM, Konrad Dybcio wrote:
> On 5/1/25 11:29 AM, Akhil P Oommen wrote:
>> On 4/30/2025 10:26 PM, neil.armstr...@linaro.org wrote:
>>> On 30/04/2025 18:39, Konrad Dybcio wrote:
On 4/30/25 6:19 PM, neil.armstr...@linaro.org wrote:
> On 30/04/2025 17:36, Konrad Dybcio wrote:
>>
On Thu, May 08, 2025 at 08:12:33PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
I'd prefer this to contain some of the problem description from the
cover letter.
Regards,
Bjorn
> Add a file that will serve as a single source of truth for UBWC
> configuration data for various multimedia
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