We start to have support many Sitronix displays in the tiny directory,
and we expect more to come.
Move them to their own subdirectory.
Reviewed-by: Javier Martinez Canillas
Suggested-by: Javier Martinez Canillas
Signed-off-by: Marcus Folkesson
---
Changes in v2:
- Rebase on drm-misc-next
- Li
On 02/05/2025 14:52, Devarsh Thakkar wrote:
Hi,
It uses hw_id i.e. 1 for all vid irqstatus related registers since it is
accessing am65x common region register space which has vid on idx0 which
we want to skip for am62l.
For dispc_plane_enable(), the caller uses
0, for dispc_k3_vid_write_irq
R61307 is liquid crystal driver for high-definition amorphous silicon
(a-Si) panels and is ideal for tablets and smartphones.
Signed-off-by: Svyatoslav Ryhel
---
.../display/panel/renesas,r61307.yaml | 95 +++
1 file changed, 95 insertions(+)
create mode 100644
Document
R61307 is liquid crystal driver for high-definition amorphous silicon
(a-Si) panels and is ideal for tablets and smartphones.
Supported compatibles are:
- hit,tx13d100vm0eaa
- koe,tx13d100vm0eaa
Signed-off-by: Svyatoslav Ryhel
---
drivers/gpu/drm/panel/Kconfig| 13 +
drivers/gp
R69328 is liquid crystal driver for high-definition amorphous silicon
(a-Si) panels and is ideal for tablets and smartphones.
Signed-off-by: Svyatoslav Ryhel
---
.../display/panel/renesas,r69328.yaml | 74 +++
1 file changed, 74 insertions(+)
create mode 100644
Document
пн, 3 бер. 2025 р. о 14:05 Svyatoslav Ryhel пише:
>
> Triple 10-BIT LVDS Transmitter is used in Microsoft Surface RT and
> MStar TSUMU88ADT3-LF-1 HDMI bridge is used in ASUS Transformer AiO
> P1801-T.
>
> ---
> Changes on switching from v2 to v3:
> - place mstar,tsumu88adt3-lf-1 alphabetically
> -
Add support for panels used in LG P880/P895 which are based on Renesas IC
(not related to Renesas RISC-V architecture just the same manufacturer).
---
Changes in v2:
- added IC vendor compatible ass fallback
- renamed renesas,inversion > renesas,column-inversion
---
Maxim Schwalm (1):
drm: pane
From: Maxim Schwalm
Driver adds support for panels with Renesas R69328 IC
Currently supported compatible is:
- jdi,dx12d100vm0eaa
Co-developed-by: Svyatoslav Ryhel
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Maxim Schwalm
---
drivers/gpu/drm/panel/Kconfig| 13 +
drivers/
SSD2825 is a cost-effective MIPI Bridge Chip solution targeting mainly
smartphones. It can convert 24bit RGB interface into 4-lane MIPI-DSI
interface to drive display modules of up to 800 x 1366, while supporting
AMOLED, a-si LCD or LTPS panel technologies for smartphone applications.
Signed-off-b
Add bindings for Solomon SSD2825 MIPI master bridge chip that connects an
application processor with traditional parallel LCD interface and an LCD
driver with MIPI slave interface. The SSD2825 supports both parallel RGB
interface and serial SPI interface.
Signed-off-by: Svyatoslav Ryhel
Reviewed-
Solomon SSD2825 is a RGB to MIPI DSI bridge used in LG Optimus 4D P880
and LG Optimus Vu P895
---
Changes on switching from v3 to v4:
- no changes, resend
Changes on switching from v2 to v3:
- added mutex guard
- configuration register flags parametrized using panel flags
- removed unneded debug
On 4/23/2025 6:58 PM, Dmitry Baryshkov wrote:
> On Sat, Apr 19, 2025 at 08:21:32PM +0530, Akhil P Oommen wrote:
>> Fix the following for qmp_get() errors:
>>
>> 1. Correctly handle probe defer for A6x GPUs
>> 2. Ignore other errors because those are okay when GPU ACD is
>> not required. They are ch
This series adds support for ACD feature for Adreno GPU which helps to
lower the power consumption on GX rail and also sometimes is a requirement
to enable higher GPU frequencies. At high level, following are the
sequences required for ACD feature:
1. Identify the ACD level data for each re
ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
the power consumption. In some chipsets, it is also a requirement to
support higher GPU frequencies. This patch adds support for GPU ACD by
sending necessary data to GMU and AOSS. The feature support for the
chipset is detecte
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-off-by: Akhil P Oommen
---
d
Update GPU node to include acd level values.
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot
Add a new schema which extends opp-v2 to support a new vendor specific
property required for Adreno GPUs found in Qualcomm's SoCs. The new
property called "qcom,opp-acd-level" carries a u32 value recommended
for each opp needs to be shared to GMU during runtime.
Also, update MAINTAINERS file inclu
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Reviewed-by: Konrad Dybcio
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno/adr
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 +++-
Fix the following for qmp_get() errors:
1. Correctly handle probe defer for A6x GPUs
2. Ignore other errors because those are okay when GPU ACD is
not required. They are checked again during gpu acd probe.
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-o
The global workqueue is only used for vblanks inside KMS code. Move
allocation / flushing / deallcation of it to msm_kms.c
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/mdp5/m
Drop superfluous msm_drm_private::num_crtcs in favour of using
drm_mode_config::num_crtc or MAX_CRCS as appropriate.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 3 ---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c |
Data for HDMI, DSI and DP blocks only makes sense for the KMS parts of
the driver. Move corresponding data pointers from struct msm_drm_private
to struct msm_kms.
Suggested-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11
dri
There is no reason to store CRTC id, it's a part of the drm_crtc. Drop
this member and use drm_crtc.name for the warning message.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 7 ++-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp/
If the Adreno device is used in a headless mode, there is no need to
build all KMS components. Build corresponding parts conditionally, only
selecting them if modeset support is actually required.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 14 +
drivers/gp
Both perf and hangrd make sense only for GPU devices. Bail out if we are
registering a KMS-only device.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_debugfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_debugfs.c
b/drivers/gpu/drm/msm/msm_debu
Currently the msm driver creates an extra interim platform device for
Imageon GPUs. This is not ideal, as the device doesn't have
corresponding OF node. If the headless mode is used for newer GPUs, then
the msm_use_mmu() function can not detect corresponding IOMMU devices.
Also the DRM device (alth
Move symbol selection to be more fine grained: select DP helpers only if
DP driver is also enabled, move KMS and display helpers to the newly
introduced DRM_MSM_KMS.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 20 ++--
1 file changed, 10 insertions(+), 10 de
Currently the KMS and GPU parts of the msm driver are pretty much
intertwined. It is impossible to register a KMS-only device and
registering a GPU-only DRM device requires modifying the DT. Not to
mention that binding the GPU-only device creates an interim platform
devices, which complicates IOMM
Extract two more KMS-related codepieces to msm_kms.c, removing last
pieces of KMS code from msm_drv.c.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 9 +++--
drivers/gpu/drm/msm/msm_kms.c | 20
drivers/gpu/drm/msm/msm_km
There are cases when we want to have separate DRM devices for GPU and
display pipelines.
One example is development, when it is beneficial to be able to bind the
GPU driver separately, without the display pipeline (and without the
hacks adding "amd,imageon" to the compatible string).
Another exampl
Some of the platforms don't have onboard GPU or don't provide support
for the GPU in the drm/msm driver. Make it possible to disable the GPU
part of the driver and build the KMS-only part.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 20 +++--
drivers/gpu/drm/msm/
On Sat May 3, 2025 at 12:02 PM JST, Joel Fernandes wrote:
>
>
> On 5/2/2025 9:59 PM, Alexandre Courbot wrote:
>>> pub trait AlignUp {
>>> fn align_up(self, alignment: Self) -> Self;
>>> }
>>>
>>> macro_rules! align_up_impl {
>>> ($($t:ty),+) => {
>>> $(
>>> impl AlignUp
On Fri, May 2, 2025, at 3:25 PM, Alex Hung wrote:
> Hi James,
>
> checkpatch reports the following warning and error
>
> WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit
> description?)
> #18:
> Adds a kernel-doc for externally linked dc_stream_remove_writeback()
> functio
On Sat May 3, 2025 at 12:02 PM JST, Joel Fernandes wrote:
>
>
> On 5/2/2025 9:59 PM, Alexandre Courbot wrote:
>>> pub trait AlignUp {
>>> fn align_up(self, alignment: Self) -> Self;
>>> }
>>>
>>> macro_rules! align_up_impl {
>>> ($($t:ty),+) => {
>>> $(
>>> impl AlignUp
Am Dienstag, 22. April 2025, 09:04:39 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> When preparing to convert the current inno hdmi driver into a
> bridge driver, I found that there are several issues currently
> existing with it:
>
> 1. When the system starts up, the firs
Add a test to submit a single job against a scheduler with the timeout
configured and verify that if the job is still running, the timeout
handler will skip the reset and allow the job to complete.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/scheduler/tests/mock_scheduler.c | 3 ++
drivers/g
When the DRM scheduler times out, it's possible that the GPU isn't hung;
instead, a job may still be running, and there may be no valid reason to
reset the hardware. This can occur in two situations:
1. The GPU exposes some mechanism that ensures the GPU is still making
progress. By checkin
Xe can skip the reset if TDR has fired before the free job worker. Instead
of using the scheduler internals to add the job to the pending list, use
the DRM_GPU_SCHED_STAT_RUNNING status to skip the reset and rearm the
timer.
Note that there is no need to restart submission if it hasn't been
stoppe
When a CL/CSD job times out, we check if the GPU has made any progress
since the last timeout. If so, instead of resetting the hardware, we skip
the reset and allow the timer to be rearmed. This gives long-running jobs
a chance to complete.
Use the DRM_GPU_SCHED_STAT_RUNNING status to skip the res
Etnaviv can skip a hardware reset in two situations:
1. TDR has fired before the IRQ and the timeout is spurious.
2. The GPU is still making progress on the front-end and we can give
the job a chance to complete.
Instead of relying on the scheduler internals, use the
DRM_GPU_SCHED_STAT_R
Currently, if we add the assertions presented in this commit to the mock
scheduler, we will see the following output:
[15:47:08] == [PASSED] drm_sched_basic_tests ==
[15:47:08] drm_sched_basic_timeout_tests (1 subtest) =
[15:47:08] # drm_sched_basic_timeout
As more KUnit tests are introduced to evaluate the basic capabilities of
the `timedout_job()` hook, the test suite will continue to increase in
duration. To reduce the overall running time of the test suite, decrease
the scheduler's timeout for the timeout tests.
Before this commit:
[15:42:26] El
When the DRM scheduler times out, it's possible that the GPU isn't hung;
instead, a job may still be running, and there may be no valid reason to
reset the hardware. This can occur in two situations:
1. The GPU exposes some mechanism that ensures the GPU is still making
progress. By checkin
Am Montag, 28. April 2025, 12:23:07 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> Convert it to drm bridge driver, it will be convenient for us to
> migrate the connector part to the display driver later.
>
> Note: I don't have the hardware to test this driver, so for now
Adds kernel-doc for externally linked dc_stream_remove_writeback function.
Signed-off-by: James Flowers
---
V1 -> V2: Corrected checkpatch warnings and errors
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/
Panfrost can skip the reset if TDR has fired before the IRQ handler.
Currently, since Panfrost doesn't take any action on these scenarios, the
job is being leaked, considering that `free_job()` won't be called.
To avoid such leaks, use the DRM_GPU_SCHED_STAT_RUNNING status to skip the
reset and re
Hi Alex
Thanks for the response.
My updates below. I also had one question for Abel below.
Thanks
Abhinav
On 5/1/2025 8:56 AM, Aleksandrs Vinarskis wrote:
On Thu, 1 May 2025 at 04:11, Abhinav Kumar wrote:
On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
DisplayPort requires per-segmen
48 matches
Mail list logo
