https://bugzilla.kernel.org/show_bug.cgi?id=220043
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Reso
On Thu, 17 Apr 2025 14:19:42 +0200
Boris Brezillon wrote:
> Right now the DRM_PANTHOR_BO_NO_MMAP flag is ignored by
> panthor_ioctl_bo_mmap_offset(), meaning BOs with this flag set can
> have a file offset but can't be mapped anyway, because
> panthor_gem_mmap() will filter them out.
>
> If we e
https://bugzilla.kernel.org/show_bug.cgi?id=220041
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Reso
On 4/22/2025 2:07 PM, Christian König wrote:
Am 17.04.25 um 18:10 schrieb Sunil Khatri:
drm_file will be used in usermode queues code to
enable better process information in logging and hence
add drm_file part of the userq_mgr struct.
update the drm_file pointer in userq_mgr for each
amdgpu_d
Am 17.04.25 um 18:10 schrieb Sunil Khatri:
> Add a drm helper function which appends the process information for
> the drm_file over drm_err formatted output.
>
> v5: change to macro from function (Christian Koenig)
> add helper functions for lock/unlock (Christian Koenig)
>
> v6: remove __mayb
On Tue, 22 Apr 2025 12:12:21 +0200
Geert Uytterhoeven wrote:
> Hi Pekka,
>
> On Tue, 22 Apr 2025 at 12:01, Pekka Paalanen wrote:
> > On Tue, 22 Apr 2025 11:41:29 +0200
> > Geert Uytterhoeven wrote:
> > > On Tue, 22 Apr 2025 at 11:11, Pekka Paalanen
> > > wrote:
> > > > On Mon, 21 Apr 2025
On Tue, Apr 22, 2025 at 12:28:20PM +0530, Ayushi Makhija wrote:
> On 4/17/2025 4:10 PM, Dmitry Baryshkov wrote:
> > On Thu, Apr 17, 2025 at 11:09:05AM +0530, Ayushi Makhija wrote:
> >> From: Ayushi Makhija
> >>
> >> Add anx7625 DSI to DP bridge device nodes.
> >>
> >> Signed-off-by: Ayushi Makhija
On Tue, Apr 22, 2025 at 08:03:52AM +0300, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Arun
> > R
> > Murthy
> > Sent: Thursday, April 17, 2025 4:22 PM
> > To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> > x...@lists.fr
On Thu, 17 Apr 2025 15:19:45 +
Simon Ser wrote:
> On Monday, April 14th, 2025 at 13:06, Pekka Paalanen
> wrote:
>
> > Looking good, but given the new wording is 100% mine, not sure I can
> > give reviewed-by?
> >
> > Co-authored-by maybe?
>
> Since it's 100% yours, probably you should
use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Wentao-Liang/drm-amdgpu-Remove-redundant-return-value-checks-for-amdgpu_ras_error_data_init/20250422-153759
base: https://git.kernel.o
On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ursulin wrote:
> Question I raised is if there are other drivers which manage to clean up
> everything correctly (like the mock scheduler does), but trigger that
> warning. Maybe there are not and maybe mock scheduler is the only false
> positive.
S
On Tue, 2025-04-22 at 04:49 +, Murthy, Arun R wrote:
>
> > -Original Message-
> > From: Govindapillai, Vinod
> > Sent: Tuesday, April 22, 2025 4:17 AM
> > To: Murthy, Arun R ; dri-
> > de...@lists.freedesktop.org; intel...@lists.freedesktop.org; intel-
> > g...@lists.freedesktop.org
>
Hi
Am 20.04.25 um 14:19 schrieb Ryosuke Yasuoka:
Drop simple-KMS in favor of regular atomic helpers to make the code more
modular. The simple-KMS helper mix up plane and CRTC state, so it is
obsolete and should go away [1]. Since it just split the simple-pipe
funtions into per-plane and per-CRTC
Hi,
On Mon, 21 Apr 2025 22:12:58 +0200, Martin Blumenstingl wrote:
> This is a successor of a previous patchset by Christian [0]
>
> Patch 1 reverts a previous fix for loss of HDMI sync when playing YUV420
> @ 59.94 media. The patch does resolve a calculation issue. It also makes
> all fractional
On 19/04/2025 18:31, David Heidelberg via B4 Relay wrote:
From: Casey Connolly
We never properly supported this panel and always used the wrong init
sequence. Drop support so we can move it to it's own proper driver.
Fixes: 5933baa36e26 ("drm/panel/samsung-sofef00: Add panel for OnePlus 6/T
d
The function amdgpu_ras_error_data_init() always returns 0, making its
return value checks redundant. This patch changes its return type to
void and removes all unnecessary checks in the callers.
This simplifies the code and avoids confusion about the function's
behavior. Additionally, this change
On 17/04/2025 21:55, Hugo Villeneuve wrote:
From: Hugo Villeneuve
commit a8972d5a49b4 ("drm: panel: jd9365da-h3: fix reset signal polarity")
fixed reset signal polarity in jadard_dsi_probe() and jadard_prepare().
It was not done in jadard_unprepare() because of an incorrect assumption
about re
Hi,
On Sat, 19 Apr 2025 09:42:08 +0530, Tejas Vipin wrote:
> panel-samsung-sofef00 is the last remaining user of
> mipi_dsi_dcs_write_seq, so mipi_dsi_dcs_write_seq can be removed after
> the panel has been changed to use mipi_dsi_*_multi functions.
>
> Tejas Vipin (2):
> drm/panel: panel-samsu
Hi Prabhakar,
On Fri, 18 Apr 2025 at 20:47, Prabhakar wrote:
> From: Lad Prabhakar
>
> Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
> precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
> high accuracy.
>
> These changes prepare the driver for upcoming
Hi,
On Thu, 17 Apr 2025 15:55:06 -0400, Hugo Villeneuve wrote:
> commit a8972d5a49b4 ("drm: panel: jd9365da-h3: fix reset signal polarity")
> fixed reset signal polarity in jadard_dsi_probe() and jadard_prepare().
>
> It was not done in jadard_unprepare() because of an incorrect assumption
> abou
On 4/19/25 21:09, Drew Fustini wrote:
> On Wed, Feb 19, 2025 at 03:02:38PM +0100, Michal Wilczynski wrote:
>> T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part
>> of the power-up sequence.
>>
>> Signed-off-by: Michal Wilczynski
>> ---
>> arch/riscv/boot/dts/thead/th1520.
On Tue, 2025-04-22 at 13:13 +0200, Danilo Krummrich wrote:
> On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ursulin wrote:
> > Question I raised is if there are other drivers which manage to
> > clean up
> > everything correctly (like the mock scheduler does), but trigger
> > that
> > warning. Ma
Am Donnerstag, 17. April 2025, 17:19:33 CEST schrieb Frank Li:
> Convert fsl,dcu.txt to yaml format.
>
> Additional changes:
> - remove label in example.
> - change node to display-controller in example.
> - use 32bit address in example.
>
> Signed-off-by: Frank Li
> ---
> .../devicetree/bindin
Hi Andy,
On Tue, 22 Apr 2025 at 12:12, Andy Shevchenko
wrote:
> On Tue, Apr 22, 2025 at 10:07:33AM +0200, Geert Uytterhoeven wrote:
> > On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
>
> ...
>
> > > +Generic FourCC code
> > > +---
> > > +
> > > +::
> > > + %p4c[hnlb]
Hi Pekka,
On Tue, 22 Apr 2025 at 12:01, Pekka Paalanen wrote:
> On Tue, 22 Apr 2025 11:41:29 +0200
> Geert Uytterhoeven wrote:
> > On Tue, 22 Apr 2025 at 11:11, Pekka Paalanen
> > wrote:
> > > On Mon, 21 Apr 2025 17:50:39 +0300
> > > Laurent Pinchart wrote:
> > > > On Thu, Apr 17, 2025 at 11:1
On Tue, Apr 22, 2025 at 10:07:33AM +0200, Geert Uytterhoeven wrote:
> On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
...
> > +Generic FourCC code
> > +---
> > +
> > +::
> > + %p4c[hnlb] gP00 (0x67503030)
> > +
> > +Print a generic FourCC code, as both ASCII characters
On Tue, Apr 22, 2025 at 10:43:59AM +0200, Geert Uytterhoeven wrote:
> On Tue, 22 Apr 2025 at 10:30, Aditya Garg wrote:
> > On 22-04-2025 01:37 pm, Geert Uytterhoeven wrote:
> > > On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
...
> > Originally, it was %p4cr (reverse-endian), but on the reques
There is a spelling mistake with the array utcl2_rounter_str, it
appears it should be utcl2_router_str. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.
On Sun, Apr 20, 2025 at 09:19:38PM +0900, Alexandre Courbot wrote:
> Add the register!() macro, which defines a given register's layout and
> provide bit-field accessors with a way to convert them to a given type.
> This macro will allow us to make clear definitions of the registers and
> manipulat
Hi all,
At 2025-03-21 17:48:04, "Maxime Ripard" wrote:
>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> In some application scenarios, we hope to get the corresponding
>> connector when the bridge's detect hook is invoked.
>>
>> In most cases, we can get the
Apply bridge window offsets to screen_info framebuffers during
relocation. Fixes invalid access to I/O memory.
Resources behind a PCI bridge can be located at a certain offset
in the kernel's I/O range. The framebuffer memory range stored in
screen_info refers to the offset as seen during boot (es
On Mon, Apr 21, 2025 at 10:35:29AM -0600, Jonathan Corbet wrote:
> Dmitry Baryshkov writes:
> > On Wed, Apr 16, 2025 at 03:51:03PM +0800, Mauro Carvalho Chehab wrote:
> >>
> >> As reported by Andy, the Kernel build system runs kernel-doc script for
> >> DRM,
> >> when W=1. Due to Python's normal
On 18/04/2025 20:18, Miguel Ojeda wrote:
On Fri, Apr 18, 2025 at 6:51 PM Jocelyn Falempe wrote:
Link:
https://lore.kernel.org/dri-devel/caniq72ke45eowckmhwhvmwxc03dxr4rnxxkvx+hvwdblopz...@mail.gmail.com/
[1]
Thanks for fixing that -- some tags for your consideration:
Reported-by: Miguel O
Add MDP-RSZ component support for MT8196.
Signed-off-by: Sunny Shen
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
3 files changed, 27 insertions(+)
diff --git a/drivers/
Due to the path mux design of the MT8196, the following components
need to be added to support Picture Quality (PQ) in the main display
path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
Signed-off-by: Sunny Shen
Reviewed-by: CK Hu
---
The method of using OF graph for display pa
Due to the path mux design of the MT8196, the following components need to be
configured to support Picture Quality (PQ) in the display path:CCORR0, CCORR1,
DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
Change in v2:
- Update compatible name of mt8196-mdp-rsz.
- Update clocks and examples in mdp
Add a compatible string for MediaTek MT8196 SoC
Signed-off-by: Sunny Shen
---
.../devicetree/bindings/display/mediatek/mediatek,postmask.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
b/Documentation/devicetre
Due to the path mux design of the MT8196, the following components
need to be configured into mutex and mmsys to support
Picture Quality (PQ) in the display path:CCORR0, CCORR1, DITHER0,
GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
Signed-off-by: Sunny Shen
---
drivers/soc/mediatek/mt8196-mmsys.h| 7
Add MDP-RSZ hardware description for MediaTek MT8196 SoC
Signed-off-by: Sunny Shen
---
.../display/mediatek/mediatek,mdp-rsz.yaml| 45 +++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
diff --gi
Hi Aditya, Hector,
On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
> From: Hector Martin
>
> %p4cc is designed for DRM/V4L2 FourCCs with their specific quirks, but
> it's useful to be able to print generic 4-character codes formatted as
> an integer. Extend it to add format specifiers for printi
On Mon, Apr 21, 2025 at 05:45:33PM -0400, Joel Fernandes wrote:
> On 4/20/2025 8:19 AM, Alexandre Courbot wrote:
> > diff --git a/drivers/gpu/nova-core/devinit.rs
> > b/drivers/gpu/nova-core/devinit.rs
> > new file mode 100644
> > index
> > ..ee5685aff845aa
On Sun, Apr 20, 2025 at 09:19:40PM +0900, Alexandre Courbot wrote:
> Upon reset, the GPU executes the GFW_BOOT firmware in order to
> initialize its base parameters such as clocks. The driver must ensure
> that this step is completed before using the hardware.
>
> Signed-off-by: Alexandre Courbot
On Mon, 10 Mar 2025 18:41:01 +0800, Damon Ding wrote:
> Picked from:
> https://patchwork.kernel.org/project/linux-rockchip/list/?series=936932
>
> These patchs have been tested with a 1536x2048p60 eDP panel on
> RK3588S EVB1 board, and HDMI 1080P/4K display also has been verified
> on RK3588 EVB
On Sun, Apr 20, 2025 at 09:19:41PM +0900, Alexandre Courbot wrote:
> A page of system memory is reserved so sysmembar can perform a read on
> it if a system write occurred since the last flush. Do this early as it
> can be required to e.g. reset the GPU falcons.
>
> Signed-off-by: Alexandre Courbo
Hi Aditya,
CC netdev
On Tue, 22 Apr 2025 at 10:30, Aditya Garg wrote:
> On 22-04-2025 01:37 pm, Geert Uytterhoeven wrote:
> > On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
> >> From: Hector Martin
> >>
> >> %p4cc is designed for DRM/V4L2 FourCCs with their specific quirks, but
> >> it's usef
On Sat, Apr 19, 2025 at 08:21:34PM GMT, Akhil P Oommen wrote:
> Add a new schema which extends opp-v2 to support a new vendor specific
> property required for Adreno GPUs found in Qualcomm's SoCs. The new
> property called "qcom,opp-acd-level" carries a u32 value recommended
> for each opp needs to
On Fri, 18 Apr 2025 21:15:32 +0100
Adrián Larumbe wrote:
> Hi Boris,
>
> On 18.04.2025 10:04, Boris Brezillon wrote:
> > On Fri, 18 Apr 2025 03:27:07 +0100
> > Adrián Larumbe wrote:
> >
> > > +#ifdef CONFIG_DEBUG_FS
> > > +static void
> > > +panthor_gem_debugfs_format_flags(char flags_str[],
On Mon, Apr 21, 2025 at 10:18:23PM GMT, Barnabás Czémán wrote:
> Add device tree bindings for the global clock controller on Qualcomm
> MSM8937 platform.
>
> Signed-off-by: Barnabás Czémán
> ---
> .../devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 11 ---
> include/dt-bindings/clock
Hi Biju,
Thank you for the review.
On Sat, Apr 19, 2025 at 8:28 AM Biju Das wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -Original Message-
> > From: Prabhakar
> > Sent: 18 April 2025 19:47
> > Subject: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for
> > RZ/
On Sun, Apr 20, 2025 at 09:19:32PM +0900, Alexandre Courbot wrote:
> Hi everyone,
>
> This series is a continuation of my previous RFCs [1] to complete the
> first step of GSP booting (running the FWSEC-FRTS firmware extracted
> from the BIOS) on Ampere devices. While it is still far from bringing
Am 17.04.25 um 18:10 schrieb Sunil Khatri:
> drm_file will be used in usermode queues code to
> enable better process information in logging and hence
> add drm_file part of the userq_mgr struct.
>
> update the drm_file pointer in userq_mgr for each
> amdgpu_driver_open_kms.
>
> Signed-off-by: Suni
On Tue, 22 Apr 2025 11:41:29 +0200
Geert Uytterhoeven wrote:
> Hi Pekka,
>
> On Tue, 22 Apr 2025 at 11:11, Pekka Paalanen
> wrote:
> > On Mon, 21 Apr 2025 17:50:39 +0300
> > Laurent Pinchart wrote:
> > > On Thu, Apr 17, 2025 at 11:13:15AM +0300, Pekka Paalanen wrote:
> > > > On Wed, 16 Apr
On 21/04/2025 22:12, Martin Blumenstingl wrote:
This is a successor of a previous patchset by Christian [0]
Patch 1 reverts a previous fix for loss of HDMI sync when playing YUV420
@ 59.94 media. The patch does resolve a calculation issue. It also makes
all fractional rates invalid which is a bi
On 19/04/2025 23:32, Martin Blumenstingl wrote:
Hi Martijn, Hi Neil,
On Thu, Apr 10, 2025 at 8:46 PM wrote:
Hi Martin,
Thank you for the patch.
I encountered this issue some time ago as well and had a possible fix in my
tree (see
below).
My apologies for not upstreaming it earlier.
No wor
From: Andy Yan
HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
is missing when it first landing upstream.
Document that it is mandatory for RK3036 HDMI.
Signed-off-by: Andy Yan
Reviewed-by: Krzysztof Kozlowski
---
(no changes since v2)
Changes in v2:
- First included
From: Andy Yan
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Signed-off-by: Andy Yan
---
Changes in v4:
- Do not store colorimetry within inno_hdmi struct
Changes in v3:
- First included in v3
drivers/gpu/drm/bridge
From: Andy Yan
This reverts commit 1580ccb6ed9dc76b8ff3e2d8912e8215c8b0fa6d.
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed from
the HDMI protocol analyzer that the H/V front/back timing output
by RK3036 HDMI are curre
From: Andy Yan
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed
from the HDMI protocol analyzer that the H/V front/back timing
output by RK3036 HDMI are currently not in line with the specifications.
Signed-off-by: Andy
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be
enabled first before normal DDC communication can be carried out.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm/boot/dts/rockchip/rk3036.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-
From: Andy Yan
When preparing to convert the current inno hdmi driver into a
bridge driver, I found that there are several issues currently
existing with it:
1. When the system starts up, the first time it reads the EDID, it
will fail. This is because RK3036 HDMI DDC bus requires it's PHY's
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be enabled
first before normal DDC communication can be carried out.
Therefore, both RK3036 and RK3128 HDMI require two identical clocks.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(no changes sinc
From: Andy Yan
Use dev_err_probe simplify the error handle.
Signed-off-by: Andy Yan
---
(no changes since v2)
Changes in v2:
- First included in this series
drivers/gpu/drm/rockchip/inno_hdmi.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers
On 22/04/2025 07:06, Philipp Stanner wrote:
On Thu, 2025-04-17 at 17:08 +0100, Tvrtko Ursulin wrote:
On 17/04/2025 15:48, Danilo Krummrich wrote:
On Thu, Apr 17, 2025 at 03:20:44PM +0100, Tvrtko Ursulin wrote:
On 17/04/2025 13:11, Danilo Krummrich wrote:
On Thu, Apr 17, 2025 at 12:27:29PM
Hi Andy,
On Tue, 22 Apr 2025 at 12:16, Andy Shevchenko
wrote:
> On Tue, Apr 22, 2025 at 10:43:59AM +0200, Geert Uytterhoeven wrote:
> > On Tue, 22 Apr 2025 at 10:30, Aditya Garg wrote:
> > > On 22-04-2025 01:37 pm, Geert Uytterhoeven wrote:
> > > > On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote
On 22/04/2025 06:43, Philipp Stanner wrote:
On Fri, 2025-04-18 at 12:32 +0100, Tvrtko Ursulin wrote:
Quick sketch idea for an alternative to
https://lore.kernel.org/dri-devel/20250407152239.34429-2-pha...@kernel.org/
.
It is possible it achieves the same effect but with less code and not
furt
On 22/04/2025 09:04, neil.armstr...@linaro.org wrote:
On 19/04/2025 23:32, Martin Blumenstingl wrote:
Hi Martijn, Hi Neil,
On Thu, Apr 10, 2025 at 8:46 PM wrote:
Hi Martin,
Thank you for the patch.
I encountered this issue some time ago as well and had a possible fix in my
tree (see
below
On Thu, Apr 17, 2025 at 04:22:28PM +0530, Arun R Murthy wrote:
> Unify the function to calculate the link symbol cycles for both dsc and
> non-dsc case and export the function so that it can be used in the
> respective platform display drivers for other calculations.
>
> v2: unify the fn for both
Hi Pekka,
On Tue, 22 Apr 2025 at 11:11, Pekka Paalanen
wrote:
> On Mon, 21 Apr 2025 17:50:39 +0300
> Laurent Pinchart wrote:
> > On Thu, Apr 17, 2025 at 11:13:15AM +0300, Pekka Paalanen wrote:
> > > On Wed, 16 Apr 2025 11:59:43 +0300 Tomi Valkeinen wrote:
> > > > On 01/04/2025 16:27, Pekka Paala
On 22-04-2025 02:13 pm, Geert Uytterhoeven wrote:
> Hi Aditya,
>
> CC netdev
>
> On Tue, 22 Apr 2025 at 10:30, Aditya Garg wrote:
>> On 22-04-2025 01:37 pm, Geert Uytterhoeven wrote:
>>> On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
From: Hector Martin
%p4cc is designed for
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Christian König
Von: Denis Arefev
Gesendet: Freitag, 18. April 2025 10:31
An: Deucher, Alexander
Cc: Koenig, Christian; David Airlie; Simona Vetter; Andrey Grodzovsky; Chunming
Zhou;
On Mon, 21 Apr 2025 17:50:39 +0300
Laurent Pinchart wrote:
> Hi Pekka,
>
> On Thu, Apr 17, 2025 at 11:13:15AM +0300, Pekka Paalanen wrote:
> > On Wed, 16 Apr 2025 11:59:43 +0300 Tomi Valkeinen wrote:
> > > On 01/04/2025 16:27, Pekka Paalanen wrote:
> > > > On Mon, 31 Mar 2025 13:53:37 +0300
On Thu, Apr 17, 2025 at 04:49:07PM +0200, Boris Brezillon wrote:
> Currently, we pick the MMIO offset based on the size of the pgoff_t
> type seen by the process that manipulates the FD, such that a 32-bit
> process can always map the user MMIO ranges. But this approach doesn't
> work well for emul
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Christian König
Von: Tvrtko Ursulin
Gesendet: Freitag, 18. April 2025 18:25
An: dri-devel@lists.freedesktop.org
Cc: kernel-...@igalia.com; Tvrtko Ursulin; Koenig, Christian; Lucas De M
Am 17.04.25 um 20:09 schrieb T.J. Mercier:
> struct dma_heap_attachment is a separate allocation from the struct
> sg_table it contains, but there is no reason for this. Let's use the
> slab allocator just once instead of twice for dma_heap_attachment.
>
> Signed-off-by: T.J. Mercier
I'm not *tha
On 22-04-2025 01:37 pm, Geert Uytterhoeven wrote:
> Hi Aditya, Hector,
>
> On Tue, 8 Apr 2025 at 08:48, Aditya Garg wrote:
>> From: Hector Martin
>>
>> %p4cc is designed for DRM/V4L2 FourCCs with their specific quirks, but
>> it's useful to be able to print generic 4-character codes formatted
On Sun, Apr 20, 2025 at 09:19:42PM +0900, Alexandre Courbot wrote:
> Add a timer that works with GPU time and provides the ability to wait on
> a condition with a specific timeout.
What can this timer do for us, what and HrTimer can't do for us?
>
> The `Duration` Rust type is used to keep track
On 22/04/2025 12:13, Danilo Krummrich wrote:
On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ursulin wrote:
Question I raised is if there are other drivers which manage to clean up
everything correctly (like the mock scheduler does), but trigger that
warning. Maybe there are not and maybe moc
On Tue, 2025-04-22 at 13:07 +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2025 12:13, Danilo Krummrich wrote:
> > On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ursulin wrote:
> > > Question I raised is if there are other drivers which manage to
> > > clean up
> > > everything correctly (like the mo
On Thu, 17 Apr 2025 11:11:33 -0400, Frank Li wrote:
> Convert fsl,tcon.txt to yaml format.
>
> Signed-off-by: Frank Li
> ---
> .../devicetree/bindings/display/fsl,tcon.txt | 17
> .../bindings/display/fsl,vf610-tcon.yaml | 43 +++
> MAINTAINERS
On Tue, Apr 22, 2025 at 08:28:31AM +0300, Kandpal, Suraj wrote:
> [...]
>
> > +void intel_dp_compute_min_hblank(int link_bpp_x16,
> > +struct intel_crtc_state *crtc_state,
> > +struct drm_connector_state *conn_state,
> > +
On Tue, Apr 22, 2025 at 09:22:26AM -0400, Alex Deucher wrote:
> On Mon, Apr 21, 2025 at 5:59 PM Kees Cook wrote:
> >
> > GCC really does not want to consider NULL (or near-NULL) addresses as
> > valid, so calculations based off of NULL end up getting range-tracked into
> > being an offset wthin a
On 16/04/25 09:04, Alex Deucher wrote:
Can you resend, I can't seem to find the original emails.
Additionally, all of the NISLANDS structures are unused in amdgpu, so
those could be removed.
Okay, I'll take a look.
Thanks
-Gustavo
This reverts commit 272e6aab14bbf98d7a06b2b1cd6308a02d4a10a1.
Applying degamma curve to the cursor by default breaks Linux userspace
expectation.
On Linux, AMD display manager enables cursor degamma ROM just for
implict sRGB on HW versions where degamma is split into two blocks:
degamma ROM for p
On Tue, Apr 22, 2025 at 02:39:21PM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2025 13:32, Danilo Krummrich wrote:
> > On Tue, Apr 22, 2025 at 01:07:47PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 22/04/2025 12:13, Danilo Krummrich wrote:
> > > > On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ur
On 22/04/2025 10:20, Koenig, Christian wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Christian König
Thanks!
I could also add:
Fixes: 3f09a0cd4ea3 ("drm: Add common fdinfo helper")
Cc: # v6.5+
With a disclaimer that the problem predates the common helper.
Hi Dave, Sima,
a bit earlier than usual, this is the PR for drm-misc-fixes for
this week.
Best regards
Thomas
drm-misc-fixes-2025-04-22:
Short summary of fixes pull:
meson:
- Fix VCLK calculation
panel:
- jd9365a: Fix reset polarity
The following changes since commit 76c332d119f9048c6e16b52359
Hello dri maintainers/developers,
This is a 31-day syzbot report for the dri subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/dri
During the period, 1 new issues were detected and 0 were fixed.
In total, 18 issues are still open and 32 have alre
Hi Joel, Danilo,
On Tue Apr 22, 2025 at 8:28 PM JST, Danilo Krummrich wrote:
> On Mon, Apr 21, 2025 at 05:45:33PM -0400, Joel Fernandes wrote:
>> On 4/20/2025 8:19 AM, Alexandre Courbot wrote:
>> > diff --git a/drivers/gpu/nova-core/devinit.rs
>> > b/drivers/gpu/nova-core/devinit.rs
>> > new file
On Mon, Apr 21, 2025 at 5:59 PM Kees Cook wrote:
>
> GCC really does not want to consider NULL (or near-NULL) addresses as
> valid, so calculations based off of NULL end up getting range-tracked into
> being an offset wthin a 0 byte array. It gets especially mad about this:
>
> if
On 22/04/2025 13:00, Philipp Stanner wrote:
On Tue, 2025-04-22 at 13:13 +0200, Danilo Krummrich wrote:
On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ursulin wrote:
Question I raised is if there are other drivers which manage to
clean up
everything correctly (like the mock scheduler does),
Hi Danilo,
On Tue Apr 22, 2025 at 5:40 PM JST, Danilo Krummrich wrote:
> On Sun, Apr 20, 2025 at 09:19:32PM +0900, Alexandre Courbot wrote:
>> Hi everyone,
>>
>> This series is a continuation of my previous RFCs [1] to complete the
>> first step of GSP booting (running the FWSEC-FRTS firmware ext
On 22/04/2025 16:53, AngeloGioacchino Del Regno wrote:
Il 21/04/25 21:16, Dmitry Baryshkov ha scritto:
On Tue, Apr 15, 2025 at 12:43:20PM +0200, AngeloGioacchino Del Regno
wrote:
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
found in MediaTek's MT8195, MT8188 SoC and their varia
On Tue, 2025-04-22 at 16:08 +0200, Danilo Krummrich wrote:
> On Tue, Apr 22, 2025 at 02:39:21PM +0100, Tvrtko Ursulin wrote:
> >
> > On 22/04/2025 13:32, Danilo Krummrich wrote:
> > > On Tue, Apr 22, 2025 at 01:07:47PM +0100, Tvrtko Ursulin wrote:
> > > >
> > > > On 22/04/2025 12:13, Danilo Krumm
On Tue, Apr 22, 2025 at 01:07:47PM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2025 12:13, Danilo Krummrich wrote:
> > On Tue, Apr 22, 2025 at 11:39:11AM +0100, Tvrtko Ursulin wrote:
> > > Question I raised is if there are other drivers which manage to clean up
> > > everything correctly (like the m
On Tue, 01 Apr 2025 08:11:32 +0300, Dmitry Baryshkov wrote:
> While it makes sense for panel callbacks to be able to return an error,
> the state-management functions from drm_panel API are usually called
> from atomic callbacks, which can not fails and must return void. Make
> drm_panel_prepare(),
On Tue, Apr 22, 2025 at 04:16:48PM +0200, Philipp Stanner wrote:
> On Tue, 2025-04-22 at 16:08 +0200, Danilo Krummrich wrote:
> > On Tue, Apr 22, 2025 at 02:39:21PM +0100, Tvrtko Ursulin wrote:
>
> > > Sorry I don't see the argument for the claim it is relying on the
> > > internals
> > > with the
On 22-04-2025 22:34, Matthew Brost wrote:
Mixing GPU and CPU atomics does not work unless a strict migration
policy of GPU atomics must be device memory. Enforce a policy of must be
in VRAM with a retry loop of 2 attempts, if retry loop fails abort
fault.
retry loop of 3 attempts not 2. with
On 09/04/2025 13:22, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> When CONFIG_DEBUG_FS is disabled, the stid_fmts[] array is not referenced
> anywhere, causing a W=1 warning with gcc:
>
> In file included from drivers/gpu/drm/imagination/pvr_fw_trace.c:7:
> drivers/gpu/drm/imagination/pvr_rogu
From: Asahi Lina
Add a GPUVM abstraction to be used by Rust GPU drivers.
GPUVM keeps track of a GPU's virtual address (VA) space and manages the
corresponding virtual mappings represented by "GPU VA" objects. It also
keeps track of the mapping's backing GEM buffers.
This initial version only su
The CMA heap's name in devtmpfs can vary depending on how the heap is
defined. Its name defaults to "reserved", but if a CMA area is defined
in the devicetree, the heap takes on the devicetree node's name, such as
"default-pool" or "linux,cma". To simplify naming, just name it
"default_cma", and ke
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