Add MAINTAINERS entry for the Sitronix ST7571 dot matrix LCD
controller.
Signed-off-by: Marcus Folkesson
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
889bd4a59551c9bc125f94944a6e1c7e3ef2de83..00d19d45679f6d18a7e9c9e619b7642176b7ef95
Sitronix ST7571 is a 4bit gray scale dot matrix LCD controller.
The controller has a SPI, I2C and 8bit parallel interface, this is for
the I2C interface only.
Signed-off-by: Marcus Folkesson
---
.../bindings/display/sitronix,st7571-i2c.yaml | 71 ++
1 file changed, 71 in
On Tue, Apr 01, 2025 at 10:53:46AM -0700, Guenter Roeck wrote:
> > > @@ -92,7 +102,8 @@ do {
> > > \
> > > do {\
> > > __auto_type __flags = BUGFLAG_WARNING|(flags);
On Tue, Apr 01, 2025 at 10:53:46AM -0700, Guenter Roeck wrote:
> > > #define _BUG_FLAGS(ins, flags, extra)
> > > \
> > > do {
> > > \
> > > asm_inline volatile("1:\t" ins "\n"
Hi,
thanks for the driver. See below for an initial review.
Am 02.04.25 um 08:12 schrieb Marcus Folkesson:
Sitronix ST7571 is a 4bit gray scale dot matrix LCD controller.
The controller has a SPI, I2C and 8bit parallel interface, this
driver is for the I2C interface only.
Signed-off-by: Marcus
As rk3399 has its own registers definitions, update related structs to
use them.
There are no changes in behaviour as updated constants values are the
same for rk3288/rk3368/rk3399 chips.
Signed-off-by: Konstantin Shabanov
---
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 94 ++--
The writepage callback is going away; filesystems must implement
migrate_folio or else dirty folios will not be migratable.
Signed-off-by: Matthew Wilcox (Oracle)
---
mm/migrate.c | 60 ++--
1 file changed, 7 insertions(+), 53 deletions(-)
diff --
If we add a migrate_folio operation, we can convert the writepage
operation to writepages. Further, this lets us optimise by using
the same write handle for multiple folios. The large folio support here
is illusory; we would need to kmap each page in turn for proper support.
But we do remove a fe
On 4/1/25 15:26, Jonathan Cavitt wrote:
Add initial declarations for the drm_xe_vm_get_property ioctl.
v2:
- Expand kernel docs for drm_xe_vm_get_property (Jianxun)
v3:
- Remove address type external definitions (Jianxun)
- Add fault type to xe_drm_fault struct (Jianxun)
v4:
- Remove engine
On Sun, Mar 23, 2025 at 12:25:58AM +0300, Dmitry Osipenko wrote:
Hi,
This a continuation of a year-old series that adds generic DRM-shmem
shrinker [1]. The old series became too big with too many patches, more
reasonable to split it up into multiple smaller patchsets. Here is
the firtst part tha
When the GPU is the only device attached to a single power domain,
core genpd disable and enable it when gpu enter and leave runtime suspend.
Some power-domain requires a sequence before disabled,
and the reverse when enabled.
Add GPU_PM_RT flag, and implement in
panfrost_device_runtime_suspend/r
According to Mali manuals, the powerup sequence should be
enable pd, asserting the reset then enabling the clock and
the reverse for powerdown.
Signed-off-by: Philippe Simons
---
drivers/gpu/drm/panfrost/panfrost_device.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletion
Tie the Allwinner compatible string to the GPU_PM_RT feature bits that will
toggle the clocks and the reset line whenever the power domain is changing
state.
Signed-off-by: Philippe Simons
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 8
1 file changed, 8 insertions(+)
diff --git a/dri
Allwinner H616 has a dedicated power domain for its Mali G31.
Currently after probe, the GPU is put in runtime suspend which
disable the power domain.
On first usage of GPU, the power domain enable hangs the system.
This series adds the necessary calls to enable the clocks and
deasserting the re
Hi Daniel,
On 28/03/25 17:29, Vignesh Raman wrote:
Hi Daniel,
On 28/03/25 17:06, Daniel Stone wrote:
Hi Vignesh,
On Fri, 28 Mar 2025 at 11:03, Vignesh Raman
wrote:
The current s3cp implementation does not work anymore after the
migration, and instead of fixing it and propagating the fix do
From: Andy Yan
The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX
controller. And this DPTX controller need share a USBDP PHY with
the USB 3.0 OTG controller during operation.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(no changes since v2)
Changes in v2:
- Link
On Tue, Apr 01, 2025 at 10:26:54PM +, Jonathan Cavitt wrote:
> +/** struct xe_vm_fault - Describes faults for %DRM_XE_VM_GET_PROPERTY_FAULTS
> */
> +struct xe_vm_fault {
> + /** @address: Address of the fault */
> + __u64 address;
> + /** @address_precision: Precision of faulted ad
Hi Dmitry:
Really sorry for missed this comment. Yes it can be done in UMD,
actually the interval tree is used with the MMU notifier normally,
it is for preventing create same MMU notifier for overlapped areas.
Cause this version patch set doesn't have MMU notifier, removing
interval tree is
From: Andy Yan
The DW DP TX Controller is compliant with the DisplayPort Specification
Version 1.4 with the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
* Single Stream Transport(SST)
* Multistream
From: Andy Yan
Add driver extension for Synopsys DesignWare DPTX IP used
on Rockchip RK3588 SoC.
Signed-off-by: Andy Yan
Acked-by: Dmitry Baryshkov
---
(no changes since v2)
Changes in v2:
- no include uapi path
- switch to drmm_encoder_init
drivers/gpu/drm/rockchip/Kconfig|
From: Andy Yan
The DP1 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY1 with USB 3.1
HOST1 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
.../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++
1 file changed, 30 inser
From: Andy Yan
RA620 is a DP to HDMI bridge converter from RADXA, which first
found be used on ROCK 5 ITX.
This chip can be used without involving software.
Signed-off-by: Andy Yan
---
Changes in v3:
- First introduced in this version.
.../devicetree/bindings/display/bridge/simple-bridge.y
From: Andy Yan
Enable the Mini DisplayPort on this board.
Note that ROCKCHIP_VOP2_EP_DP0 is defined as 10 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address error,
expected "a"" if we use it directly after endpoint, so we use "a"
instead here.
Signed-off-by: A
Matthew Wilcox (Oracle) wrote on Wed, Apr 02, 2025 at 03:59:55PM +0100:
> The migration code used to be able to migrate dirty 9p folios by writing
> them back using writepage. When the writepage method was removed,
> we neglected to add a migrate_folio method, which means that dirty 9p
> folios ha
On 4/2/25 18:19, Jianxun Zhang wrote:
On 4/1/25 15:26, Jonathan Cavitt wrote:
Add initial declarations for the drm_xe_vm_get_property ioctl.
v2:
- Expand kernel docs for drm_xe_vm_get_property (Jianxun)
v3:
- Remove address type external definitions (Jianxun)
- Add fault type to xe_drm_fa
From: Andy Yan
HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
is missing when it first landing upstream.
Document that it is mandatory for RK3036 HDMI.
Signed-off-by: Andy Yan
---
(no changes since v2)
Changes in v2:
- First included in v2
.../bindings/display/rock
On Tue, 01 Apr 2025, Jason Gunthorpe wrote:
> On Tue, Apr 01, 2025 at 10:42:35PM +0300, Jani Nikula wrote:
>> On Tue, 01 Apr 2025, Jason Gunthorpe wrote:
>> > So, I'd suggest a better way to run this is first build the kernel,
>> > then mine the gcc -MD output (ie stored in the .XX.cmd files) to
On Wed, 2 Apr 2025 12:54:29 +0100
Adrián Larumbe wrote:
> Add a device DebugFS file that displays a complete list of all the DRM
> GEM objects that are exposed to UM through a DRM handle.
>
> Since leaking object identifiers that might belong to a different NS is
> inadmissible, this functional
Introduces the new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
Both sharpness and panel fitter uses pipe scaler,
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler is available and make sure that only
either of panel fitter or sharpness is enabled at
a time.
v2: Add the panel fitting check befo
On Wed, Apr 02, 2025 at 03:56:37PM +0300, Jani Nikula wrote:
> On Tue, 01 Apr 2025, Jason Gunthorpe wrote:
> > On Tue, Apr 01, 2025 at 10:42:35PM +0300, Jani Nikula wrote:
> >> On Tue, 01 Apr 2025, Jason Gunthorpe wrote:
> >> > So, I'd suggest a better way to run this is first build the kernel,
>
On Wed, 2 Apr 2025 12:54:28 +0100
Adrián Larumbe wrote:
> Kernel BO's aren't exposed to UM, so labelling them is the responsibility
> of the driver itself. This kind of tagging will prove useful in further
> commits when want to expose these objects through DebugFS.
>
> Expand panthor_kernel_bo
Set the configuration for CASF and capture it
in crtc_state and get the configuration by
reading back. Add the support to compare the
software and hardware state of CASF.
v2: Update subject[Ankit]
v3: Add the state compare[Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel
Add HAS_CASF macro to check whether platform supports
the content adaptive sharpness capability or not.
v2: Update commit message[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 7 +++
drivers/gpu/drm/i915/display/int
At the moment the driver just sets the clock rate with clk_set_rate(),
and if the resulting rate is not the same as requested, prints a debug
print, but nothing else.
Add functionality to atomic_check(), in which the clk_round_rate() is
used to get the "rounded" rate, and set that to the adjusted_
Clean up the function a bit, mainly by doing the mode_valid_check dance
once in the beginning of the function, and grouping the calculations
wrt. sync/event mode a bit better.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 48 --
1 file
The timings calculation gets it wrong for DSI event mode, resulting in
too large hbp value. Fix the issue by taking into account the
pulse/event mode difference.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 33 ++
1 file changed, 23 i
While trying to get the cdns-dsi to work on Toradex's AM69 Aquila
platform, I hit multiple issues in the driver. Basicaly nothing worked
for with the board.
This series fixes those issues. While I itch to make much larger changes
to the cdns-dsi driver, I opted to keep this series relatively simpl
Use the crtc_* fields from drm_display_mode, instead of the "logical"
fields. This shouldn't change anything in practice, but afaiu the crtc_*
fields are the correct ones to use here.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/tidss/tidss_crtc.c | 2 +-
drivers/gpu/drm/tidss/tidss_dispc
The driver check if "DPI(HFP) > DSI(HSS+HSA+HSE+HBP)", and rejects the
mode if not.
However, testing shows that this doesn't hold at all. I can set the hfp
to very small values, with no errors. The feedback from the HW team also
was that the check is not right, although it's not clear if there's a
The docs say about mode_valid():
"it is not allowed to look at anything else but the passed-in mode, and
validate it against configuration-invariant hardware constraints"
We're doing a lot more than just looking at the mode. The main issue
here is that we're doing checks based on the pixel clock,
The driver uses crtc_* fields from the mode. While I think in the
enable-path this would be correct, I do not think it's correct in the
check phase, as the crtc hasn't had a chance to update the crtc_* fields
yet.
Overall, my understanding is that the crtc_* fields are relevant only in
cases where
cdns_dsi_mode2cfg() calculates the dsi timings, but for some reason
doesn't set the htotal based on those timings. It is set only later, in
cdns_dsi_adjust_phy_config().
As cdns_dsi_mode2cfg() is the logical place to calculate it, let's move
it there. Especially as the following patch will remove
The driver currently expects the pixel clock and the HS clock to be
compatible, but the DPHY PLL doesn't give very finely grained rates.
This often leads to the situation where the pipeline just fails, as the
resulting HS clock is just too off.
We could change the driver to do a better job on adju
The phy_validate() can change the HS clock rate we passed to it in the
PHY config, depending on what the HW can actually do. The driver just
ignores this at the moment, but if the actual HS clock rate is different
than the requested one, the pipeline will fail as all the DSI timing
calculations wil
Am 02.04.25 um 15:22 schrieb Michel Dänzer:
> On 2025-04-02 14:00, Philipp Stanner wrote:
>> On Wed, 2025-04-02 at 12:58 +0200, Michel Dänzer wrote:
>>> On 2025-04-02 12:46, Philipp Stanner wrote:
On Mon, 2025-03-31 at 21:16 +0100, Tvrtko Ursulin wrote:
> Round-robin being the non-default
There are multiple places where conversions between IOV resources and
corresponding VF BAR numbers are done.
Extract the logic to pci_resource_num_from_vf_bar() and
pci_resource_num_to_vf_bar() helpers.
Suggested-by: Ilpo Järvinen
Signed-off-by: Michał Winiarski
Acked-by: Christian König
---
Drivers could leverage the fact that the VF BAR MMIO reservation is
created for total number of VFs supported by the device by resizing the
BAR to larger size when smaller number of VFs is enabled.
Add a pci_iov_vf_bar_set_size() function to control the size and a
pci_iov_vf_bar_get_sizes() helper
From: Andrey Vatoropin
Static analysis shows that pointer "svms" cannot be NULL because it points
to the object "struct svm_range_list". Remove the extra NULL check. It is
meaningless and harms the readability of the code.
In the function svm_range_get_info() there is no possibility of failure.
Similar to regular resizable BAR, VF BAR can also be resized, e.g. by
the system firmware or the PCI subsystem itself.
The capability layout is the same as PCI_EXT_CAP_ID_REBAR.
Add the capability ID and restore it as a part of IOV state.
See PCIe r6.2, sec 7.8.7.
Signed-off-by: Michał Winiarsk
On Wed, Apr 02, 2025 at 10:58:32AM +0100, Christopher Obbard wrote:
> The eDP controller has an HPD GPIO. Describe it in the device tree
> for the generic T14s model, as the HPD GPIO is used in both the
> OLED and LCD models which inherit this device tree.
>
> Signed-off-by: Christopher Obbard
>
From: Andrey Vatoropin
Static analysis shows that pointer "timing" cannot be NULL because it
points to the object "struct dc_crtc_timing".
Remove the extra NULL check. It is meaningless and harms the readability
of the code.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Sig
Hi Dmitry,
On Wed, 2025-04-02 at 16:36 +0300, Dmitry Baryshkov wrote:
> > >
> > > It works if I call
> > > drm_mode_set_crtcinfo((struct drm_display_mode *)mode, 0) before
> > > create_validate_stream_for_sink()
> > > in amdgpu_dm_connector_mode_valid()
> > >
> > > or
> > >
> > > if I comment o
(Dmitry).
- Link to v4:
https://lore.kernel.org/r/20250402-wip-obbardc-qcom-t14s-oled-panel-v4-0-41ba3f373...@linaro.org
Changes in v4:
- Rework HPD GPIO into eDP device rather than panel (Johan).
- Drop review tags for HPD GPIO patch.
- Link to v3:
https://lore.kernel.org/r/20250327-wip-obbardc
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
b/drivers/gpu/drm/p
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
b/dr
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-novatek-nt36672e.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
b/drivers/gpu/d
HuC delayed loading fence, introduced with commit 27536e03271da
("drm/i915/huc: track delayed HuC load with a fence"), is registered with
object tracker early on driver probe but unregistered only from driver
remove, which is not called on early probe errors. Since its memory is
allocated under de
On Wed, Apr 02, 2025 at 03:36:33PM +0100, Christopher Obbard wrote:
> The eDP controller has an HPD GPIO. Describe it in the device tree
> for the generic T14s model, as the HPD GPIO is used in both the
> OLED and LCD models which inherit this device tree.
>
> Signed-off-by: Christopher Obbard
>
On Wed, Apr 02, 2025 at 03:36:34PM +0100, Christopher Obbard wrote:
> Add the Samsung ATNA40YK20 eDP panel to the device tree for the
> Snapdragon T14s OLED model.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Christopher Obbard
> ---
> arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14
Gentle ping..
At 2025-03-14 15:57:47, "Andy Yan" wrote:
>From: Andy Yan
>
>It is not recommended for drivers to include UAPI header
>directly.
>
>Signed-off-by: Andy Yan
>---
>
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff
From: Andy Yan
The RA620 is an active DP to HDMI converter chip, basically
no software is involved to drive it.
Add it to simple bridge to make it can be find by the drm bridge chain.
Signed-off-by: Andy Yan
---
Changes in v3:
- First introduced in this version.
drivers/gpu/drm/bridge/simp
On Tue, 18 Mar 2025 14:53:13 +, Brendan King wrote:
> For paired jobs, have the fragment job take a reference on the
> geometry job, so that the geometry job cannot be freed until
> the fragment job has finished with it.
>
> The geometry job structure is accessed when the fragment job is bei
On Thu, Apr 03, 2025 at 12:46:17PM +0900, Dominique Martinet wrote:
> Matthew Wilcox (Oracle) wrote on Wed, Apr 02, 2025 at 03:59:55PM +0100:
> > The migration code used to be able to migrate dirty 9p folios by writing
> > them back using writepage. When the writepage method was removed,
> > we ne
On Wed, Apr 02, 2025 at 08:31:36PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
> is missing when it first landing upstream.
>
> Document that it is mandatory for RK3036 HDMI.
>
> Signed-off-by: Andy Yan
>
> ---
>
> (no ch
On Fri, Mar 28, 2025 at 06:39:29PM +0200, Ilpo Järvinen wrote:
> On Wed, 26 Mar 2025, Ilpo Järvinen wrote:
>
> > On Thu, 20 Mar 2025, Michał Winiarski wrote:
> >
> > > When the resource representing VF MMIO BAR reservation is created, its
> > > size is always large enough to accommodate the BAR o
On Wed, Mar 26, 2025 at 05:22:50PM +0200, Ilpo Järvinen wrote:
> On Thu, 20 Mar 2025, Michał Winiarski wrote:
>
> > Drivers could leverage the fact that the VF BAR MMIO reservation is
> > created for total number of VFs supported by the device by resizing the
> > BAR to larger size when smaller nu
On Wed, Mar 26, 2025 at 05:29:31PM +0200, Ilpo Järvinen wrote:
> On Thu, 20 Mar 2025, Michał Winiarski wrote:
>
> > LMEM is partitioned between multiple VFs and we expect that the more
> > VFs we have, the less LMEM is assigned to each VF.
> > This means that we can achieve full LMEM BAR access wi
Build fails with:
error: multiple unsequenced modifications to 'sbuf32'
[-Werror,-Wunsequenced]
264 | le32_to_cpup(sbuf32++),
|^
265 | le32_to_cpup(sbuf32++),
|
Hi,
While playing with
https://lore.kernel.org/all/61c3df83ab73aba0bc7a941a443cd7faf4cf7fb0.1743195250.git.so...@irl.hu/
I found a regression that prevented some EDID DTDs from being selected
in some specific cases.
This is the first bad commit:
b255ce4 ("drm/amdgpu: don't change mode in
amdgpu_
Il 02/04/25 11:38, Chen-Yu Tsai ha scritto:
On Wed, Apr 2, 2025 at 4:36 PM AngeloGioacchino Del Regno
wrote:
The OVL driver is installing an ISR in the probe function but, if
the component is not bound yet, the interrupt handler may call the
vblank_cb ahead of time (while probing other drivers
On Wed, 2 Apr 2025 11:20:17 +0100
Steven Price wrote:
> On 01/04/2025 19:23, Boris Brezillon wrote:
> > MMU handler needs to be in control of the job interrupt clears because
> > clearing the interrupt also unblocks the writer/reader that triggered
> > the fault, and we don't want it to be unbloc
Add a device DebugFS file that displays a complete list of all the DRM
GEM objects that are exposed to UM through a DRM handle.
Since leaking object identifiers that might belong to a different NS is
inadmissible, this functionality is only made available in debug builds
with DEBUGFS support enabl
On Wed, 2 Apr 2025, Michał Winiarski wrote:
> On Wed, Mar 26, 2025 at 05:22:50PM +0200, Ilpo Järvinen wrote:
> > On Thu, 20 Mar 2025, Michał Winiarski wrote:
> >
> > > Drivers could leverage the fact that the VF BAR MMIO reservation is
> > > created for total number of VFs supported by the device
Hi Boris,
On 28.03.2025 15:30, Boris Brezillon wrote:
> On Thu, 27 Mar 2025 14:08:36 +
> Adrián Larumbe wrote:
>
> > Add a device DebugFS file that displays a complete list of all the DRM GEM
> > objects that are exposed to UM through a DRM handle.
> >
> > Since leaking object identifiers tha
On Wed, 2 Apr 2025 at 15:00, Gergo Koteles wrote:
>
> to: Dmitry's new address
> cc: regressions
>
> On Wed, 2025-04-02 at 12:40 +0200, Gergo Koteles wrote:
> > Hi,
> >
> > While playing with
> > https://lore.kernel.org/all/61c3df83ab73aba0bc7a941a443cd7faf4cf7fb0.1743195250.git.so...@irl.hu/
> >
On 26/03/2025 17:51, Andy Shevchenko wrote:
> On Wed, Mar 26, 2025 at 11:55:33AM +0200, Jani Nikula wrote:
>> On Wed, 26 Mar 2025, Andy Shevchenko
>> wrote:
>>> +Cc: Jani (sorry, forgot to add you in the first place).
>>>
>>> Do you think it's applicable now?
>> Cc: Yaron, Koby, and Konstantin
Add drm_panic module supports for hyperv drm so that panic screen can be
displayed on panic.
Signed-off-by: Ryosuke Yasuoka
---
drivers/gpu/drm/drm_simple_kms_helper.c | 26 +
drivers/gpu/drm/hyperv/hyperv_drm_modeset.c | 42 +
include/drm/drm_simple_kms_helpe
This will be the replacement for shmem_writepage().
Signed-off-by: Matthew Wilcox (Oracle)
---
include/linux/shmem_fs.h | 7 ---
mm/shmem.c | 20 ++--
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/include/linux/shmem_fs.h b/include/linux/shmem
Convert from an inefficient loop to the standard writeback iterator.
Signed-off-by: Matthew Wilcox (Oracle)
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 32 ++-
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/driv
All callers and implementations are now removed, so remove the operation
and update the documentation to match.
Signed-off-by: Matthew Wilcox (Oracle)
---
Documentation/admin-guide/cgroup-v2.rst | 2 +-
Documentation/filesystems/fscrypt.rst | 2 +-
Documentation/filesystems/locking.rst | 5
The migration code used to be able to migrate dirty 9p folios by writing
them back using writepage. When the writepage method was removed,
we neglected to add a migrate_folio method, which means that dirty 9p
folios have been unmovable ever since. This reduced our success at
defragmenting memory
Hi Dmitry,
On Wed, 2025-04-02 at 17:40 +0300, Dmitry Baryshkov wrote:
> On Wed, 2 Apr 2025 at 17:35, Gergo Koteles wrote:
> >
> > Hi Dmitry,
> >
> > On Wed, 2025-04-02 at 16:36 +0300, Dmitry Baryshkov wrote:
> > > > >
> > > > > It works if I call
> > > > > drm_mode_set_crtcinfo((struct drm_dis
From: Andrey Vatoropin
Static analysis shows that pointer "table" cannot be NULL because it
points to the object "struct amdgpu_cac_leakage_table".
Remove the extra NULL check. It is meaningless and harms the readability
of the code.
Found by Linux Verification Center (linuxtesting.org) with S
Add new drm_dyndbg_user.c with a single call to
DYNDBG_CLASSMAP_USE(drm_debug_classes). This creates a _class_user
record (and a linkage dependency).
If a driver adds this object to its Makefile target, it gets the
record, which authorizes dyndbg to enable the module's class'd
pr_debugs, such as
The drm_gem_shmem_helper driver has a number of DRM_UT_* debugs, make
them controllable when CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling
dyndbg that the module uses them.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/driver
Treat comma as a token terminator, just like a space. This allows a
user to avoid quoting hassles when spaces are otherwise needed:
:#> modprobe drm dyndbg=class,DRM_UT_CORE,+p\;class,DRM_UT_KMS,+p
or as a boot arg:
drm.dyndbg=class,DRM_UT_CORE,+p # todo: support multi-query here
Given the
The vmwgfx driver has a number of DRM_UT_* debugs, make them
controllable when CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling dyndbg
that the module uses them.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/vmwgf
The gud driver has a number of DRM_UT_* debugs, make them
controllable when CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling dyndbg
that the module uses them.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/gud/gud_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/gud/gud_drv.c
Following the dyndbg-api-fix, replace DECLARE_DYNDBG_CLASSMAP with
DRM_CLASSMAP_USE. This refs the defined & exported classmap, rather
than re-declaring it redundantly, and error-prone-ly.
This resolves the appearance of "class:_UNKNOWN_" in the control file
for the driver's drm_dbg()s.
Fixes: f
The mgag200 driver has a number of DRM_UT_* debugs, make them
controllable when CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling dyndbg
that the module uses them.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/mgag200/mgag200_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mg
Following the dyndbg-api-fix, replace DECLARE_DYNDBG_CLASSMAP with
DRM_CLASSMAP_USE. This refs the defined & exported classmap, rather
than re-declaring it redundantly, and error-prone-ly.
This resolves the appearance of "class:_UNKNOWN_" in the control file
for the driver's drm_dbg()s.
Fixes: f
etnaviv has 5 DRM_UT_CORE debugs, make them controllable when
CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling dyndbg that the module has
class'd debugs as well as plain-old pr_debug()s
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --g
The udl driver has a number of DRM_UT_* debugs, make them
controllable when CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling dyndbg
that the module uses them.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/udl/udl_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/udl/udl_main.
Add VIRTGPU_PARAM_HOST_PAGE_SIZE as a param that can be read with
VIRTGPU_GETPARAM by userspace applications running in the guest to
obtain the host's page size and find out the right alignment to be used
in shared memory allocations.
Signed-off-by: Sergio Lopez
---
drivers/gpu/drm/virtio/virtgp
6 files changed, 24 insertions(+), 3 deletions(-)
---
base-commit: acc4d5ff0b61eb1715c498b6536c38c1feb7f3c1
change-id: 20250402-virtio-gpu-host-page-size-282c99dfe44c
Best regards,
--
Sergio Lopez
When writing queries to >control, flags are parsed 1st, since they are
the only required field, and they require specific compositions. So
if the flags draw an error (on those specifics), then keyword errors
aren't reported. This can be mildly confusing/annoying, so explain it
instead.
cc: linux
ARRAY_SIZE works here, since array decl is complete.
no functional change
Signed-off-by: Jim Cromie
Reviewed-by: Louis Chauvet
---
include/linux/dynamic_debug.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
Refactor callchain below param_set_dyndbg_classes(1) to allow mod-name
specific settings. Split (1) into upper/lower fns, adding modname
param to lower, and passing NULL in from upper. Below that, add the
same param to ddebug_apply_class_bitmap(), and pass it thru to
_ddebug_queries(), replacing
Classmaps are stored in an elf section/array, but currently are
individually list-linked onto dyndbg's per-module ddebug_table for
operation. This is unnecessary.
Just like dyndbg's descriptors, classes are packed in compile order;
so even with many builtin modules employing multiple classmaps, ea
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