Hello,
syzbot has tested the proposed patch and the reproducer did not trigger any
issue:
Reported-by: syzbot+a504cb5bae4fe117b...@syzkaller.appspotmail.com
Tested-by: syzbot+a504cb5bae4fe117b...@syzkaller.appspotmail.com
Tested on:
commit: d1302efc selftests/udmabuf: add a test to pin
On Fri, Jan 31, 2025 at 06:28:57PM +, Lorenzo Stoakes wrote:
> in the fb_defio video driver, page dirty state is used to determine when
> frame buffer pages have been changed, allowing for batched, deferred I/O to
> be performed for efficiency.
>
> This implementation had only one means of doi
Fix incorrect format of compatible string (comma instead of hyphen) for
TI's AM62A7 SoC.
s/ti,am62a7,dss/ti,am62a7-dss
Fixes: 7959ceb767e4 ("dt-bindings: display: ti: Add support for am62a7 dss")
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Devarsh Thakkar
---
V2: Add Reviewed-by and update
On Mon, Feb 03, 2025 at 03:58:22PM +0100, Herve Codina wrote:
> The current code uses a the reset_pipe() local function to reset the
> CRTC outputs.
>
> drm_atomic_helper_reset_crtc() has been introduced recently and it
> performs exact same operations.
>
> In order to avoid code duplication, use
Hi all,
Oops, this series doesn't apply on top of v6.14-rc1. My bad, sorry about
that.
Please ignore this series. I will send soon a new iteration fixed.
Apologies,
Hervé
On Mon, 3 Feb 2025 15:58:19 +0100
Herve Codina wrote:
> Hi,
>
> Usually the TI SN65DSI83 recovers from error by itself b
On Mon, Feb 03, 2025 at 03:58:21PM +0100, Herve Codina wrote:
> drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
>
> This resets all active components available between the CRTC and
> connectors.
>
> Signed-off-by: Herve Codina
> ---
> drivers/gpu/drm/drm_atomic_helper.c
On Sun, Feb 02, 2025 at 01:02:47PM +0900, Inki Dae wrote:
> 2025년 2월 1일 (토) 오전 1:56, Bjorn Helgaas 님이 작성:
> >
> > I don't know this code at all, so this is likely just noise, but the
> > wait_event_timeout() usage in decon_wait_for_vblank() looks funny to
> > me.
> >
> > decon_wait_for_vblank() wai
Hi Dmitry,
On Mon, 3 Feb 2025 17:56:33 +0200
Dmitry Baryshkov wrote:
> On Mon, Feb 03, 2025 at 03:58:21PM +0100, Herve Codina wrote:
> > drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
> >
> > This resets all active components available between the CRTC and
> > connector
Hi Rob
On 30/01/2025 23:20, Rob Herring wrote:
>
> Why would panthor need CMA, it has an MMU.
>
> In any case, I agree with Maxime that this is redundant.
>
This is correct, the GPU has an MMU. The reason I introduced this custom
CMA DTB entry is to allow creation of a standalone DMA heap whic
Hi Dmitry,
On Mon, 3 Feb 2025 17:56:46 +0200
Dmitry Baryshkov wrote:
> On Mon, Feb 03, 2025 at 03:58:22PM +0100, Herve Codina wrote:
> > The current code uses a the reset_pipe() local function to reset the
> > CRTC outputs.
> >
> > drm_atomic_helper_reset_crtc() has been introduced recently and
On Mon, Feb 03, 2025 at 04:49:34PM +0100, Simona Vetter wrote:
> On Fri, Jan 31, 2025 at 06:28:57PM +, Lorenzo Stoakes wrote:
> > in the fb_defio video driver, page dirty state is used to determine when
> > frame buffer pages have been changed, allowing for batched, deferred I/O to
> > be perfo
Enable display for AM62L DSS [1] which supports only a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and
the DPI signals from the video
The DSS controller on TI's AM62L SoC is an update from that on TI's
AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is route
This adds support for DSS subsystem present in TI's AM62L SoC
which supports single display pipeline with DPI output which
is also routed to DSI Tx controller within the SoC.
Change Log:
V2:
- Fix incorrect format of compatible string (comma instead of
hyphen) for AM62L SoC
- Use separate regist
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
The mode_set callback is deprecated, it doesn't get the
drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
that HDMI timings should be programmed after setting up HDMI PHY and
PLL. Rework the code to program HDMI timings at the
On 2/1/25 09:18, Soci/Singular wrote:
I was wondering why there's garbage at the bottom of the screen when
tile blitting is used with an odd mode like 1080, 600 or 200. Sure there's
only space for half a tile but the same area is clean when the buffer
is bitmap.
Then later I found that it's supp
Applied. Thanks!
Alex
On Sun, Feb 2, 2025 at 5:08 PM wrote:
>
> From: "Dr. David Alan Gilbert"
>
> Another small pile of deadcode patches.
>
> Signed-off-by: Dr. David Alan Gilbert
>
>
> Dr. David Alan Gilbert (7):
> drm/amd/display: Remove unused mpc1_is_mpcc_idle
> drm/amd/display: Remo
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
Setup the HDMI connector on the MSM HDMI outputs. Make use of
atomic_check hook and of the provided Infoframe infrastructure.
By atomic_check are you referring to the
msm_hdmi_bridge_tmds_char_rate_valid()?
Also please confirm if HDMI audio w
On 2/3/2025 2:57 AM, Abel Vesa wrote:
Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
1.4a specification. As the name suggests, these PHY repeaters are
capable of adjusting their output for link training purposes.
According to the DisplayPort standard, LTTPRs have two
On 2/2/25 21:33, Kajtár Zsolt wrote:
The erase colour calculation for fbcon clearing should use get_color instead
of attr_col_ec, like everything else. The latter is similar but is not correct.
For example it's missing the depth dependent remapping and doesn't care about
blanking.
The problem ca
CC'ed: driv-devel
On 2/2/25 13:39, Kajtár Zsolt wrote:
A series on de-duplicating the common cfb and sys drawing routines will
follow.
Some background:
It happens that I need to use both cfb and sys drawing routines.
For which driver do you need this?
At low resolution where the aperture i
On Sun, Feb 02, 2025 at 06:28:08AM -0800, Guenter Roeck wrote:
> On 2/2/25 05:27, David Laight wrote:
> > On Tue, 21 Jan 2025 15:15:09 -0800
> > Linus Torvalds wrote:
> >
> > > On Tue, 21 Jan 2025 at 14:59, Rodrigo Vivi wrote:
> > > >
> > > > I'm pushing this soon to drm-intel-next, unless Linu
On Mon, Feb 03, 2025 at 04:25:59PM -0800, Abhinav Kumar wrote:
>
>
> On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
> > Setup the HDMI connector on the MSM HDMI outputs. Make use of
> > atomic_check hook and of the provided Infoframe infrastructure.
> >
>
> By atomic_check are you referring to t
On 2025-02-03 8:29 a.m., Andi Shyti wrote:
Hi,
Please, next time, do not remove the mailing and the other folks
you cc'ed.
I'm adding back the mailing list and Daniele who has commented
before.
Thanks, I also found my previous response click on "reply", not the
"reply all".
...
Clos
On Mon, Feb 03, 2025 at 09:19:59AM +0100, Greg Kroah-Hartman wrote:
> On Sun, Feb 02, 2025 at 12:54:07PM -0800, Linus Torvalds wrote:
> > Greg, Luis, can you explain that odd uevent message / netlink issue?
>
> There was reports from Android devices that the uevent was causing the
> system to wake
On Mon, Feb 3, 2025 at 4:00 PM John Hubbard wrote:
[..]
>
> >> +()
> >> +)]
> >> +);
> >> +
> >> +impl pci::Driver for NovaCore {
> >> +type IdInfo = ();
> >> +const ID_TABLE: pci::IdTable = &PCI_TABLE;
> >> +
> >> +fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) ->
Hi Danilo,
On Fri, Jan 31, 2025 at 11:04:24PM +0100, Danilo Krummrich wrote:
> Add the initial nova-core driver stub.
>
> nova-core is intended to serve as a common base for nova-drm (the
> corresponding DRM driver) and the vGPU manager VFIO driver, serving as a
> hard- and firmware abstraction l
On Mon, Feb 3, 2025 at 11:17 AM Biju Das wrote:
>
> Hi Rob,
>
> +Cc relevant subsystems.
>
> > -Original Message-
> > From: Rob Herring
> > Sent: 03 February 2025 16:53
> > Subject: Re: [PATCH v2] of: base: Add of_get_available_child_by_name()
> >
> > On Sat, Feb 1, 2025 at 3:31 AM Biju D
Hi
>
>-Original Message-
>From: Dmitry Baryshkov
>Sent: Tuesday, February 4, 2025 1:28 AM
>To: Hermes Wu (吳佳宏)
>Cc: Andrzej Hajda ; Neil Armstrong
>; Robert Foss ; Laurent Pinchart
>; Jonas Karlman ; Jernej
>Skrabec ; Maarten Lankhorst
>; Maxime Ripard ;
>Thomas Zimmermann ; David A
On Mon, 3 Feb 2025 10:39:58 +0200 "Kirill A. Shutemov"
wrote:
> > diff --git a/mm/filemap.c b/mm/filemap.c
> > index 4fe551037bf7..98493443d120 100644
> > --- a/mm/filemap.c
> > +++ b/mm/filemap.c
> > @@ -1605,8 +1605,9 @@ static void folio_end_reclaim_write(struct folio
> > *folio)
> >
On Mon, Feb 03, 2025 at 04:23:56PM -0300, raf...@beims.me wrote:
> From: Rafael Beims
>
> Add support for HDMI codec with audio coming from the I2S input.
> Support 48kHz and 96kHz sample rate, with 16 bits word size.
>
> Co-developed-by: João Paulo Gonçalves
> Signed-off-by: João Paulo Gonçalv
On Mon, Feb 03, 2025 at 09:14:26PM +0300, Danila Tikhonov wrote:
> From: Eugene Lepshy
>
> DRM DSC helper has parameters for various bpc values other than 8:
> (8/10/12/14/16).
>
> Remove this guard.
>
> Signed-off-by: Eugene Lepshy
> Signed-off-by: Danila Tikhonov
> ---
> drivers/gpu/drm/
On Mon, Feb 03, 2025 at 11:34:00AM -0800, Abhinav Kumar wrote:
>
>
> On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
> > The mode_set callback is deprecated, it doesn't get the
> > drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
> > that HDMI timings should be programmed aft
Just found my previous response click on "reply", not the "reply all",
so add Cc list.
Regards,
Zhanjun Dong
Forwarded Message
Subject: Re: [PATCH v1] drm/i915/guc: Always disable interrupt ahead of
synchronize_irq
Date: Mon, 27 Jan 2025 17:17:33 -0500
From: Dong, Zhanjun
Applied. Thanks!
Alex
On Fri, Jan 31, 2025 at 5:38 PM Nathan Chancellor wrote:
>
> Currently, there are several files in drm/amd/display that aim to have a
> higher -Wframe-larger-than value to avoid instances of that warning with
> a lower value from the user's configuration. However, with the
On 2/3/25 12:24 PM, Joel Fernandes wrote:
Hi Danilo,
On Fri, Jan 31, 2025 at 11:04:24PM +0100, Danilo Krummrich wrote:
...
+const BAR0_SIZE: usize = 8;
+pub(crate) type Bar0 = pci::Bar;
+
+kernel::pci_device_table!(
+PCI_TABLE,
+MODULE_PCI_TABLE,
+::IdInfo,
+[(
+pci::Dev
On Tue, Jan 21, 2025 at 09:42:17AM -0500, Rodrigo Vivi wrote:
> On Sat, Jan 18, 2025 at 06:47:27PM +0100, Michal Wajdeczko wrote:
> >
> >
> > On 17.01.2025 22:57, Vinay Belgaumkar wrote:
> > > Default SLPC power profile is Base(0). Power Saving mode(1)
> > > has conservative up/down thresholds an
On Mon, 03 Feb 2025 21:14:24 +0300, Danila Tikhonov wrote:
> The Visionox RM692E5 is a 6.55” AMOLED panel used in Nothing Phone (1)
> (sm7325-nothing-spacewar).
>
> Signed-off-by: Danila Tikhonov
> ---
> .../display/panel/visionox,rm692e5.yaml | 77 +++
> 1 file changed,
On Mon, 03 Feb 2025 16:23:55 -0300, raf...@beims.me wrote:
> From: Rafael Beims
>
> Add the I2S audio input port for audio over HDMI support.
>
> Signed-off-by: Rafael Beims
> ---
> .../bindings/display/bridge/lontium,lt8912b.yaml | 8
> 1 file changed, 8 insertions(+)
>
From: Thomas Tai Sent: Thursday, January 30, 2025 12:44
PM
>
> > -Original Message-
> > From: Michael Kelley
> > Sent: Thursday, January 30, 2025 3:20 PM
> > To: Thomas Tai ; mhkelle...@gmail.com;
> > haiya...@microsoft.com; wei@kernel.org; de...@microsoft.com;
> > drawat.fl...@gmai
-t830"
# "arm,mali-t880"
reg:
---
base-commit: df4b2bbff898227db0c14264ac7edd634e79f755
change-id: 20250203-exynos7870-gpu-ccb918e23b2e
Best regards,
--
Kaustabh Chakraborty
On Sun, Feb 02, 2025 at 10:14:31PM +, Colin Ian King wrote:
> There is a spelling mistake in an error message. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu
The current code can issue CDMA flushes (DMAPUT bumps) in the middle
of a job, before all opcodes have been written into the pushbuffer.
This can happen when pushbuffer fills up. Presumably this made sense
at some point in the past, but it doesn't anymore, as it cannot lead
to more space appearing
Applied to drm-misc-next
On 1/29/2025 1:56 PM, Jacek Lawrynowicz wrote:
> Most notable is the addition of hardware fault injection support which allows
> to test error handling paths in the driver.
>
> Jacek Lawrynowicz (2):
> accel/ivpu: Add support for hardware fault injection
> accel/ivpu:
Hi Dmitry,
On Thu, Jan 16, 2025 at 03:08:00AM +0200, Dmitry Baryshkov wrote:
> On Wed, Jan 15, 2025 at 10:05:36PM +0100, Maxime Ripard wrote:
> > The TI sn65dsi86 driver follows the drm_encoder->crtc pointer that is
> > deprecated and shouldn't be used by atomic drivers.
> >
> > This was due to t
Hi
Am 14.01.25 um 00:15 schrieb Lorenzo Stoakes:
[...]
*** REVIEWERS NOTES: ***
I do not have any hardware that uses fb_defio, so I'm asking for help with
testing this series from those who do :) I have tested the mm side of this,
and done a quick compile smoke test of the fb_defio side but t
Hi Detlev,
On 1/31/25 6:18 PM, Detlev Casanova wrote:
Hi Quentin,
On Friday, 31 January 2025 11:38:34 EST Quentin Schulz wrote:
Hi Detlev,
On 1/30/25 5:45 PM, Detlev Casanova wrote:
[...]
The only hesitation I have is that HDMI0 can use either I2S or SPDIF for
audio, both audio controllers
Hi,
On Tue, Dec 10, 2024 at 12:10:19AM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
> DSI2 host controller, based on the Rockchip version from the driver
> rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bri
Am 01.02.25 um 05:39 schrieb Armin Wolf:
Am 21.01.25 um 23:31 schrieb Werner Sembach:
Hi,
after some other work, picked this up again.
Only coding style changes vs v4.
I now got my feet a little wet with hid-bpf regarding something else, and
with that knowledge I would leave the long arrays
On Mon, Feb 03, 2025 at 11:24:50AM +0100, Thomas Zimmermann wrote:
> Hi
>
>
> Am 14.01.25 um 00:15 schrieb Lorenzo Stoakes:
> [...]
> >
> > *** REVIEWERS NOTES: ***
> >
> > I do not have any hardware that uses fb_defio, so I'm asking for help with
> > testing this series from those who do :) I have
Looking at both i915 and nouveau DP drivers, both are setting the first
LTTPR (if found) in transparent mode first and then in non-transparent
mode, just like the DP v2.0 specification mentions in section 3.6.6.1.
Being part of the standard, setting the LTTPR in a specific operation mode
can be ea
According to the DisplayPort standard, LTTPRs have two operating
modes:
- non-transparent - it replies to DPCD LTTPR field specific AUX
requests, while passes through all other AUX requests
- transparent - it passes through all AUX requests.
Switching between this two modes is done by the DPT
LTTPRs operating modes are defined by the DisplayPort standard and the
generic framework now provides a helper to switch between them, which
is handling the explicit disabling of non-transparent mode and its
disable->enable sequence mentioned in the DP Standard v2.0 section
3.6.6.1.
So use the new
Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
1.4a specification. As the name suggests, these PHY repeaters are
capable of adjusting their output for link training purposes.
According to the DisplayPort standard, LTTPRs have two operating
modes:
- non-transparent - it re
Hi Biju,
Thanks for your patch!
On Sat, 1 Feb 2025 at 11:57, Biju Das wrote:
> Simplify tegra_dc_rgb_probe() by using of_get_available_child_by_name().
That's not the only thing this patch does...
>
> Signed-off-by: Biju Das
> --- a/drivers/gpu/drm/tegra/rgb.c
> +++ b/drivers/gpu/drm/tegra/r
On Sun, Feb 02, 2025 at 12:54:07PM -0800, Linus Torvalds wrote:
> On Sun, 2 Feb 2025 at 12:15, Dave Airlie wrote:
> >
> > Currently FW_CACHE is an optional feature (that distros may or may not
> > configure off), where we will cache loaded firmwares to avoid problems
> > over suspend/resume (and s
On Sat, Feb 01, 2025 at 07:18:56PM +0200, Dmitry Baryshkov wrote:
> On Wed, Jan 29, 2025 at 05:07:52PM +0200, Andy Shevchenko wrote:
> > On Tue, Jan 28, 2025 at 06:43:26PM +0200, Andy Shevchenko wrote:
> > > On Tue, Jan 28, 2025 at 05:08:08PM +0100, Marek Szyprowski wrote:
> > > > On 21.01.2025 14:
+Akash with whom we've been discussing adding a 'REPEAT' mode to
drm_gpuvm/panthor.
On Sun, 2 Feb 2025 19:53:47 +0100
Danilo Krummrich wrote:
> Hi Lina,
>
> On Sun, Feb 02, 2025 at 10:34:49PM +0900, Asahi Lina wrote:
> > Some hardware requires dummy page mappings to efficiently implement
> > Vu
On Mon, Feb 03, 2025 at 12:57:55PM +0200, Abel Vesa wrote:
> Looking at both i915 and nouveau DP drivers, both are setting the first
> LTTPR (if found) in transparent mode first and then in non-transparent
> mode, just like the DP v2.0 specification mentions in section 3.6.6.1.
>
> Being part of t
On Sun, Feb 02, 2025 at 07:40:35PM +0900, Vincent Mailhol wrote:
Hi Lucas and Yury,
On 08/02/2024 at 16:45, Lucas De Marchi wrote:
ove the implementation of REG_GENMASK/REG_BIT to a more appropriate
place to be shared by i915, xe and possibly other parts of the kernel.
For now this re-defines
On Mon, Feb 03, 2025 at 12:19:04PM +0100, Krzysztof Kozlowski wrote:
> On 31/01/2025 17:25, Dmitry Baryshkov wrote:
> >>
> >> -static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
> >> +static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
> >> +
There has repeatedly been quite a bit of apprehension when any change to the DRM
scheduler is proposed, with two main reasons being code base is considered
fragile, not well understood and not very well documented, and secondly the lack
of systematic testing outside the vendor specific tests suites
Implement a mock scheduler backend and add some basic test to exercise the
core scheduler code paths.
Mock backend (kind of like a very simple mock GPU) can either process jobs
by tests manually advancing the "timeline" job at a time, or alternatively
jobs can be configured with a time duration in
Add a basic test for exercising modifying the entities scheduler list at
runtime.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../scheduler/tests/drm_sched_tests_basic.c | 66 ++-
1 file changed, 65 insert
Add a very simple TDR test which submits a single job and verifies that
the TDR handling will run if the backend failed to complete the job in
time.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../drm/scheduler/tests/drm_mo
Move some options out into a new debug specific kconfig file in order to
make things a bit cleaner.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/Kconfig | 98 ++-
drivers/gpu/drm/Kconfig.debug | 92
2 files changed, 97 i
Add a basic test for exercising modifying the entities scheduler list at
runtime.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../scheduler/tests/drm_sched_tests_basic.c | 66 ++-
1 file changed, 65 insert
Add some basic tests for exercising entity priority handling.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../scheduler/tests/drm_sched_tests_basic.c | 95 ++-
1 file changed, 94 insertions(+), 1 deletion(
Hi Krzysztof
On 30/01/2025 13:25, Krzysztof Kozlowski wrote:
> On 30/01/2025 14:08, Florent Tomasin wrote:
>> Allow mali-valhall-csf driver to retrieve a protected
>> heap at probe time by passing the name of the heap
>> as attribute to the device tree GPU node.
>
> Please wrap commit message acc
From: Brendan King
Ensure job done fences are only initialised once.
This fixes a memory manager not clean warning from drm_mm_takedown
on module unload.
Signed-off-by: Brendan King
---
drivers/gpu/drm/imagination/pvr_queue.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --
struct pvr_gem_object *pvr_obj, u64 pvr_obj_offset,
u64 device_addr, u64 size);
+int pvr_vm_unmap_obj(struct pvr_vm_context *vm_ctx,
+struct pvr_gem_object *pvr_obj,
+u64 device_addr, u64 size);
int pvr_vm_unmap(struct pvr_vm_context *vm_ctx, u64 device_
release work structure. */
+ struct work_struct release_work;
};
/**
---
base-commit: 3ab334814dc7dff39075e055e12847d51878916e
change-id: 20250203-fence-release-deadlock-a0753c07bfdd
Best regards,
--
Brendan King
On 03/02/2025 15:03, Devarsh Thakkar wrote:
> Fix compatible string for AM62A7 DSS.
Fix incorrect format of compatible string (comma instead of hyphen) for
> s/ti,am62a7,dss/ti,am62a7-dss
>
> Fixes: 7959ceb767e4 ("dt-bindings: display: ti: Add support for am62a7 dss")
> Signed-off-by: Devars
This patch series adds support for the Visionox RM692E5 panel, which is
used on the Nothing Phone (1) and then adds it to the DTS.
But before adding to DTS we need to allow all bpc values in DSC code,
because Visionox RM692E5 has a bpc value of 10. Also we need to make sure
that the DSC patch fo
From: Eugene Lepshy
Add the driver for Visionox RM692E5 panel support found in Nothing
Phone (1).
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile
The Visionox RM692E5 is a 6.55” AMOLED panel used in Nothing Phone (1)
(sm7325-nothing-spacewar).
Signed-off-by: Danila Tikhonov
---
.../display/panel/visionox,rm692e5.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/dis
From: Eugene Lepshy
Enable the Adreno GPU and configure the Visionox RM692E5 panel.
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
---
Note:
Depends on
https://lore.kernel.org/linux-arm-msm/20250122-dpu-111-topology-v2-1-505e95964...@somainline.o
From: Eugene Lepshy
DRM DSC helper has parameters for various bpc values other than 8:
(8/10/12/14/16).
Remove this guard.
Signed-off-by: Eugene Lepshy
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --
>
> syzbot has found a reproducer for the following issue on:
>
> HEAD commit:69e858e0b8b2 Merge tag 'uml-for-linus-6.14-rc1' of git://g..
> git tree: upstream
> console+strace: https://syzkaller.appspot.com/x/log.txt?x=1431cb2458
> kernel config: https://syzkaller.appspot.com/x/.c
On 31/01/2025 17:24, Dmitry Baryshkov wrote:
> On Fri, Jan 31, 2025 at 04:02:49PM +0100, Krzysztof Kozlowski wrote:
>> Calling these improvements, not fixes, because I don't think we ever hit
>> actual concurrency issue. Although if we ever hit it, it would be very
>> tricky to debug and find the
LTTPRs operating modes are defined by the DisplayPort standard and the
generic framework now provides a helper to switch between them, which
is handling the explicit disabling of non-transparent mode and its
disable->enable sequence mentioned in the DP Standard v2.0 section
3.6.6.1.
So use the new
On 31/01/2025 17:25, Dmitry Baryshkov wrote:
>>
>> -static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
>> +u32 val)
>> {
>> +unsigned long flags;
>> u32 data;
On Mon, Feb 03, 2025 at 10:21:53AM +0100, Boris Brezillon wrote:
> +Akash with whom we've been discussing adding a 'REPEAT' mode to
> drm_gpuvm/panthor.
>
> On Sun, 2 Feb 2025 19:53:47 +0100
> Danilo Krummrich wrote:
>
> > Hi Lina,
> >
> > On Sun, Feb 02, 2025 at 10:34:49PM +0900, Asahi Lina wr
Add MAINTAINERS entries for the driver.
Reviewed-by: Daniel Thompson (RISCstar)
Signed-off-by: Nick Chan
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 896a307fa065..a576324807f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2228,6 +2228,7
On Thu, 30 Jan 2025, Haoyu Li wrote:
> In the function "wled_probe", the "wled->name" is dynamically allocated
> (wled_probe -> wled_configure -> devm_kasprintf), which is possible
> to be null.
>
> In the call trace: wled_probe -> devm_backlight_device_register
> -> backlight_device_register, thi
On Mon, Feb 03, 2025 at 02:04:30PM +0800, Hermes Wu via B4 Relay wrote:
> From: Hermes Wu
>
> For supporting audio form I2S to DP audio data sub stream.
> Add hdmi_audio callbacks to drm_bridge_funcs for the
> HDMI codec framework. The DRM_BRIDGE_OP_HDMI flag in bridge.ops
> must be set, and hdmi
Changes in v2:
- Add Fixes tag
- New patch #4
- Link to v1:
https://lore.kernel.org/r/20250131-drm-msm-phy-pll-cfg-reg-v1-0-3b99efeb2...@linaro.org
Calling these improvements, not fixes, because I don't think we ever hit
actual concurrency issue. Although if we ever hit it, it would be very
tric
PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux
clock from Common Clock Framework:
devm_clk_hw_register_mux_parent_hws(). There could be a path leading to
concurrent and conflicting updates between PHY driver and clock
framework, e.g. changing the mux and enabling PLL clocks.
On Mon, Feb 03, 2025 at 05:16:05PM +0100, Herve Codina wrote:
> The current code uses a the reset_pipe() local function to reset the
> CRTC outputs.
>
> drm_atomic_helper_reset_crtc() has been introduced recently and it
> performs exact same operations.
>
> In order to avoid code duplication, use
PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
clock divider, source of bitclk and two for enabling the DSI PHY PLL
clocks.
dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
all other bits untouched. Use newly introduced
dsi_pll_cmn_clk_cfg1_update() t
PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two
divider clocks from Common Clock Framework:
devm_clk_hw_register_divider_parent_hw(). Concurrent access by the
clocks side is protected with spinlock, however driver's side in
restoring state is not. Restoring state is called from
Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
avoid hard-coding bit masks and shifts and make the code a bit more
readable. While touching the lines in dsi_7nm_pll_save_state()
resulting cached->pix_clk_div assignment would be too big, so just
combine pix_clk_div and bit_clk
On Mon, Feb 03, 2025 at 05:16:04PM +0100, Herve Codina wrote:
> drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
>
> This resets all active components available between the CRTC and
> connectors.
>
> Signed-off-by: Herve Codina
> ---
> drivers/gpu/drm/drm_atomic_helper.c
On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux
> clock from Common Clock Framework:
> devm_clk_hw_register_mux_parent_hws(). There could be a path leading to
> concurrent and conflicting updates between PHY
On Mon, Feb 03, 2025 at 06:29:20PM +0100, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
> clock divider, source of bitclk and two for enabling the DSI PHY PLL
> clocks.
>
> dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
On Mon, Feb 03, 2025 at 06:29:18PM +0100, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two
> divider clocks from Common Clock Framework:
> devm_clk_hw_register_divider_parent_hw(). Concurrent access by the
> clocks side is protected with spinlock, howe
On Mon, Feb 03, 2025 at 11:01:28AM +0100, Maxime Ripard wrote:
> Hi Dmitry,
>
> On Thu, Jan 16, 2025 at 03:08:00AM +0200, Dmitry Baryshkov wrote:
> > On Wed, Jan 15, 2025 at 10:05:36PM +0100, Maxime Ripard wrote:
> > > The TI sn65dsi86 driver follows the drm_encoder->crtc pointer that is
> > > dep
Hi,
Usually the TI SN65DSI83 recovers from error by itself but during ESD
tests, we have some cases where the TI SN65DSI83 didn't recover.
In order to handle those cases, this series adds support for a recovery
mechanism.
Compare to the previous iteration, this v4 series:
- rebase on top of v6
drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
This resets all active components available between the CRTC and
connectors.
Signed-off-by: Herve Codina
---
drivers/gpu/drm/drm_atomic_helper.c | 41 +
include/drm/drm_atomic_helper.h | 2 +
The current code uses a the reset_pipe() local function to reset the
CRTC outputs.
drm_atomic_helper_reset_crtc() has been introduced recently and it
performs exact same operations.
In order to avoid code duplication, use the new helper instead of the
local function.
Signed-off-by: Herve Codina
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