The HDMI Connectors need to perform a variety of tasks when the HDMI
connector state changes. Such tasks include setting or invalidating CEC
address, notifying HDMI codec driver, updating scrambler data, etc.
Implementing such tasks in a driver-specific callbacks is error prone.
Start implementing
Extend drm_bridge_connector code to read the EDID and use it to update
connector status if the bridge chain implements HDMI bridge. Performing
it from the generic location minimizes individual bridge's code and
enforces standard behaviour from all corresponding drivers.
Signed-off-by: Dmitry Barys
Drop driver-specific implementation and use the generic HDMI Codec
framework in order to implement the HDMI audio support.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 69 ++
drivers/gpu/drm/vc4/vc4_hdmi.h | 2 --
2 files changed,
The no_capture_mute flag might differ from platform to platform,
especially in the case of the wrapping implementations, like the
upcoming DRM HDMI Codec framework. Move the flag next to all other flags
in struct hdmi_codec_pdata.
Acked-by: Mark Brown
Signed-off-by: Dmitry Baryshkov
---
drivers
Add necessary glue code to be able to use new HDMI codec framework from
the DRM bridge drivers. The drm_bridge implements a limited set of the
hdmi_codec_ops interface, with the functions accepting both
drm_connector and drm_bridge instead of just a generic void pointer.
This framework is integrat
Make the Lontium LT9611 DSI-to-HDMI bridge driver use the DRM HDMI Codec
framework. This enables programming of Audio InfoFrames using the HDMI
Connector interface and also enables support for the missing features,
including the ELD retrieval and better hotplug support.
Signed-off-by: Dmitry Barys
The upcoming DRM connector HDMI codec implementation is going to use
codec-specific data in the .get_dai_id to get drm_connector. Pass data
to the callback, as it is done with other hdmi_codec_ops callbacks.
Acked-by: Mark Brown
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/adv7511
Several DRM drivers implement HDMI codec support (despite its name it
applies to both HDMI and DisplayPort drivers). Implement generic
framework to be used by these drivers. This removes a requirement to
implement get_eld() callback and provides default implementation for
codec's plug handling.
Th
While porting lt9611 DSI-to-HDMI bridge driver to use HDMI Connector
framework, I stumbled upon an issue while handling the Audio InfoFrames.
The HDMI codec callbacks weren't receiving the drm_atomic_state, so
there was no simple way to get the drm_connector that stayed at the end
of the bridge cha
Use the helper function to update the connector's information. This
makes sure that HDMI-related events are handled in a generic way.
Currently it is limited to the HDMI state reporting to the sound system.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++--
1 file c
The vc4_hdmi_connector_detect_ctx() via vc4_hdmi_handle_hotplug()
already reads EDID and propagates it to the drm_connector. Stop
rereading EDID as a part of the .get_modes() callback and just update
the list of modes. This matches the behaviour of the i915 driver.
Signed-off-by: Dmitry Baryshkov
On Thu, Dec 05, 2024 at 08:32:02PM -0800, Abhinav Kumar wrote:
> Add a new file dp_mst_drm to manage the DP MST bridge operations
> similar to the dp_drm file which manages the SST bridge operations.
> Each MST encoder creates one bridge and each bridge is bound to its
> own dp_panel abstraction to
> On Thu, Dec 05, 2024 at 04:29:55PM +, Murthy, Arun R wrote:
> > > > > -Original Message-
> > > > > From: Dmitry Baryshkov
> > > > > Sent: Wednesday, December 4, 2024 5:17 PM
> > > > > To: Murthy, Arun R
> > > > > Cc: intel...@lists.freedesktop.org;
> > > > > intel-...@lists.freedesk
Hi Dmitry,
On Wed, Nov 20, 2024 at 09:39:27AM +0100, Johan Hovold wrote:
> On Fri, Aug 02, 2024 at 10:47:33PM +0300, Dmitry Baryshkov wrote:
> > During suspend/resume process all connectors are explicitly disabled and
> > then reenabled. However resume fails because of the connector_status check:
Hi Guoqing,
At 2024-12-06 19:42:33, "Guoqing Jiang" wrote:
>It is not needed since drm_atomic_helper_shutdown checks it.
>
>Signed-off-by: Guoqing Jiang
Acked-by: Andy Yan
Thanks
>---
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
>
On Thu, Dec 05, 2024 at 08:31:44PM -0800, Abhinav Kumar wrote:
> dp_display_prepare() only prepares the link in case its not
> already ready before dp_display_enable(). Hence separate it into
> its own API.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 24 +++
On 6.12.2024 5:32 AM, Abhinav Kumar wrote:
> From: Yongxing Mou
>
> Populate the pixel clock for stream 1 for DP0 for sa8775p DP controller.
>
> Signed-off-by: Yongxing Mou
> Signed-off-by: Abhinav Kumar
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12
> 1 file changed, 8 inse
On 11/29/2024 10:33 PM, Dmitry Baryshkov wrote:
> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote:
>>
>> Extended DP support for QCS615 USB or DP phy. Differentiated between
>> USBC and DP PHY using the match table’s type, dynamically generating
>> different types of cfg and layout attributes d
On 12/2/2024 6:46 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 02, 2024 at 04:40:05PM +0800, Xiangxu Yin wrote:
>>
>>
>> On 11/29/2024 9:50 PM, Dmitry Baryshkov wrote:
>>> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote:
Add the ability to configure lane mapping for the DP controller. Th
On Thu. 5 Dec 2024 at 03:30, David Laight wrote:
> From: Vincent Mailhol
> > Sent: 02 December 2024 17:33
> >
> > From: Vincent Mailhol
> >
> > For completion, add statically_false() which is the equivalent of
> > statically_true() except that it will return true only if the input is
> > known to
On Thu. 5 Dec 2024 at 04:00, David Laight wrote:
> From: Vincent Mailhol
> > Sent: 02 December 2024 17:34
> >
> > Most of the use of __is_const_expr() in i915_reg_defs.h are just to
> > test whether an expression is known to be true. Because those checks
> > are all done in a BUILD_BUG_ON_ZERO(),
Am Freitag, dem 06.12.2024 um 02:25 + schrieb David Laight:
> From: Vincent Mailhol
> > Sent: 05 December 2024 15:31
> >
> > -CC: Martin Uecker
> > +CC: Martin Uecker
> > (seems that Martin changed his address)
My current one is this: uec...@tugraz.at
Martin
> >
> > On Thu. 5 Dec. 2024 a
On Thu. 5 Dec. 2024 at 08:58, Kees Cook wrote:
> On December 3, 2024 3:33:22 AM GMT+10:00, Vincent Mailhol via B4 Relay
> wrote:
> >This series is the spiritual successor of [1] which introduced
> >const_true(). In [1], following a comment from David Laight, Linus
> >came with a suggestion to si
Hello Heiko,
On 03.12.24 21:54, Heiko Stuebner wrote:
> This series adds a bridge and glue driver for the DSI2 controller found
> in the rk3588 soc from Rockchip, that is based on a Synopsis IP block.
>
> As the manual states:
> The Display Serial Interface 2 (DSI-2) is part of a group of communic
Hi Lucas,
I am grateful to you for your answer as this is my first attempt to contribute
to the kernel.
> -Message d'origine-
> De : Lucas Stach
> Envoyé : mardi 3 décembre 2024 18:58
> À : LECOINTRE Philippe ; Russell King
> ; Christian Gmeiner
>
> Cc : David Airlie ; Simona Vetter ;
From: Alex Hung
[ Upstream commit 8b0ddf19cca2a352b2a7e01d99d3ba949a99c84c ]
BIOS images may fail to load and null checks are added before they are
used.
This fixes 6 NULL_RETURNS issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
Signe
On Thu, Dec 05, 2024 at 08:32:12PM -0800, Abhinav Kumar wrote:
> Use msm_dp_get_mst_intf_id() to get the intf id for the DP MST
> controller as the intf_id is unique for each MST stream of each
> DP controller.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
From: Tomi Valkeinen
Add support for r8a779h0. It is very similar to r8a779g0, but has only
one output.
Signed-off-by: Tomi Valkeinen
Tested-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 18 ++
drivers/gpu/drm/renes
From: Tomi Valkeinen
Add support for DSI on r8a779h0. As it is identical to DSI on r8a779g0,
all we need is to handle the compatible string.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Tested-by: Geert Uytterhoeven
---
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 2 ++
1
From: Tomi Valkeinen
Extend the Renesas DU display bindings to support the r8a779h0 V4M.
Note that we remove the requirement for two ports from the global part
of the bindings, as each conditional part defines the number of required
ports already. This came up with r8a779h0 as it's the first one
On Thu, Dec 05, 2024 at 08:32:00PM -0800, Abhinav Kumar wrote:
> For MST cases, EDID is handled through AUX sideband messaging.
> Skip the EDID read during hotplug handle for MST cases.
But why? Isn't EDID being read at the hotplug time to update
drm_connector's data?
>
> Signed-off-by: Abhinav
From: Tomi Valkeinen
Extend the Renesas DSI display bindings to support the r8a779h0 V4M.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Acked-by: Krzysztof Kozlowski
Tested-by: Geert Uytterhoeven
---
.../devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml | 1
Add everything needed to support the DSI output on Renesas r8a779h0
(V4M) SoC, and the DP output (via sn65dsi86 DSI to DP bridge) on the
Renesas grey-hawk board.
Overall the DSI and the board design is almost identical to Renesas
r8a779g0 and white-hawk board.
Signed-off-by: Tomi Valkeinen
---
C
From: Tomi Valkeinen
Add support for the mini DP output on the Gray Hawk board.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Tested-by: Geert Uytterhoeven
---
.../boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 95 ++
1 file changed, 95 insertions(+)
diff
From: Tomi Valkeinen
Fix the indent on the two regulators.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Tested-by: Geert Uytterhoeven
---
.../boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 24 +++---
1 file changed, 12 insertions(+), 12 deletions(-)
diff --g
From: Tomi Valkeinen
Add the device nodes for supporting DU and DSI.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Tested-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 73 +++
1 file changed, 73 insertions(+)
diff --git a/ar
From: Tomi Valkeinen
Add display related clocks for DU, DSI, FCPVD, and VSPD.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Tested-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a779h0-cpg-mssr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/renesas/r8a7
On 2024/11/30 2:53, Dmitry Baryshkov wrote:
On Fri, Nov 29, 2024 at 06:15:56PM +0800, Yongxing Mou wrote:
On 2024/11/27 21:43, Dmitry Baryshkov wrote:
On Wed, Nov 27, 2024 at 04:15:51PM +0800, Yongxing Mou wrote:
The Qualcomm QCS8300 platform comes with a DisplayPort controller
with same
From: David Laight
> Sent: 06 December 2024 02:26
(now it is no longer 2am...)
Linus suggested this a while back:
> in
> https://lore.kernel.org/all/CAHk-=wiq=gunwjwwh1craychw73umoaskacovlatfdkevez...@mail.gmail.com/
>
>/*
> * iff 'x' is a non-zero constant integer expression,
> *
On Thu, Dec 05, 2024 at 08:32:08PM -0800, Abhinav Kumar wrote:
> Hook up the mst framework APIs with atomic_commit_setup() and
> atomic_commit_tail() APIs to handle non-blocking commits.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/msm_atomic.c | 2 ++
> drivers/gpu/drm/msm/msm_d
On Thu. 5 Dec. 2024 at 03:58, David Laight wrote:
> From: Vincent Mailhol
> > Sent: 02 December 2024 17:33
> >
> > From: Vincent Mailhol
> >
> > is_const() is a one to one replacement of __is_constexpr(). Do the
> > replacement so that __is_constexpr() can be removed.
> >
> > Signed-off-by: Vince
On Thu, Dec 05, 2024 at 08:31:47PM -0800, Abhinav Kumar wrote:
> p1 register block is needed for the second mst stream.
> Add support in the catalog to be able to program this block.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 29 +
>
On 2024/12/6 15:21, Uwe Kleine-König wrote:
> Hello,
>
> On Thu, Dec 05, 2024 at 08:10:13AM +0800, Zijun Hu wrote:
>> From: Zijun Hu
>>
>> Constify the following API:
>> struct device *device_find_child(struct device *dev, void *data,
>> int (*match)(struct device *dev, void *data));
On Thu, Dec 05, 2024 at 08:31:40PM -0800, Abhinav Kumar wrote:
> Currently, the dp_ctrl stream APIs operate on their own dp_panel
> which is cached inside the dp_ctrl's private struct. However with MST,
> the cached panel represents the fixed link and not the sinks which
> are hotplugged. Allow the
On Thu, Dec 05, 2024 at 08:31:41PM -0800, Abhinav Kumar wrote:
> Enable/Disable of DP pixel clock happens in multiple code paths
> leading to code duplication. Move it into individual helpers so that
> the helpers can be called wherever necessary.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers
On Thu, Dec 05, 2024 at 08:31:42PM -0800, Abhinav Kumar wrote:
> Split dp_ctrl_off() into stream and link parts so that for MST
> cases we can control the link and pixel parts separately.
Please start by describing the problem.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/dp/dp
On Thu, Dec 05, 2024 at 08:31:38PM -0800, Abhinav Kumar wrote:
> dp_display_enable() currently re-trains the link if needed
> and then enables the pixel clock, programs the controller to
> start sending the pixel stream. Break up these two parts into
> separate APIs to distinguish these two parts b
Am Donnerstag, dem 05.12.2024 um 22:14 -0800 schrieb Linus Torvalds:
> On Thu, 5 Dec 2024 at 18:26, David Laight wrote:
> >
> > From: Vincent Mailhol
> > > ACK. Would adding a suggested--by Linus tag solve your concern?
>
> I'm genberally the one person who doesn't need any more credit ;)
>
> >
On Thu, Dec 05, 2024 at 08:32:11PM -0800, Abhinav Kumar wrote:
> Each DP controller capable of MST can support multiple streams
> and each of the streams maps to an interface block ID which can
> vary based on chipset. Add a stream to interface map for MST capable
> DP controllers.
>
> Signed-off-
On Thu, Dec 05, 2024 at 08:31:33PM -0800, Abhinav Kumar wrote:
> dp_ctrl_off_link() was created to handle a case where we received
> a cable connect and then get a cable disconnect without the corresponding
> dp_display_enable(). For such cases the pixel clock will be off but the
> link clock will
On Thu, Dec 05, 2024 at 08:31:34PM -0800, Abhinav Kumar wrote:
> Interface type of MST interfaces is currently INTF_NONE.
> Fix this to INTF_DP.
Neither subject nor commit message tell that this is limited to sa8775p
only. Please consider toggling all catalog files which are supposed to
handle MST
On Thu, Dec 05, 2024 at 08:31:36PM -0800, Abhinav Kumar wrote:
> Add a helper to check whether a dp_panel is mst capable.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/dp/dp_aux.h | 1 +
> drivers/gpu/drm/msm/dp/dp_panel.c | 14 ++
> drivers/gpu/drm/msm/dp/dp_panel.
On Thu, Dec 05, 2024 at 08:31:35PM -0800, Abhinav Kumar wrote:
> In preparation of DP MST where link caps are read for the
> immediate downstream device and the edid is read through
> sideband messaging, split the msm_dp_panel_read_sink_caps() into
> two parts which read the link parameters and the
On Thu, Dec 05, 2024 at 08:31:37PM -0800, Abhinav Kumar wrote:
> dp_display caches the current display mode and then passes it onto
> the panel to be used for programming the panel params. Remove this
> two level passing and directly populated the panel's dp_display_mode
> instead.
Remove both and
On Thu, Dec 05, 2024 at 08:31:47PM -0800, Abhinav Kumar wrote:
> p1 register block is needed for the second mst stream.
> Add support in the catalog to be able to program this block.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 29 +
>
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Acked-by: Abhinav Kumar
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Bary
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Acked-by: Raphael Gallais-Pou
Signed-off-by: Dmitry Baryshkov
---
drivers/gp
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
From: Tomi Valkeinen
Currently the driver always writes DPTSR when setting up the hardware.
However, writing the register is only meaningful when the second source
for a plane is used, and the register is not even documented for SoCs
that do not have the second source.
So move the write behind a
The connector->eld is accessed by the .get_eld() callback. This access
can collide with the drm_edid_to_eld() updating the data at the same
time. Add drm_connector.eld_mutex to protect the data from concurrenct
access. Individual drivers are not updated (to reduce possible issues
while applying the
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/analogix/anx7625.c
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/amd/display/amdgpu_dm/amd
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 2
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/ite-it66121.c | 2
The connector->eld is accessed by the .get_eld() callback. This access
can collide with the drm_edid_to_eld() updating the data at the same
time. Add drm_connector.eld_mutex to protect the data from concurrenct
access.
The individual drivers were just compile tested. I propose to merge the
drm_con
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Reviewed-by: Jani Nikula
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshko
Reading access to connector->eld can happen at the same time the
drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
order to protect connector->eld from concurrent access.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/radeon/radeon_audio.c | 2
From: Tomi Valkeinen
The driver checks for bit 16 (using CLOCKSET1_LOCK define) in CLOCKSET1
register when waiting for the PPI clock. However, the right bit to check
is bit 17 (CLOCKSET1_LOCK_PHY define). Not only that, but there's
nothing in the documents for bit 16 for V3U nor V4H.
So, fix the
As the BOs used by VC4 have DMA Reservation Objects attached to it,
there is no need to use seqnos wait for the BOs availability. Instead,
we can use `dma_gem_dma_resv_wait()`.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/vc4/vc4_drv.h | 10 ++
drivers/gpu/drm/vc4/vc4_gem.c | 31 ++
This series introduces a series of clean-ups in BO reservations for the
VC4 driver. Currently, VC4 uses shared fences to track BO reservations as
several other DRM devices. But apart from the DMA reservation objects, VC4
also attaches seqnos to its BOs with the intention to track if the job that
us
`bo->seqno`, `bo->write_seqno`, and `exec->bin_dep_seqno` are leftovers
from a time when VC4 didn't support DMA Reservation Objects. When they
were introduced, it made sense to think about tracking the correspondence
between the BOs and the jobs through the job's seqno.
This is no longer needed, a
The function `vc4_queue_seqno_cb()` is no longer needed, as we are
using DMA Reservation Objects to track BOs. Using DMA Resv, we can use
`dma_fence_add_callback()` to perform the async page flip.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/vc4/vc4_drv.h | 3 ---
drivers/gpu/drm/vc4/vc4_gem.
Instead of creating internal copies of `drm_gem_lock_reservations()`
and `drm_gem_unlock_reservations()`, use the functions provided by DRM
GEM.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/vc4/vc4_gem.c | 66 ---
1 file changed, 6 insertions(+), 60 deletions(-)
Hi Tomi,
On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen
wrote:
> From: Tomi Valkeinen
>
> Add display related clocks for DU, DSI, FCPVD, and VSPD.
>
> Signed-off-by: Tomi Valkeinen
> Reviewed-by: Laurent Pinchart
> Tested-by: Geert Uytterhoeven
Reviewed-by: Geert Uytterhoeven
i.e. will queu
Hi,
On Thu, Dec 05, 2024 at 08:10:13AM +0800, Zijun Hu wrote:
> From: Zijun Hu
>
> Constify the following API:
> struct device *device_find_child(struct device *dev, void *data,
> int (*match)(struct device *dev, void *data));
> To :
> struct device *device_find_child(struct device
On Tue, Dec 03, 2024 at 02:19:41PM +0200, Dmitry Baryshkov wrote:
> On Mon, Dec 02, 2024 at 02:20:04PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > Sorry, I've been drowning under work and couldn't review that series before.
>
> No worries, at this point I'm more concerned about my IGT series rath
Am 06.12.24 um 14:12 schrieb Maíra Canal:
This series introduces a series of clean-ups in BO reservations for the
VC4 driver. Currently, VC4 uses shared fences to track BO reservations as
several other DRM devices. But apart from the DMA reservation objects, VC4
also attaches seqnos to its BOs wi
Hi Nikolaus,
On 03/12/2024 at 20:09:52 +01, Nikolaus Voss wrote:
> LDB clock has to be a fixed multiple of the pixel clock.
Not only, IIUC it also needs to be synchronized, ie. share the same
source.
> As LDB and pixel clock are derived from different clock sources
> (at least on imx8mp),
Wai
On Tue, Dec 03, 2024 at 02:27:44PM +0200, Dmitry Baryshkov wrote:
> On Mon, Dec 02, 2024 at 02:27:49PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > On Sun, Dec 01, 2024 at 02:44:13AM +0200, Dmitry Baryshkov wrote:
> > > Use the helper function to update the connector's information. This
> > > makes
Hi Rafael,
since 6.13-rc1 is out, hopefully you can have a look over the next few days
We have deployed a variant of this patchset now on desktop builds as
well for over 2 months now, and we haven't had any regressions
reported. We have also been using it on handheld builds, where for the
last 2 o
The pull request you sent on Fri, 6 Dec 2024 22:12:48 +0100:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2024-12-06
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/c7cde621b2acfd6bc7d5f002b19b60ad2ed25df8
Thank you!
--
Deet-doot-dot, I am a bot.
ht
On 12/6/24 3:24 PM, A. Sverdlin wrote:
From: Alexander Sverdlin
Add driver for TI LP8864, LP8864S, LP8866 4/6 channel LED-backlight drivers
with I2C interface.
Link: https://www.ti.com/lit/gpn/lp8864-q1
Link: https://www.ti.com/lit/gpn/lp8864s-q1
Link: https://www.ti.com/lit/gpn/lp8866-q1
Link
Add recent improvements and bug fixes for amdxdna driver (depends on [1])
1. Support recent hardware and firmware.
2. Replace idr APIs with xarray.
3. Fix the bugs been found.
[1]: https://lore.kernel.org/all/20241118172942.2014541-1-lizhi@amd.com/
Changes since v1:
- Add one patch to fix pos
Add NPU6 registers and other private configurations.
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/Makefile| 3 +-
drivers/accel/amdxdna/npu6_regs.c | 121 ++
2 files changed, 123 insertions(+), 1
Enhance GET_INFO ioctl to support retrieving firmware version.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_pci.c | 20
include/uapi/drm/amdxdna_accel.h | 16 +++-
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/accel/amdxdna/aie
Hardware mailbox message receiving handler calls mmput to release the
process mm. If the process has already exited, the mmput here may call mmu
notifier handler, amdxdna_hmm_invalidate, which will cause a dead lock.
Using mmput_async instead prevents this dead lock.
Fixes: aac243092b70 ("accel/am
Add SET_STATE ioctl to configure device power mode for aie2 device.
Three modes are supported initially.
POWER_MODE_DEFAULT: Enable clock gating and set DPM (Dynamic Power
Management) level to value which has been set by resource solver or
maximum DPM level the device supports.
POWER_MODE_HIGH: E
Switch mailbox message id and hardware context id management over from
the idr api to the xarray api.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/TODO | 1 -
drivers/accel/amdxdna/aie2_ctx.c| 4 +-
drivers/accel/amdxdna/aie2_message.c| 4 +-
drivers/accel/amdxd
For amdxdna_mailbox.c, linux/interrupt.h is indirectly included by
trace/events/amdxdna.h. So if TRACING is disabled, driver compiling will
fail.
Fixes: b87f920b9344 ("accel/amdxdna: Support hardware mailbox")
Reported-by: Mike Lothian
Closes:
https://lore.kernel.org/dri-devel/CAHbf0-E+Z2O7rW-x+
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. If the firmware interface does not compatible with
the driver, the driver's probe routine returns failure.
Co-developed-by: Min Ma
...
> > > #define const_NULL(x) _Generic(0 ? (x) : (char *)0, char *: 1, void *: 0)
> > > #define const_true(x) const_NULL((x) ? NULL : (void *)1L))
> > > #define const_expr(x) const_NULL((x) ? NULL : NULL))
> > > I send this morning.
> > > Needs 's/char/struct kjkjkjkjui/' applied.
> >
> > Oh Chri
On Mon, Dec 02, 2024 at 10:07:23PM +0200, Imre Deak wrote:
> On Mon, Dec 02, 2024 at 05:35:34PM +0100, Simona Vetter wrote:
> > On Tue, Nov 26, 2024 at 06:18:56PM +0200, Imre Deak wrote:
> > > Atm when the connector is added to the drm_mode_config::connector_list,
> > > the connector may not be ful
Hi Linus,
Due to mailing list unreliability we missed the amdgpu pull, hence part 2
with that now included.
drm-fixes-2024-12-06:
drm fixes for -rc2, part 2
- amdgu: mostly display fixes + jpeg vcn 1.0, sriov, dcn4.0 resume
firxes
- amdkfd fixes
Cheers, Sima
The following changes since commi
On Fri, 2024-12-06 at 22:24 +0100, A. Sverdlin wrote:
> From: Alexander Sverdlin
>
> The series adds support for a family of Texas Instruments' automotive
> high-efficiency LED drivers with boost controller. The four or six
> high-precision current sinks support phase shifting that is automatical
Add device status to track if aie2_hw_start() or aie2_hw_stop() is
re-entered. In aie2_hw_stop(), call drmm_kfree to free mbox.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_pci.c| 17 +
drivers/accel/amdxdna/aie2_pci.h| 7 +++
drivers/accel/amdxdna
I can send one in tomorrow if you like
On Fri, 6 Dec 2024, 22:55 Jeffrey Hugo, wrote:
> On 12/6/2024 11:47 AM, Lizhi Hou wrote:
> >
> > On 12/6/24 09:01, Mike Lothian wrote:
> >> On Fri, 6 Dec 2024 at 16:41, Mike Lothian wrote:
> >>> On Fri, 6 Dec 2024 at 16:26, Jeffrey Hugo
> >>> wrote:
> >>>
On 9/25/2024 12:23 AM, Maxime Ripard wrote:
On Tue, Sep 24, 2024 at 03:59:18PM GMT, Jessica Zhang wrote:
Check that all encoders attached to a given CRTC are valid
possible_clones of each other.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_helper.c | 23
Hi Ian,
On Thu, Dec 05, 2024 at 11:38:25PM -0800, Ian Rogers wrote:
> When /proc/pid/fdinfo was part of proc.5 man page the indentation made
> sense. As a standalone man page the indentation doesn't need to be so
> far over to the right. Remove the initial tagged pragraph, move the
> "since Linux
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