From: Dave Airlie
These WARN_ONs seem to trigger a lot, and we don't seem to have a
plan to fix them, so just drop them, as they are most likely
harmless.
Cc: sta...@vger.kernel.org
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 12 ++--
1 file changed,
On Wed, Nov 20, 2024 at 5:17 PM Petr Vorel wrote:
>
> > On Thu, Nov 21, 2024 at 5:41 AM Petr Vorel wrote:
>
> > > It will be used in the next commit for DRM_MSM.
>
> > > Suggested-by: Rob Clark
> > > Signed-off-by: Petr Vorel
> > > ---
> > > Changes v3->v4:
> > > * Move definition to the end of
This patch series aims to fix 2 bugs in the ADV7535 driver
1) use-after-free bug in adv7533_attach_dsi()
2) Drop unsupported single lane.
Changes in v5:
- Updated commit description for patch#1.
- restored host_node in struct adv7511.
- Dropped of_node_put() in adv7533_parse_dt() and calling o
As per [1] and [2], ADV7535/7533 supports only 2-, 3-, or 4-lane. Drop
unsupported 1-lane from bindings.
[1]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7535.pdf
[2]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7533.pdf
Fixes: 1e4d58cd7f88 ("
On Tue, Nov 19, 2024 at 01:13:26PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> > Add SVM init / close / fini to faulting VMs. Minimual implementation.
> >
> > v2:
> > - Add close function
> >
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gp
> -Original Message-
> From: Uwe Kleine-König
> Sent: 2024年11月20日 22:56
> To: Keith Zhao
> Cc: devicet...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jernej.skra...@gmail.c
On Tue, Nov 19, 2024 at 09:33:26AM -0500, Leonard Lausen wrote:
> > I'm seeing the same issue as György on the x1e80100 CRD and Lenovo
> > ThinkPad T14s. Without this patch, the internal display fails to resume
> > properly (switching VT brings it back) and the following errors are
> > logged:
> >
On Wed, Nov 20, 2024 at 02:38:49PM +0100, Christian König wrote:
> Am 19.11.24 um 00:37 schrieb Matthew Brost:
> > Normalize user fence attachment to a DMA fence. A user fence is a simple
> > seqno write to memory, implemented by attaching a DMA fence callback
> > that writes out the seqno. Intende
Hi,
On Tue, Nov 12, 2024 at 1:12 PM Christophe JAILLET
wrote:
>
> 'struct i2c_device_id' is not modified in these drivers.
>
> Constifying this structure moves some data to a read-only section, so
> increase overall security.
>
> On a x86_64, with allmodconfig, as an example:
> Before:
> ==
>
On Wed, Nov 20, 2024 at 3:18 AM Dmitry Baryshkov
wrote:
>
> On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wrote:
> > Now the features defines have the right name, introduce a features
> > bitfield and move the features defines in it, fixing all code checking
> > for them.
> >
> > No fun
On Wed, Nov 20, 2024 at 7:49 AM Petr Vorel wrote:
>
> 0fddd045f88e introduced python3 dependency, require it to quick early.
>
> Signed-off-by: Petr Vorel
> ---
> Hi all,
>
> RFC because I'm not sure if previous failed build wasn't better:
>
> GENHDR drivers/gpu/drm/msm/generated/a2xx.xm
On Tue, 19 Nov 2024 13:50:29 +
Karunika Choo wrote:
> Stop checking the FW halt_status as MCU_STATUS should be sufficient.
> This should make the check for successful FW halt and subsequently
> setting fast_reset to true more robust.
>
> We should also clear GLB_REQ.GLB_HALT bit only on post
On Thu, Nov 21, 2024 at 5:41 AM Petr Vorel wrote:
>
> It will be used in the next commit for DRM_MSM.
>
> Suggested-by: Rob Clark
> Signed-off-by: Petr Vorel
> ---
> Changes v3->v4:
> * Move definition to the end of the file
I prefer to not check the tool.
Why don't you install python3?
>
> On Wed, Nov 20, 2024 at 7:49 AM Petr Vorel wrote:
> > 0fddd045f88e introduced python3 dependency, require it to quick early.
> > Signed-off-by: Petr Vorel
> > ---
> > Hi all,
> > RFC because I'm not sure if previous failed build wasn't better:
> > GENHDR drivers/gpu/drm/msm/generat
Hi everyone, this is my very first trivial contribution to the Linux kernel and
I started from a very basic task.
As the subject suggests I removed hard-coded string by using str_true_false()
helper.
Paolo Perego (1):
Remove hard-coded strings by using the helper functions
str_true_false()
On Wed, Nov 20, 2024 at 01:02:32PM +0200, Dmitry Baryshkov wrote:
> On Wed, Nov 20, 2024 at 10:34:51AM +0530, Dheeraj Reddy Jonnalagadda wrote:
> > The variable pixel_div can remain zero due to an invalid rate input,
>
> No, it can not. Rate is set by the driver, which knowns which rates are
> sup
The supported resolutions were misrepresented in earlier versions of
hardware manuals.
Fixes: 768e9e61b3b9 ("drm: renesas: Add RZ/G2L DU Support")
Cc: sta...@vger.kernel.org
Signed-off-by: Chris Brandt
---
drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 6 +++---
1 file changed, 3 insertions(+),
0fddd045f88e introduced python3 dependency, use HAVE_PYTHON3 to make it
obvious.
Signed-off-by: Petr Vorel
---
Changes v2->v3:
* Update commit message (I'm sorry for the noise).
drivers/gpu/drm/msm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers
0fddd045f88e introduced python3 dependency, require it to quick early.
Signed-off-by: Petr Vorel
---
Changes v1->v2:
* use HAVE_PYTHON3
drivers/gpu/drm/msm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 90c68106b63b..0
It will be used in the next commit for DRM_MSM.
Suggested-by: Rob Clark
Signed-off-by: Petr Vorel
---
Changes v2->v3:
The same as in v2.
init/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/init/Kconfig b/init/Kconfig
index fbd0cb06a50a..2561eaebd1d3 100644
--- a/init/Kconfig
++
Signed-off-by: Paolo Perego
---
drivers/staging/fbtft/fb_ssd1351.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/fbtft/fb_ssd1351.c
b/drivers/staging/fbtft/fb_ssd1351.c
index f6db2933ebba..6736b09b2f45 100644
--- a/drivers/staging/fbtft/fb_ssd1351.c
+++ b/
0fddd045f88e introduced python3 dependency, require it to quick early.
Signed-off-by: Petr Vorel
---
Hi all,
RFC because I'm not sure if previous failed build wasn't better:
GENHDR drivers/gpu/drm/msm/generated/a2xx.xml.h
/bin/sh: python3: not found
This way it's documented, b
It will be used in the next commit for DRM_MSM.
Suggested-by: Rob Clark
Signed-off-by: Petr Vorel
---
New in v2
init/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/init/Kconfig b/init/Kconfig
index fbd0cb06a50a..2561eaebd1d3 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -262,
Using str_true_false() helper instead of hardcoded strings.
Signed-off-by: Paolo Perego
---
v2:
* Used a shorter email subject
* Added a commit message
* The email subject now contains kernel subsytem
drivers/staging/fbtft/fb_ssd1351.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
d
From: Matthew Brost
[ Upstream commit dd886a63d6e2ce5c16e662c07547c067ad7d91f5 ]
GGTT mappings reside on the device and this state is lost during suspend
/ d3cold thus this state must be restored resume regardless if the BO is
in system memory or VRAM.
v2:
- Unnecessary parentheses around bo->
On Wed, Nov 20, 2024 at 04:59:43PM +0200, Imre Deak wrote:
> On Mon, Nov 18, 2024 at 05:14:52PM +0200, Jani Nikula wrote:
> > SST with 128b/132b channel coding needs this too. Extract to a separate
> > helper, independent of MST.
> >
> > Pass timeout in as a parameter, anticipating that we can red
Am 19.11.24 um 00:37 schrieb Matthew Brost:
Add a dma_fence_preempt base class with driver ops to implement
preemption, based on the existing Xe preemptive fence implementation.
Annotated to ensure correct driver usage.
Cc: Dave Airlie
Cc: Simona Vetter
Cc: Christian Koenig
Signed-off-by: Ma
On Wed, Nov 20, 2024 at 4:22 AM Jani Nikula
wrote:
>
> Please avoid all struct edid based interfaces, in this case
> drm_connector_update_edid_property(). They will be removed in the
> future, and adding more is counter-productive. Everything should be
> struct drm_edid based going forward.
>
> Of
On Mon, Nov 18, 2024 at 01:01:54PM +, Matt Coster wrote:
> All Imagination GPUs use three clocks: core, mem and sys. All reasonably
> modern Imagination GPUs also support a single-clock mode where the SoC
> only hooks up core and the other two are derived internally. On GPUs which
> support thi
On 18/11/2024 14:01, Matt Coster wrote:
> Use the new compatible string introduced earlier (in "dt-bindings: gpu:
> img: More explicit compatible strings") and add a name to the single power
> domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
> details").
>
> Signed-off-by: M
On Mon, Nov 18, 2024 at 01:02:00PM +, Matt Coster wrote:
> Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
> integration in the TI k3-j721s2.
>
> Signed-off-by: Matt Coster
> ---
> Changes in v2:
> - Use normal reg syntax for 64-bit values
> - Link to v1:
> https://lo
On 18/11/2024 14:01, Matt Coster wrote:
> Follow-on from the companion dt-bindings change ("dt-bindings: gpu: img:
> More explicit compatible strings"), deprecating "img,img-axe" in favour of
> the more specific "img,img-axe-1-16m".
>
> Keep the previous compatible string around for backwards comp
Sparse complains about incorrect type in argument 1.
expected void const volatile __iomem *ptr but got void *.
so modify mixer_dbg_mxn's addr parameter.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202411191809.6v3c826r-...@intel.com/
Fixes: a5f81078a56c ("drm/st
On Mon, Nov 18, 2024 at 01:01:56PM +, Matt Coster wrote:
> This attribute will be required for the BXS-4-64 MC1 and will be enabled in
> the DTS for the TI k3-j721s2 in a subsequent patch; add it now so
> dtbs_check doesn't complain later.
That's not a reason. You add it because device is DMA
On Wed, Nov 20, 2024 at 10:34:51AM +0530, Dheeraj Reddy Jonnalagadda wrote:
> The variable pixel_div can remain zero due to an invalid rate input,
No, it can not. Rate is set by the driver, which knowns which rates are
supported.
> leading to a potential division by zero issue. This patch fixes
On Mon, Nov 18, 2024 at 01:01:55PM +, Matt Coster wrote:
> The single existing GPU (AXE-1-16M) only requires a single power domain.
> Subsequent patches will add support for BXS-4-64 MC1, which has two power
> domains. Add infrastructure now to allow for this.
>
> Signed-off-by: Matt Coster
>
> -Original Message-
> From: Intel-gfx On Behalf Of Arun
> R Murthy
> Sent: Tuesday, November 19, 2024 4:15 PM
> To: intel...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCH 8/8] drm/i915/histogram: Enabl
On 19/11/24 10:56, Louis Chauvet wrote:
On 19/11/24 - 14:34, Louis Chauvet wrote:
VKMS currently supports only one CRTC, so it make no sense to have this
index configurable. To avoid issues, replace this hardcoded index by
drm_crtc_mask when applicable.
There is no need to manually set a crtc m
On Tue, Nov 19, 2024 at 06:56:46PM +0100, Neil Armstrong wrote:
> Each GPU OPP requires a specific peak DDR bandwidth, let's add
> those to each OPP and also the related interconnect path.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++
> 1 fil
On Wed, Oct 30, 2024 at 10:54:04PM +, Akash Goel wrote:
> This patch series contains 3 cache coherency related fixes for the
> Panthor driver.
> - The first fix, regarding the Inner-shareability, is mandatory to
> ensure things work on all platforms (including Juno FPGA) when
> no_coherency
On Tue, 19 Nov 2024 16:44:55 +
Liviu Dudau wrote:
> Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path") forgot
> to copy the definition of glb_iface when it move one line of code.
>
> Fixes: Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path")
> Signed-off-by: Liviu
On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
> The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along
> the Frequency and Power Domain level, but by default we leave the
> OPP core scale the interconnect ddr path.
>
> In order to calculate vote values used by th
On Tue, Nov 19, 2024 at 06:56:42PM +0100, Neil Armstrong wrote:
> The Adreno GMU Management Unit (GMU) can also scale the DDR Bandwidth
> along the Frequency and Power Domain level, until now we left the OPP
> core scale the OPP bandwidth via the interconnect path.
>
> In order to enable bandwidth
On Tue, Nov 19, 2024 at 06:56:44PM +0100, Neil Armstrong wrote:
> Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
> is in place, declare the Bus Control Modules (BCMs) and the
> corresponding parameters in the GPU info struct and add the
> GMU_BW_VOTE feature bit to enable it.
>
On Tue, Nov 19, 2024 at 06:56:45PM +0100, Neil Armstrong wrote:
> Each GPU OPP requires a specific peak DDR bandwidth, let's add
> those to each OPP and also the related interconnect path.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++
> 1 file c
On Wed, Nov 20, 2024 at 12:41:25PM +0100, Boris Brezillon wrote:
> On Tue, 19 Nov 2024 16:44:55 +
> Liviu Dudau wrote:
>
> > Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path") forgot
> > to copy the definition of glb_iface when it move one line of code.
> >
> > Fixes: Commit 49
In intel-dg, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/m
Register the on-die nvm device with the mtd subsystem.
Refcount nvm object on _get and _put mtd callbacks.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Acked-by: Miquel Raynal
Co-de
Hi Dmitry,
> Subject: Re: [PATCH v2 2/5] drm/virtio: Add a helper to map and note the
> dma addrs and lengths
>
> ...
> > After rebasing v2 of this patch series on top of the above patch, I see that
> > this use-case works as expected with Qemu master. Let me send out v3,
> > which would be a reb
On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> From: Thomas Hellström
>
> Useful for SVM ranges in SRAM and programing page tables.
We should look at providing a better commit message.
>
> Signed-off-by: Matthew Brost
> Signed-off-by: Thomas Hellström
> ---
> drivers/gpu/drm/xe/x
As per [1] and [2], ADV7535/7533 supports only 2-, 3-, or 4-lane. Drop
unsupported 1-lane from bindings.
[1]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7535.pdf
[2]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7533.pdf
Fixes: 1e4d58cd7f88 ("
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS| 7 ++
dr
On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> Add SVM init / close / fini to faulting VMs. Minimual implementation.
>
> v2:
> - Add close function
>
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_svm.c | 46
> +++
Adding Michal from the compute userspace team for sharing references to
the code.
Quoting Christian König (2024-11-19 12:00:44)
> Am 19.11.24 um 00:37 schrieb Matthew Brost:
> > From: Tejas Upadhyay
> >
> > In order to avoid having userspace to use MI_MEM_FENCE,
> > we are adding a mechanism for
On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wrote:
> Now the features defines have the right name, introduce a features
> bitfield and move the features defines in it, fixing all code checking
> for them.
>
> No functional changes intended.
I think it might be better to squahs this p
This IP includes a Pattern Generator which is useful for debugging
and testing purposes: add the relevant register and bits to the
mtk_dpi_regs.h header, and implement support for it in mtk_dpi.
Adding this required to introduce a .debugfs_init() callback for
the DPI bridge, which creates a "dpi_t
On Tue, Nov 19, 2024 at 10:02:33PM -0500, Leonard Lausen wrote:
> The finding is that while 6.10.14 with this patch applied still suffers from
> that regression, 6.11.9 and 6.12 do not face the CRTC state regression.
> Therefore, whatever issue the patch uncovered in older kernels and which
> just
On Fri, Aug 02, 2024 at 10:47:33PM +0300, Dmitry Baryshkov wrote:
> During suspend/resume process all connectors are explicitly disabled and
> then reenabled. However resume fails because of the connector_status check:
>
> [ 1185.831970] [dpu error]connector not connected 3
Please also include th
On Wed, 2024-11-20 at 10:24 +0100, Christian König wrote:
> Am 20.11.24 um 08:58 schrieb Thomas Hellström:
> > On Tue, 2024-11-19 at 14:40 +0100, Christian König wrote:
> > > [SNIP]
> > > > +
> > > > +/*
> > > > + * Casting from randomized struct file * to struct ttm_backup
> > > > * is
> > > > fin
Am 20.11.24 um 11:34 schrieb Thomas Hellström:
On Wed, 2024-11-20 at 10:24 +0100, Christian König wrote:
Am 20.11.24 um 08:58 schrieb Thomas Hellström:
On Tue, 2024-11-19 at 14:40 +0100, Christian König wrote:
[SNIP]
+
+/*
+ * Casting from randomized struct file * to struct ttm_backup
* is
fi
Am 15.11.24 um 16:01 schrieb Thomas Hellström:
Make the interface more symmetric by providing and using a
ttm_resource_cursor_init().
v10:
- Fix a stray newline (Matthew Brost)
- Update kerneldoc (Matthew Brost)
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Brost
Reviewed-by: Christian
On 20/11/2024 12:19, Dmitry Baryshkov wrote:
On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
along the Frequency and Power Domain level, but by default we leave the
OPP core vote for the interconnect ddr path.
On 20/11/2024 12:47, Dmitry Baryshkov wrote:
On Tue, Nov 19, 2024 at 06:56:45PM +0100, Neil Armstrong wrote:
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8
At least version 2 of the HDMI PHY, found in MediaTek MT8195 and
MT8188 SoCs, does provide hardware support to switch on/off the
HDMI 5V pins (which are also used for DDC), and this translates
to this being a fixed regulator.
Register this PHY-provided regulator so that it can be fed to the
hdmi-c
In preparation for splitting out the common bits from the HDMI
driver, change the mtk_cec driver from being registered from the
HDMI driver itself to be a module_platform_driver of its own.
With this change, there are no more users of the mtk_hdmi.h header
so, while at it, also remove it.
Signed-
In preparation for adding a new driver for the HDMI TX v2 IP,
split out the functions that will be common between the already
present mtk_hdmi (v1) driver and the new one.
Since the probe flow for both drivers is 90% similar, add a common
probe function that will be called from each driver's .prob
Add support for the DPI block found in the MT8195 and MT8188 SoCs.
Inside of the SoC, this block is directly connected to the HDMI IP.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 55 ++---
drivers/gpu/drm/mediatek/mtk_dpi_regs.h |
Add compatibles for the Digital Parallel Interface (DPI) block
found in the MT8195 and MT8188 SoCs: inside of the chip, this one
is directly connected to the HDMI block.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +
1 file
Setting the TVD PLL clock requires to multiply the target pixel
clock by a specific constant factor to achieve the target PLL
frequency, and this is done to reduce jitter to acceptable levels.
On all MediaTek SoCs, the factor is not retrieved by any real kind
of calculation but rather by checking
Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
and MT8188 SoCs.
This fully supports the HDMI Specification 2.0b, hence it provides
support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and
xvYCC, with o
Add support for the direct connection DPI found in MT8195 and MT8188 SoCs.
Bonus in this series is the addition of support for the Pattern Generator
found in the DPI HW: since I needed this for debugging during development,
I had to code in the actual support bits and it looked like a waste of
tim
In preparation for splitting out the common bits from the HDMI
driver, change the mtk_cec driver from being registered from the
HDMI driver itself to be a module_platform_driver of its own.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_cec.c | 5 -
drivers/gpu/
In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.
As a
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
found in MediaTek's MT8195, MT8188 SoC and their variants, and
including support for display modes up to 4k60 and for HDMI
Audio, as per the HDMI 2.0 spec.
HDCP and CEC functionalities are also supported by this hardware,
but are not in
This series adds support for the HDMI-TX v2 Encoder and DDCv2, as found
in MT8195, MT8188 and their variants.
Tested on Genio 700 EVK:
- ABIST ON: ok, pattern generated internally from HDMI is shown on
HDMI screen at the correct resolution;
- ABIST OFF + DPI Pattern Generator ON: ok, pattern
On 20/11/2024 12:42, Dmitry Baryshkov wrote:
On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along
the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
In ord
From: Guillaume Ranquet
In preparation for the addition of a new version of the HDMI IP
which will need to share its iospace between multiple subdrivers,
and in preparation for moving out the common bits between the two,
migrate this driver to fully use regmap.
Signed-off-by: Guillaume Ranquet
Add a binding for the Display Data Channel (DDC) IP in MediaTek
SoCs with version 2 HDMI TX IP.
Signed-off-by: AngeloGioacchino Del Regno
---
.../mediatek/mediatek,mt8195-hdmi-ddc.yaml| 41 +++
1 file changed, 41 insertions(+)
create mode 100644
Documentation/devicetree/bi
On Wed, Nov 20, 2024 at 5:22 AM Jani Nikula wrote:
>
> On Wed, 20 Nov 2024, Thomas Zimmermann wrote:
> > Hi
> >
> >
> > Am 19.11.24 um 20:40 schrieb Ian Forbes:
> >> Most compositors are using a change in EDID as an indicator to
> >> refresh their connector information on hotplug regardless of wh
On Tue, Nov 19, 2024 at 03:25:25PM +0100, Boris Brezillon wrote:
> On Tue, 19 Nov 2024 13:50:29 +
> Karunika Choo wrote:
>
> > Stop checking the FW halt_status as MCU_STATUS should be sufficient.
> > This should make the check for successful FW halt and subsequently
> > setting fast_reset to
Am 20.11.24 um 08:58 schrieb Thomas Hellström:
On Tue, 2024-11-19 at 14:40 +0100, Christian König wrote:
[SNIP]
+
+/*
+ * Casting from randomized struct file * to struct ttm_backup * is
fine since
+ * struct ttm_backup is never defined nor dereferenced.
+ */
+static struct file *ttm_backup_to_f
Hi
Am 19.11.24 um 20:40 schrieb Ian Forbes:
Most compositors are using a change in EDID as an indicator to
refresh their connector information on hotplug regardless of whether the
connector was previously connected. Originally the hotplug_mode_update
property was supposed to provide a hint to u
On Mon, Nov 18, 2024 at 01:01:53PM +, Matt Coster wrote:
> The current compatible strings are not specific enough to constrain the
No, they are specific enough.
> hardware in devicetree. For example, the current "img,img-axe" string
> refers to the entire family of Series AXE GPUs. The more s
> -Original Message-
> From: dri-devel On Behalf Of
> Arun R Murthy
> Sent: Tuesday, November 19, 2024 4:15 PM
> To: intel...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv5 5/8] drm/i915/histogram: Add
On 18/11/2024 14:02, Matt Coster wrote:
> The J721S2 binding is based on the TI downstream binding in 54b0f2a00d92
> ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated
> compatible strings.
>
> The clock[2] and power[3] indices were verified from docs, but the
> source of t
The variable pixel_div can remain zero due to an invalid rate input,
leading to a potential division by zero issue. This patch fixes it and
the function now logs an error and returns early.
Additionally, this patch resolves trailing whitespace issues detected
by checkpatch.pl in the same file.
Si
Hello Heiko,
> This series adds a bridge and glue driver for the DSI2 controller found
> in the rk3588 soc from Rockchip, that is based on a Synopsis IP block.
>
> As the manual states:
> The Display Serial Interface 2 (DSI-2) is part of a group of communication
> protocols defined by the MIPI Al
On Wed, Nov 20, 2024 at 10:30:20AM +0100, Paolo Perego wrote:
> Signed-off-by: Paolo Perego
> ---
> drivers/staging/fbtft/fb_ssd1351.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/staging/fbtft/fb_ssd1351.c
> b/drivers/staging/fbtft/fb_ssd1351.c
> index f6d
> -Original Message-
> From: Intel-xe On Behalf Of Arun R
> Murthy
> Sent: Tuesday, November 19, 2024 4:15 PM
> To: intel...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCH 6/8] drm/i915/histogram: histog
On Wed, 20 Nov 2024, Thomas Zimmermann wrote:
> Hi
>
>
> Am 19.11.24 um 20:40 schrieb Ian Forbes:
>> Most compositors are using a change in EDID as an indicator to
>> refresh their connector information on hotplug regardless of whether the
>> connector was previously connected. Originally the hotp
> -Original Message-
> From: Intel-xe On Behalf Of Arun R
> Murthy
> Sent: Tuesday, November 19, 2024 4:15 PM
> To: intel...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv4 7/8] drm/i915/histogram: Hist
On Wed, 2024-11-20 at 11:50 +0100, Christian König wrote:
> Am 20.11.24 um 11:34 schrieb Thomas Hellström:
> > On Wed, 2024-11-20 at 10:24 +0100, Christian König wrote:
> > > Am 20.11.24 um 08:58 schrieb Thomas Hellström:
> > > > On Tue, 2024-11-19 at 14:40 +0100, Christian König wrote:
> > > > > [
On Wed, 2024-11-20 at 10:24 +0100, Christian König wrote:
>
[SNIP]
> > > Just that I sleep better: This can never return a folio larger
> > > than a
> > > page, doesn't it?
> > The interface definitely allows for returning larger folios, but
> > the
> > individual page in the folio is selected b
On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
> along the Frequency and Power Domain level, but by default we leave the
> OPP core vote for the interconnect ddr path.
>
> While scaling via the interconnect pa
On Wed, Nov 20, 2024 at 10:30:20AM +0100, Paolo Perego wrote:
> Signed-off-by: Paolo Perego
You need to have a subsystem prefix in the subject. The subject is probably too
long as well. You need to have a commit message.
Otherwise, fine.
https://staticthinking.wordpress.com/2022/07/27/how-to-
On Tue, Nov 19, 2024 at 04:44:55PM +, Liviu Dudau wrote:
> Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path") forgot
> to copy the definition of glb_iface when it move one line of code.
>
> Fixes: Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path")
> Signed-off-by: L
In preparation for adding support for the DPI IP found in MT8195
and in MT8188 used for HDMI, move the code flow for calculation
and setting of the DPI pixel clock to a separate function called
mtk_dpi_set_pixel_clk().
This was done because, on those platforms, the DPI instance that
is used for HD
in function `i915_gem_gtt_reserve` @node comment,
i915_vma has no `mode` member, `i915_vma.node` is the correct name
Signed-off-by: Zhang He
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/
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