On Sun, Nov 10, 2024 at 9:31 AM Bjorn Andersson
wrote:
>
> The QCOM_SCM_SVC_MP service provides QCOM_SCM_MP_CP_SMMU_APERTURE_ID,
> which is used to trigger the mapping of register banks into the SMMU
> context for per-processes page tables to function (in case this isn't
> statically setup by firm
On Sun, Nov 10, 2024 at 9:31 AM Bjorn Andersson
wrote:
>
> Support for per-process page tables requires the SMMU aparture to be
> setup such that the GPU can make updates with the SMMU. On some targets
> this is done statically in firmware, on others it's expected to be
> requested in runtime by t
The hardware mailboxes are used by the driver to submit requests to
firmware and receive the completion notices from hardware.
Initially, a management mailbox channel is up and running. The driver may
request firmware to create/destroy more channels dynamically through
management channel.
Add dri
AMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator
integrated into AMD client APU. NPU enables efficient execution of Machine
Learning applications like CNN, LLM, etc. NPU is based on AMD XDNA
Architecture. NPU is managed by amdxdna driver.
Co-developed-by: Sonal Santan
Sig
The hardware can be shared among multiple user applications. The
hardware resources are allocated/freed based on the request from
user application via driver IOCTLs.
DRM_IOCTL_AMDXDNA_CREATE_HWCTX
Allocate tile columns and create a hardware context structure to track the
usage and status of the re
The AI Engine consists of 2D array of tiles arranged as columns. Provides
the basic column allocation and release functions for the tile columns.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/Makefile | 1
Add interfaces for user application to submit command and wait for its
completion.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_ctx.c | 607 +-
drivers/accel/amdxdna/aie2_message.c | 343 ++
When there is a hardware error, the NPU firmware notifies the host through
a mailbox message. The message includes details of the error, such as the
tile and column indexes where the error occurred.
The driver starts a thread to handle the NPU error message. The thread
stops the clients which are
There different types of BOs are supported:
- shmem
A user application uses shmem BOs as input/output for its workload running
on NPU.
- device memory heap
The fixed size buffer dedicated to the device.
- device buffer
The buffer object allocated from device memory heap.
- command buffer
The bu
AMD AI Engine forms the core of AMD NPU and can be used for accelerating
machine learning applications.
Add the driver to support AI Engine integrated to AMD CPU.
Only very basic functionalities are added.
- module and PCI device initialization
- firmware load
- power up
- low level hardwa
Implement PCI power management suspend and resume callbacks.
Co-developed-by: Narendra Gutta
Signed-off-by: Narendra Gutta
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
---
drivers
Add GET_INFO ioctl to retrieve hardware information, including
AIE, clock, hardware context etc.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_message.c| 65 +++
drivers/accel/amdxdna/aie2_pci.c
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference accelerator integrated
into AMD client CPUs. NPU enables efficient execution of Machine Learning
applications like CNNs, LLMs, etc
On Sun, 06 Oct 2024 00:20:17 +0100, li...@treblig.org wrote:
> cdns_mhdp_hdcp_set_lc() and cdns_mhdp_hdcp_set_public_key_param()
> were added by commit
> 6a3608eae6d3 ("drm: bridge: cdns-mhdp8546: Enable HDCP")
> but never used.
>
> Remove them.
>
> [...]
Applied, thanks!
[1/1] drm/bridge: cdns
On Fri, Nov 08, 2024 at 09:18:53AM -0700, Shuah Khan wrote:
> The Code of Conduct committee's goal first and foremost is to bring about
> change to ensure our community continues to foster respectful discussions.
>
> In the interest of transparency, the CoC enforcement policy is formalized
> for u
Hello Alexander,
On 07/11/2024 at 15:13:46 +02, Alexander Usyskin
wrote:
> Add driver for access to Intel discrete graphics card
> internal NVM device.
> Expose device on auxiliary bus by i915 and Xe drivers and
> provide mtd driver to register this device with MTD framework.
>
> This is a rewr
On 28/10/2024 16:04, Leo Li wrote:
On 2024-10-25 22:01, Melissa Wen wrote:
On 25/10/2024 16:37, Zaeem Mohamed wrote:
[why]
Prevent index-out-of-bounds due to requiring cursor overlay when
plane_count is MAX_SURFACES.
Hi Zaeem,
Thanks for working on this fix.
[how]
Bounds check on
On 11/11/24 13:07, Simona Vetter wrote:
On Fri, Nov 08, 2024 at 09:18:53AM -0700, Shuah Khan wrote:
The Code of Conduct committee's goal first and foremost is to bring about
change to ensure our community continues to foster respectful discussions.
In the interest of transparency, the CoC enfor
On Mon, Nov 11, 2024 at 04:54:57PM +0100, Christian König wrote:
> Am 11.11.24 um 15:00 schrieb Joonas Lahtinen:
> > Quoting Christian König (2024-11-11 13:34:12)
> > > Am 11.11.24 um 11:10 schrieb Simona Vetter:
> > > > On Mon, Nov 11, 2024 at 10:00:17AM +0200, Joonas Lahtinen wrote:
> > > > > Bac
Den 2024-10-28 kl. 15:53, skrev Friedrich Vock:
On 23.10.24 09:52, Maarten Lankhorst wrote:
The initial version was based roughly on the rdma and misc cgroup
controllers, with a lot of the accounting code borrowed from rdma.
The current version is a complete rewrite with page counter; it use
Hi Alexander,
Please reduce the context when answering, otherwise it's hard to find
all places where you commented.
>> > > > That's the part that I'm not sure if I agree. if I remember from some
>> > > > experiments in the past,
>> > > > when you call to wake up the child, the parent will wakeup
On Mon, Nov 11, 2024 at 01:57:15PM +0100, Christian König wrote:
> Am 08.11.24 um 23:27 schrieb Matthew Brost:
> > On Tue, Sep 24, 2024 at 11:30:53AM +0200, Simona Vetter wrote:
> > > Apologies for the late reply ...
> > >
> > Also late reply, just read this.
> >
> > > On Wed, Sep 04, 2024 at 01:
On 2024-11-01 14:23, André Almeida wrote:
> amdgpu can handle async flips on overlay planes, so allow it for atomic
> async checks.
>
> Signed-off-by: André Almeida
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff
Hi Shuah,
On Mon, Nov 11, 2024 at 02:50:45PM -0700, Shuah Khan wrote:
> On 11/11/24 13:07, Simona Vetter wrote:
> > On Fri, Nov 08, 2024 at 09:18:53AM -0700, Shuah Khan wrote:
> >> The Code of Conduct committee's goal first and foremost is to bring about
> >> change to ensure our community continu
Ping, Vinod :-)
Andi
On Mon, Nov 11, 2024 at 07:32:42PM +0530, Jyothi Kumar Seerapu wrote:
> GSI hardware generates an interrupt for each transfer completion.
> For multiple messages within a single transfer, this results
> in receiving N interrupts for N messages, which can introduce
> significa
Bhavin Sharma (2):
drm: amd: display: Remove redundant check
drm: amd: pm: Remove redundant check
.../display/dc/dml/dml1_display_rq_dlg_calc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 13 --
.../amd/pm/powerplay/smumgr/vega12_smumgr.c | 24 +--
3 fil
The mode_422 variable is initialized to zero, making mode_422 ? 2 : 1
always false.
Since is_dsc_possible is already checked just above, there's no need to
check it again before filling out the DSC settings.
Removing this redundant check simplifies the code without affecting
functionality.
Signe
在 2024/11/11 22:39, Chuck Lever III 写道:
On Nov 10, 2024, at 9:36 PM, Yu Kuai wrote:
Hi,
在 2024/11/11 8:52, c...@kernel.org 写道:
From: yangerkun
[ Upstream commit 64a7ce76fb901bf9f9c36cf5d681328fc0fd4b5a ]
After we switch tmpfs dir operations from simple_dir_operations to
simple_offset_d
The check for tools_size being non-zero is redundant as tools_size is
explicitly set to a non-zero value (0x19000). Removing the if condition
simplifies the code without altering functionality.
Signed-off-by: Bhavin Sharma
---
.../amd/pm/powerplay/smumgr/vega12_smumgr.c | 24 +---
On 11/11/24 15:35, Laurent Pinchart wrote:
Hi Shuah,
On Mon, Nov 11, 2024 at 02:50:45PM -0700, Shuah Khan wrote:
On 11/11/24 13:07, Simona Vetter wrote:
On Fri, Nov 08, 2024 at 09:18:53AM -0700, Shuah Khan wrote:
The Code of Conduct committee's goal first and foremost is to bring about
change
The I2C driver gets an interrupt upon transfer completion.
For multiple messages in a single transfer, N interrupts will be
received for N messages, leading to significant software interrupt
latency. To mitigate this latency, utilize Block Event Interrupt (BEI)
only when an interrupt is necessary.
GSI hardware generates an interrupt for each transfer completion.
For multiple messages within a single transfer, this results
in receiving N interrupts for N messages, which can introduce
significant software interrupt latency. To mitigate this latency,
utilize Block Event Interrupt (BEI) only whe
I2C_QCOM_GENI is having compile dependencies on QCOM_GPI_DMA and
so update I2C_QCOM_GENI to depends on QCOM_GPI_DMA.
Signed-off-by: Jyothi Kumar Seerapu
---
v1 -> v2:
This patch is added in v2 to address the kernel test robot
reported compilation error.
ERROR: modpost: "
The I2C driver gets an interrupt upon transfer completion.
For multiple messages in a single transfer, N interrupts will be
received for N messages, leading to significant software interrupt
latency. To mitigate this latency, utilize Block Event Interrupt (BEI)
only when an interrupt is necessary.
Le 11/11/2024 à 14:46, Murad Masimov a écrit :
If the value of the clock variable is higher than 80, the value of the
variable m, which is used as a divisor, will remain zero, because
(clock * testp) will be higher than vcomax in every loop iteration, which
leads to skipping every iteration a
When memory stats is generated fresh everytime by going though all the
BOs, their active information is quite easy to get. But if the stats are
tracked alongside BO's state changes this becomes harder since the job
scheduling part doesn't really deal with individual buffers.
Make drm-active- optio
On 11/11/24 04:06, Dan Carpenter wrote:
> We added some locking to this function, but accidentally forgot to unlock
> if zynqmp_dp_mode_configure() failed. Use a guard lock to fix it.
>
> Fixes: a7d5eeaa57d7 ("drm: zynqmp_dp: Add locking")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/
Use the pitch and size values stored in the args parameter for
allocating a dumb buffer in drm_gem_dma_dumb_create(). The values
come from drm_mode_create_dumb(). Align the pitch to a multiple
of 8.
Push the current calculation into the only direct caller imx. Imx's
hardware requires the framebuff
The ioctls MODE_CREATE_DUMB and MODE_MAP_DUMB return results into a
memory buffer supplied by user space. On errors, it is possible that
intermediate values are being returned. The exact semantics depends
on the DRM driver's implementation of these ioctls. Although this is
most-likely not a securit
Use the pitch and size values stored in the args parameter for
allocating a dumb buffer in drm_gem_vram_dumb_create(). Inline
the relevant code from drm_gem_vram_fill_create_dumb(), but
without the size computation. This value comes from
drm_mode_create_dumb(). Align the pitch to a multiple of 8.
Calculate the dumb-buffer scanline pitch with existing 4CC format
helpers and provide results to drivers. Fixes the overflow and size
tests. Drivers can further reuse the computed values.
The dumb-buffer overflow tests round up any given bits-per-pixel
value to a multiple of 8. So even one-bit for
Dumb-buffer pitch and size is specified by width, height, bits-per-pixel
plus various hardware-specific alignments. The calculation of these
values is inconsistent and duplicated among drivers. The results for
formats with bpp < 8 are incorrect.
This series begins to fix this. Default scanline pit
Use the pitch and size values stored in the args parameter for
allocating a dumb buffer in drm_gem_shmem_dumb_create(). The values
come from drm_mode_create_dumb(). Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 16 +-
On Fri, Oct 18, 2024 at 6:00 AM Dmitry Baryshkov
wrote:
>
> On Wed, Oct 09, 2024 at 08:02:01PM +0530, Mahadevan wrote:
> > Document the MDSS hardware found on the Qualcomm SA8775P platform.
> >
> > Reviewed-by: Krzysztof Kozlowski
> > Signed-off-by: Mahadevan
> > ---
> > .../bindings/display/ms
On Mon, 11 Nov 2024 at 19:06, Rob Herring wrote:
>
> On Fri, Oct 18, 2024 at 6:00 AM Dmitry Baryshkov
> wrote:
> >
> > On Wed, Oct 09, 2024 at 08:02:01PM +0530, Mahadevan wrote:
> > > Document the MDSS hardware found on the Qualcomm SA8775P platform.
> > >
> > > Reviewed-by: Krzysztof Kozlowski
> On Nov 11, 2024, at 10:20 AM, yangerkun wrote:
>
>
>
> 在 2024/11/11 22:39, Chuck Lever III 写道:
>>> On Nov 10, 2024, at 9:36 PM, Yu Kuai wrote:
>>>
>>> Hi,
>>>
>>> 在 2024/11/11 8:52, c...@kernel.org 写道:
From: yangerkun
[ Upstream commit 64a7ce76fb901bf9f9c36cf5d681328fc0fd4b5a
Am 11.11.24 um 15:00 schrieb Joonas Lahtinen:
Quoting Christian König (2024-11-11 13:34:12)
Am 11.11.24 um 11:10 schrieb Simona Vetter:
On Mon, Nov 11, 2024 at 10:00:17AM +0200, Joonas Lahtinen wrote:
Back from some time off and will try to answer below.
Adding Dave and Sima as this topic has
If the value of the clock variable is higher than 80, the value of the
variable m, which is used as a divisor, will remain zero, because
(clock * testp) will be higher than vcomax in every loop iteration, which
leads to skipping every iteration and leaving variable m unmodified.
Clamp value of
On Fri, 08 Nov 2024 08:30:44 +, Daniel Thompson wrote:
> Going forward, I'll be using my kernel.org address for upstream work.
>
>
Applied, thanks!
[1/2] MAINTAINERS: Use Daniel Thompson's korg address for backlight work
commit: 3adec6f907b698b32ab62f70da31b41abed00c59
--
Lee Jones [
422b750038123334f6ecc2
change-id: 2024-uninitializedpointer1601557-9803b725b6bd
Best regards,
--
Karan Sanghavi
Sorry, just noticed that I miss merged one line. Please ignore this V8
set. I will send out V9 instead.
Lizhi
On 11/11/24 09:32, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Uni
AMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator
integrated into AMD client APU. NPU enables efficient execution of Machine
Learning applications like CNN, LLM, etc. NPU is based on AMD XDNA
Architecture. NPU is managed by amdxdna driver.
Co-developed-by: Sonal Santan
Sig
Add interfaces for user application to submit command and wait for its
completion.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_ctx.c | 607 +-
drivers/accel/amdxdna/aie2_message.c | 343 ++
When there is a hardware error, the NPU firmware notifies the host through
a mailbox message. The message includes details of the error, such as the
tile and column indexes where the error occurred.
The driver starts a thread to handle the NPU error message. The thread
stops the clients which are
AMD AI Engine forms the core of AMD NPU and can be used for accelerating
machine learning applications.
Add the driver to support AI Engine integrated to AMD CPU.
Only very basic functionalities are added.
- module and PCI device initialization
- firmware load
- power up
- low level hardwa
The hardware can be shared among multiple user applications. The
hardware resources are allocated/freed based on the request from
user application via driver IOCTLs.
DRM_IOCTL_AMDXDNA_CREATE_HWCTX
Allocate tile columns and create a hardware context structure to track the
usage and status of the re
Add GET_INFO ioctl to retrieve hardware information, including
AIE, clock, hardware context etc.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_message.c| 65 +++
drivers/accel/amdxdna/aie2_pci.c
The AI Engine consists of 2D array of tiles arranged as columns. Provides
the basic column allocation and release functions for the tile columns.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/Makefile | 1
There different types of BOs are supported:
- shmem
A user application uses shmem BOs as input/output for its workload running
on NPU.
- device memory heap
The fixed size buffer dedicated to the device.
- device buffer
The buffer object allocated from device memory heap.
- command buffer
The bu
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference accelerator integrated
into AMD client CPUs. NPU enables efficient execution of Machine Learning
applications like CNNs, LLMs, etc
Implement PCI power management suspend and resume callbacks.
Co-developed-by: Narendra Gutta
Signed-off-by: Narendra Gutta
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
---
drivers
On 10/11/2024 15:41, Yunxiang Li wrote:
Make drm-active- optional just like drm-resident- and drm-purgeable-.
As Jani has already commented the commit message needs some work.
Signed-off-by: Yunxiang Li
CC: dri-devel@lists.freedesktop.org
CC: intel-...@lists.freedesktop.org
CC: amd-...@lis
Hi Jonas,
Am 11.11.24 um 09:00 schrieb Joonas Lahtinen:
Back from some time off and will try to answer below.
welcome back, good to have the designer of this at hand.
Adding Dave and Sima as this topic has been previously discussed to some
extent and will be good to reach common understandin
> -Original Message-
> From: Usyskin, Alexander
> Sent: Sunday, November 10, 2024 3:17 PM
> To: Vivi, Rodrigo
> Cc: Gupta, Anshuman ; Deak, Imre
> ; Miquel Raynal ;
> Richard Weinberger ; Vignesh Raghavendra
> ; De Marchi, Lucas ; Thomas
> Hellström ; Maarten Lankhorst
> ; Maxime Ripard ;
On 11/11/2024 09:26, Akash Goel wrote:
> This commit fixes the handling of partial GPU mapping of buffer objects
> in Panthor.
> VM_BIND ioctl allows Userspace to partially map the BOs to GPU.
> To map a BO, Panthor walks through the sg_table to retrieve the physical
> address of pages. If the mapp
[CCing a few more lists]
On 21.10.24 15:03, Nuno Gonçalves wrote:
>
> Since 5ab91447aa13b8b98bc11f5326f33500b0ee2c48 and still happening in
> master, I often get a kernel crash, either a "Unable to handle kernel
> NULL pointer dereference at virtual address" or "Unable to handle
> kernel paging r
On Mon, Nov 11, 2024 at 09:26:21AM +, Akash Goel wrote:
> This commit fixes the handling of partial GPU mapping of buffer objects
> in Panthor.
> VM_BIND ioctl allows Userspace to partially map the BOs to GPU.
> To map a BO, Panthor walks through the sg_table to retrieve the physical
> address
Hi
Am 08.11.24 um 09:10 schrieb Jocelyn Falempe:
Add a module parameter, to increase the font size for HiDPI screen.
Even with CONFIG_FONT_TER16x32, it can still be a bit small to read.
In this case, adding drm_log.scale=2 to your kernel command line will
double the character size.
Can't we h
Commit dbbfaf5f2641a ("drm: Remove bridge support from legacy helpers")
removes the drm_bridge_mode_fixup() call in drm_crtc_helper_set_mode(),
which makes the subsequent "encoder_funcs = encoder->helper_private" be
redundant, so remove it.
Cc: sta...@vger.kernel.org
Fixes: dbbfaf5f2641a ("drm: Re
Hi
Am 11.11.24 um 12:51 schrieb Thorsten Leemhuis:
[CCing a few more lists]
On 21.10.24 15:03, Nuno Gonçalves wrote:
Since 5ab91447aa13b8b98bc11f5326f33500b0ee2c48 and still happening in
master, I often get a kernel crash, either a "Unable to handle kernel
NULL pointer dereference at virtual
Hello,
syzbot found the following issue on:
HEAD commit:6efbea77b390 Merge tag 'arm64-fixes' of git://git.kernel.o..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=144e8c5f98
kernel config: https://syzkaller.appspot.com/x/.config?x=4c9b3fd66df7ebb7
das
On Mon, 11 Nov 2024 at 10:38, syzbot
wrote:
>
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:6efbea77b390 Merge tag 'arm64-fixes' of git://git.kernel.o..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=144e8c5f98
> kernel config: h
On Sun, 10 Nov 2024, Yunxiang Li wrote:
> Make drm-active- optional just like drm-resident- and drm-purgeable-.
Why? What does it mean?
This is what the commit message should answer.
>
> Signed-off-by: Yunxiang Li
> CC: dri-devel@lists.freedesktop.org
> CC: intel-...@lists.freedesktop.org
> CC
Den 2024-10-23 kl. 17:26, skrev Waiman Long:
On 10/23/24 3:52 AM, Maarten Lankhorst wrote:
The initial version was based roughly on the rdma and misc cgroup
controllers, with a lot of the accounting code borrowed from rdma.
The current version is a complete rewrite with page counter; it uses
This commit fixes the handling of partial GPU mapping of buffer objects
in Panthor.
VM_BIND ioctl allows Userspace to partially map the BOs to GPU.
To map a BO, Panthor walks through the sg_table to retrieve the physical
address of pages. If the mapping is created at an offset into the BO,
then the
We added some locking to this function, but accidentally forgot to unlock
if zynqmp_dp_mode_configure() failed. Use a guard lock to fix it.
Fixes: a7d5eeaa57d7 ("drm: zynqmp_dp: Add locking")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 3 +--
1 file changed, 1 insertion(
Am 11.11.24 um 11:10 schrieb Simona Vetter:
On Mon, Nov 11, 2024 at 10:00:17AM +0200, Joonas Lahtinen wrote:
Back from some time off and will try to answer below.
Adding Dave and Sima as this topic has been previously discussed to some
extent and will be good to reach common understanding about
On 11/8/24 06:26, Ryosuke Yasuoka wrote:
> +struct virtio_gpu_panic_object_array {
> + struct ww_acquire_ctx ticket;
> + struct list_head next;
> + u32 nents, total;
> + struct drm_gem_object *objs;
> +};
> +
> +static void *virtio_panic_buffer;
This won't work well if there is mor
Am 08.11.24 um 23:27 schrieb Matthew Brost:
On Tue, Sep 24, 2024 at 11:30:53AM +0200, Simona Vetter wrote:
Apologies for the late reply ...
Also late reply, just read this.
On Wed, Sep 04, 2024 at 01:34:18PM +0200, Christian König wrote:
Hi Boris,
Am 04.09.24 um 13:23 schrieb Boris Brezill
Hi
Am 08.11.24 um 09:10 schrieb Jocelyn Falempe:
Move the color conversions, blit and fill functions to drm_draw.c,
so that they can be re-used by drm_log.
drm_draw is internal to the drm subsystem, and shouldn't be used by
gpu drivers.
Just a remark on this patch: I don't like the proliferat
On Tue, Oct 29, 2024 at 10:15 PM Alex Deucher wrote:
>
> On Fri, Oct 25, 2024 at 2:03 AM Qiang Yu wrote:
> >
> > From: Qiang Yu
> >
> > This is used when radeonsi export small texture's modifier
> > to user with eglExportDMABUFImageQueryMESA().
> >
> > mesa changes is available here:
> > https:/
On 06/11/24 09:16, Maíra Canal wrote:
When the new register addresses were introduced for V3D 7.x, we added
new masks for performance counter sources on V3D 7.x. Nevertheless,
we never apply these new masks when setting the sources.
Fix the performance counter source settings on V3D 7.x by intr
This message reports a mismatch between new_crtc_state->enable and
has_connectors, which should be either both true or both false. However it
does not mention which one is true and which is false, which can be useful
for debugging. Add the value of both avriables to the log message.
Reviewed-by: D
Remove unintended extra word.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Luca Ceresoli
---
include/drm/drm_mode_object.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
index
08d7a7f0188fea79e2d8ad5ee6cc5044300
Add a wrapper to kref_read() just like the ones already in place for
kref_get() and kref_put(). This will be used for sanity checks on object
lifetime.
Signed-off-by: Luca Ceresoli
---
Changed in v3:
* use conventions for 'Returns' doc syntax
* ditch DRM_DEBUG() and as a consequence rework a
Calling drm_connector_cleanup() should only be done via the free_cb =>
.destroy path, which cleans up the struct drm_connector only when the
refcount drops to zero.
A cleanup done with a refcount higher than 0 can result from buggy code,
e.g. by doing cleanup directly in the drivers teardown code.
This series brings small improvements to the DRM documentation, logging and
a warning on an incorrect code path.
Signed-off-by: Luca Ceresoli
---
Changes in v3:
- patch 3: various fixes suggested by Jani Nikula and kernel test robot
- Updated reviewed-by tags
- Link to v2:
https://lore.kernel.or
On Mon, Nov 11, 2024 at 1:22 PM Thomas Zimmermann wrote:
> The patch in question changes the whole memory management of the
> affected code. It's also noteworthy that most of it has been reworked
> for the upcoming v6.12. Maybe this already fixed the problem. Kernel
> v6.11-rc7 added commit 5a498d
This commit fixes the bug in the handling of partial mapping of the
buffer objects to the GPU, which caused kernel warnings.
Panthor didn't correctly handle the case where the partial mapping
spanned multiple scatterlists and the mapping offset didn't point
to the 1st page of starting scatterlist.
Am 09.11.24 um 18:29 schrieb Matthew Brost:
The motivation for this series comes from pending UMD submission work by
AMD [1], ARM [3], and the Xe team, who are also beginning to look at
this. Sima has suggested [4] some common driver preemptive fences and
semantics, which we all agree on. This is
If the value of the clock variable is higher than 80, the value of the
variable m, which is used as a divisor, will remain zero, because
(clock * testp) will be higher than vcomax in every loop iteration, which
leads to skipping every iteration and leaving variable m unmodified.
Clamp value of
Hi Jason and David,
On Fri, 8 Nov 2024 at 19:33, David Hildenbrand wrote:
>
> On 08.11.24 18:05, Jason Gunthorpe wrote:
> > On Fri, Nov 08, 2024 at 04:20:30PM +, Fuad Tabba wrote:
> >> Some folios, such as hugetlb folios and zone device folios,
> >> require special handling when the folio's r
Back from some time off and will try to answer below.
Adding Dave and Sima as this topic has been previously discussed to some
extent and will be good to reach common understanding about what the
series is trying to do and what is the difference to the AMD debugging
model.
Quoting Christian König
On Mon, Nov 11, 2024 at 10:00:17AM +0200, Joonas Lahtinen wrote:
> Back from some time off and will try to answer below.
>
> Adding Dave and Sima as this topic has been previously discussed to some
> extent and will be good to reach common understanding about what the
> series is trying to do and
The hardware mailboxes are used by the driver to submit requests to
firmware and receive the completion notices from hardware.
Initially, a management mailbox channel is up and running. The driver may
request firmware to create/destroy more channels dynamically through
management channel.
Add dri
On Mon, Nov 11, 2024, 14:37 Thomas Zimmermann wrote:
> Hi
>
>
> Am 11.11.24 um 14:42 schrieb Nuno Gonçalves:
> > On Mon, Nov 11, 2024 at 1:22 PM Thomas Zimmermann
> wrote:
> >> The patch in question changes the whole memory management of the
> >> affected code. It's also noteworthy that most of
Am 11.11.24 um 15:38 schrieb Thomas Hellström:
On Fri, 2024-11-08 at 15:32 +0100, Christian König wrote:
Am 16.10.24 um 10:55 schrieb Thomas Hellström:
Initially intended for experimenting with different backup
solutions (shmem vs direct swap cache insertion), abstract
the backup destination us
On Sun, 10 Nov 2024 09:33:39 -0800, Bjorn Andersson wrote:
> Support for per-page tables requires the SMMU aparture to be setup, on
> some targets this is done statically in firmware, on others it's
> expected to be requested in runtime by the driver, through a SCM call.
>
> Marking the series a
Panels using a PWM-controlled backlight source do not have a standard
way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI through driver-specific tables.
The built-in ranges are not necessarily correct, or may grow stale if an
older device can be retrofitted with newer p
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Introduce a quirk to override "min_input_signal" to "0" which leads to a
much lower minimum brightness, which is still readable even in daylight.
One solution
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