Am 18.10.24 um 15:33 schrieb Yunxiang Li:
The old behavior reports the resident memory usage for this key and the
documentation say so as well. However this was accidentally changed to
include buffers that was evicted.
Fixes: a2529f67e2ed ("drm/amdgpu: Use drm_print_memory_stats helper from
fdi
Hi Doug,
On Tue, Oct 22, 2024 at 2:28 AM Doug Anderson wrote:
> On Mon, Oct 21, 2024 at 1:48 AM Geert Uytterhoeven
> wrote:
> > On Mon, Oct 21, 2024 at 10:23 AM Geert Uytterhoeven
> > wrote:
> > > On Mon, Oct 21, 2024 at 9:27 AM Greg KH
> > > wrote:
> > > > On Mon, Oct 21, 2024 at 08:58:30AM
On 10/20/24 17:41, Christian Gmeiner wrote:
From: Christian Gmeiner
This patch adds a new ioctl, DRM_IOCTL_V3D_PERFMON_SET_GLOBAL, which
allows the configuration of a global performance monitor (perfmon).
The global perfmon is used for all jobs, ensuring consistent performance
tracking across s
On Fri, Oct 18, 2024 at 02:46:31PM -0500, Lucas De Marchi wrote:
> I will give this a try with i915 and/or xe.
Less horrible version here:
git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git
perf/pmu-unregister
I've just pushed it out to the robots, but it builds, passes perf test
On 22/10/2024 22:10, Alex Deucher wrote:
On Fri, Oct 4, 2024 at 5:09 AM Jocelyn Falempe wrote:
Add support for the drm_panic module, which displays a pretty user
friendly message on the screen when a Linux kernel panic occurs.
It should work on all readeon using amdgpu_dm_plane.c, when the
On 2024-10-22 09:16, Bjorn Helgaas wrote:
> On Sun, Oct 20, 2024 at 10:21:29PM -0700, Vivek Kasireddy wrote:
>> Functions of the same PCI device (such as a PF and a VF) share the
>> same bus and have a common root port and typically, the PF provisions
>> resources for the VF. Therefore, they can
On Mon, Oct 14, 2024 at 07:55:36PM +, Matthew Brost wrote:
> On Mon, Oct 14, 2024 at 07:32:24PM +0200, Michal Wajdeczko wrote:
> >
> >
> > On 13.10.2024 19:30, Matthew Brost wrote:
> > > On Sun, Oct 13, 2024 at 01:55:45PM +0200, Michal Wajdeczko wrote:
> > >>
> > >>
> > >> On 12.10.2024 03:50
Hi!
> > > > - interface for setting multiple LEDs at once
> > > > - interface for setting a range of LEDs at once
> > How are LEDs ordered? I don't believe range makes much sense.
>
> Range would allow for efficiently changing the color of all LEDs. But i agree
> that this can be considered optio
On Fri, Oct 4, 2024 at 5:09 AM Jocelyn Falempe wrote:
>
> Add support for the drm_panic module, which displays a pretty user
> friendly message on the screen when a Linux kernel panic occurs.
>
> It should work on all readeon using amdgpu_dm_plane.c, when the
radeon
> framebuffer is linear (like
This initial part of the panel driver was mostly generated by the
"linux-mdss-dsi-panel-driver-generator" tool [1], reading downstream
Android kernel file "dsi_panel_S6E88A0_AMS427AP24_qhd_octa_video.dtsi" [2].
On top of the generic output of the tool, there were a couple of changes
applied:
- Add
The tables for brightness to candela, aid and elvss were taken from downstream
kernel file "dsi_panel_S6E88A0_AMS427AP24_qhd_octa_video.dtsi" [1][2][3].
The gamma table gets generated in "ss_dsi_smart_dimming_S6E88A0_AMS427AP24.c"
[4]
with hard-coded starting values. The function smart_dimming_in
The way of implementing a flip option follows the existing
panel-samsung-s6e8aa0.c [1][2][3].
The value to flip the screen is taken from a downstream kernel file of
a similar but older panel [4]. The mipi clock [5] for the new panel
samsung-s6e88a0-ams427ap24 matches 461 MHz and a hardware read-ou
Add bindings for Samsung AMS427AP24 panel with S6E88A0 controller.
Signed-off-by: Jakob Hauser
---
Patch is based on current branch drm-misc-next.
Changes in v2:
- Adapted property "flip-horizontal" to being moved to "panel-common.yaml".
---
.../panel/samsung,s6e88a0-ams427ap24.yaml | 65 +
The flip properties were used by "samsung,s6e8aa0.yaml" only so far. By
introducing "samsung,s6e88a0-ams427ap24.yaml" they become more common.
Signed-off-by: Jakob Hauser
---
Patch is based on current branch drm-misc-next.
---
.../bindings/display/panel/panel-common.yaml | 8
The patchset adds a new driver for Samsung AMS427AP24 panel with S6E88A0
controller. Patches are based on current branch drm-misc-next.
Changes in v2:
- Patch 1: New patch to move the bt-bindings properties "flip-horizontal"
and "flip-vertical" to "panel-common.yaml". File "samsung,s6e8aa0.yam
From: "Dr. David Alan Gilbert"
drm_client_framebuffer_flush() was explicitly added in 2020
by
commit c9c03e3cf072 ("drm/client: Add drm_client_framebuffer_flush()")
but has never been used.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/drm_client.c | 33
From: "Dr. David Alan Gilbert"
Hi,
This is a bunch of deadcode removals; they're all whole
function removals, no changing actual code or behaviour.
Note the last 3 delete functions that were each added (long ago)
by patches that explicitly added that individual function, but then
neve used the
From: "Dr. David Alan Gilbert"
drm_crtc_vblank_count_and_time() was explicitly added by
commit cf6483050e9b ("drm/irq: Add drm_crtc_vblank_count_and_time()")
in 2015, but never used.
Remove it, and rework comments that reference it.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/dr
From: "Dr. David Alan Gilbert"
drm_client_modeset_check() was explicitly added in 2020 by
commit 64593f2a6fc9 ("drm/client: Add drm_client_modeset_check()")
but has never been used.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/drm_client_modeset.c | 24
From: "Dr. David Alan Gilbert"
The last use of drm_atomic_helper_commit_planes_on_crtc() was removed
in 2018 by
commit 6c246b81f938 ("drm/i915: Replace call to commit_planes_on_crtc with
internal update, v2.")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/drm_atomic_hel
From: "Dr. David Alan Gilbert"
drm_class_device_register() and drm_class_device_unregister() have been
unused since
commit ed89fff97382 ("drm/ttm: drop sysfs directory")
Remove them.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/drm_sysfs.c | 32
i
Am 22.10.24 um 18:18 schrieb Chia-I Wu:
Userspace might poll a syncobj with the query ioctl. Call
dma_fence_enable_sw_signaling to ensure dma_fence_is_signaled returns
true in finite time.
Wait a second, just querying the fence status is absolutely not
guaranteed to return true in finite time
[Public]
I suppose we could add a field like amd-memory-private: to cover the private
placements. When would a BO not have a placement, is it when it is being moved?
Since we are tracking the state changes, I wonder if such situations can be
avoided now so whenever we call these stat update fun
On 10/22/24 00:09, Dmitry Baryshkov wrote:
> On Mon, 21 Oct 2024 at 20:07, Aradhya Bhatia wrote:
>>
>> Hi Dmitry,
>>
>> Thank you for reviewing the patches!
>>
>> On 10/20/24 17:27, Dmitry Baryshkov wrote:
>>> On Sun, Oct 20, 2024 at 01:35:30AM +0530, Aradhya Bhatia wrote:
From: Aradhya Bh
On Tue, Oct 22, 2024 at 9:53 AM Christian König
wrote:
>
> Am 22.10.24 um 18:18 schrieb Chia-I Wu:
> > Userspace might poll a syncobj with the query ioctl. Call
> > dma_fence_enable_sw_signaling to ensure dma_fence_is_signaled returns
> > true in finite time.
>
> Wait a second, just querying the
On 22/10/24 11:55, Devarsh Thakkar wrote:
> Hi Aradhya,
>
> Thanks for the patch.
>
> On 20/10/24 01:24, Aradhya Bhatia wrote:
>> From: Aradhya Bhatia
>
> [...]
>
>> +/*
>> + * Now that the DSI Link and DSI Phy are initialized,
>> + * wait for the CLK and Data Lanes to be ready.
On 10/22/24 8:13 AM, Liu Ying wrote:
[...]
This patch would cause the below in-flight LDB bridge driver
patch[1] fail to do display mode validation upon display modes
read from LVDS to HDMI converter IT6263's DDC I2C bus.
Why ?
Mode validation is affected only for dual LVDS link mode.
For s
On 10/22/24 7:59 AM, Liu Ying wrote:
[...]
Anyway, I don't think it is necessary to manage the clk_set_rate()
function calls between this driver and mxsfb_kms or lcdif_kms
because "video_pll1" clock rate is supposed to be assigned in DT...
I disagree with this part. I believe the assignment o
On Tue, 22 Oct 2024 at 15:24, Yongbang Shi wrote:
On Mon, Sep 30, 2024 at 06:06:10PM +0800, shiyongbang wrote:
From: baihan li
To support DP interface displaying in hibmc driver. Add
a encoder and connector for DP modual.
Signed-off-by: baihan li
---
drivers/gpu/drm/hisilicon/hibmc/Mak
Quoting Dmitry Baryshkov (2024-09-20 02:38:53)
> On Sat, Aug 31, 2024 at 09:06:53PM GMT, Stephen Boyd wrote:
>
> Based on our disccusions at LPC, here are several DT examples that seem
> sensible to implement this case and several related cases from other
> ChromeBooks.
(Apologies for getting back
On Tue, Oct 22, 2024 at 12:51 AM Tomi Valkeinen
wrote:
>
> Hi,
>
> On 22/10/2024 02:29, Saravana Kannan wrote:
> > Hi Tomi,
> >
> > Sorry it took a while to get back.
> >
> > On Mon, Sep 16, 2024 at 4:52 AM Tomi Valkeinen
> > wrote:
> >>
> >> Hi,
> >>
> >> We have an issue where two devices have
Hi,
Le mardi 22 octobre 2024 à 09:19 -0700, John Stultz a écrit :
> On Tue, Oct 22, 2024 at 1:38 AM Maxime Ripard wrote:
> >
> > I wanted to follow-up on the discussion we had at Plumbers with John and
> > T.J. about (among other things) adding new heaps to the kernel.
> >
> > I'm still interes
On Tue, Oct 22, 2024 at 09:43:35AM +0100, Matthew Auld wrote:
> On 21/10/2024 22:18, Matthew Brost wrote:
> > Don't open code vmap of a BO, use ttm_bo_access helper which is safe for
> > non-contiguous BOs and non-visible BOs.
> >
> > Suggested-by: Matthew Auld
> > Signed-off-by: Matthew Brost
>
Am 22.10.24 um 18:46 schrieb Li, Yunxiang (Teddy):
[Public]
I suppose we could add a field like amd-memory-private: to cover the private
placements.
No, that is not really appropriate either. GWS, GDS and OA are not
memory in the first place.
Those BOs are HW blocks which the driver alloca
On Tue, Oct 22, 2024 at 04:19:18PM +0200, Philipp Stanner wrote:
> On Mon, 2024-10-21 at 10:57 -0700, Matthew Brost wrote:
> > DRM scheduler work queues are used to submit jobs, jobs are in the
> > path
>
> "scheduler work queues" is very generic, how about
> "drm_gpu_scheduler.submit_wq is used t
Am 22.10.24 um 11:47 schrieb Pavel Machek:
Hi!
Sorry for taking a bit long to respond.
This "illumination" subsystem would (from my perspective) act like some sort of
LED subsystem
for devices with a high count of LEDs, like some RGB keyboards.
This would allow us too:
- provide an abstract
[Public]
> >
> > +static uint32_t fold_memtype(uint32_t memtype) {
>
> In general please add prefixes to even static functions, e.g. amdgpu_vm_ or
> amdgpu_bo_.
>
> > + /* Squash private placements into 'cpu' to keep the legacy userspace
> > view.
> */
> > + switch (mem_type) {
> > + case T
On 22/10/2024 15:55, Thomas Zimmermann wrote:
Hi
Am 22.10.24 um 15:31 schrieb Jon Hunter:
Hi Thomas,
On 12/03/2024 15:45, Thomas Zimmermann wrote:
Only TTM-based drivers use fbdev-generic. Rename it to fbdev-ttm and
change the symbol infix from _generic_ to _ttm_. Link the source file
into
Hi,
Gentle ping to land the fix for the kernel crash.
If faster, I can send a new version increasing max surfaces to 4 as
previously discussed.
There are now two bug reports for the same issue:
- https://gitlab.freedesktop.org/drm/amd/-/issues/3693
- https://gitlab.freedesktop.org/drm/amd/-/is
On Tue, Oct 22, 2024 at 1:38 AM Maxime Ripard wrote:
>
> I wanted to follow-up on the discussion we had at Plumbers with John and
> T.J. about (among other things) adding new heaps to the kernel.
>
> I'm still interested in merging a carve-out driver[1], since it seems to be
> in every vendor BSP
Userspace might poll a syncobj with the query ioctl. Call
dma_fence_enable_sw_signaling to ensure dma_fence_is_signaled returns
true in finite time.
Fixes: 27b575a9aa2f ("drm/syncobj: add timeline payload query ioctl v6")
Signed-off-by: Chia-I Wu
---
v2: add Signed-off-by and Fixes tags
---
d
On Tue, Oct 22, 2024 at 3:30 AM Boris Brezillon
wrote:
>
> On Thu, 17 Oct 2024 09:20:53 -0700
> Chia-I Wu wrote:
>
> > Userspace might poll a syncobj with the query ioctl. Call
> > dma_fence_enable_sw_signaling to ensure dma_fence_is_signaled returns
> > true in finite time.
> >
> > ---
> >
> >
[AMD Official Use Only - AMD Internal Distribution Only]
It sounds like it makes the most sense to ignore the BOs that have no placement
or private placements then, it would simplify the code too.
Teddy
Hello,
On Thu, Sep 26, 2024 at 04:12:46PM +0200, Francesco Dolcini wrote:
> From: Francesco Dolcini
>
> Wait for the command transmission to be completed in the DSI transfer
> function polling for the dc_start bit to go back to idle state after the
> transmission is started.
>
> This is documen
Am 22.10.24 um 17:17 schrieb Li, Yunxiang (Teddy):
[Public]
+static uint32_t fold_memtype(uint32_t memtype) {
In general please add prefixes to even static functions, e.g. amdgpu_vm_ or
amdgpu_bo_.
+ /* Squash private placements into 'cpu' to keep the legacy userspace view.
*/
+ switch
Add support for ABGR2101010, used by the nouveau driver.
Signed-off-by: Jocelyn Falempe
Reviewed-by: Javier Martinez Canillas
---
drivers/gpu/drm/drm_panic.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/drm_panic.c b/drivers/gpu/drm/drm_panic.c
index 74412b7bf
Refactor, and move the tiling geometry functions to dispnv50/tile.h,
so they can be re-used by drm_panic.
No functional impact.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/nouveau/dispnv50/tile.h | 63 +++
drivers/gpu/drm/nouveau/nouveau_display.c | 59 -
This series adds basic drm_panic support for nouveau.
I've tested on GTX1650 (Turing), GeForce GT 1030 (Pascal) and
Geforce 8800 GTS (Tesla), running Gnome/Wayland desktop, and in VT.
It should work on other nv50+ cards, but I didn't test them.
To test it, you need to build your kernel with CONFI
Add drm_panic support for nv50+ cards.
It's enough to get the panic screen while running Gnome/Wayland with
an nv50+ nvidia GPU.
It doesn't support multi-plane or compressed format yet.
Tiling is tested on GTX1650 (Turing), GeForce GT 1030 (Pascal) and
Geforce 8800 GTS (Tesla).
Signed-off-by: Joce
In intel-dg, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 199 +
Implement read(), erase() and write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Co-developed-by: Vitaly Lubart
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 199 ++
On Tue, Oct 22, 2024 at 02:13:57PM +0800, Liu Ying wrote:
> On 10/13/2024, Marek Vasut wrote:
> > On 10/11/24 8:18 AM, Liu Ying wrote:
> >> On 10/11/2024, Marek Vasut wrote:
> >>> On 10/10/24 7:22 AM, Liu Ying wrote:
> On 10/09/2024, Marek Vasut wrote:
> > The media_ldb_root_clk supply LDB
As per the RZ/G2UL hardware manual Table 33.4 Clock List, the maximum
dot clock for the DPI interface is 83.5 MHz. Add mode_valid callback
to reject modes greater than 83.5 MHz.
Suggested-by: Laurent Pinchart
Signed-off-by: Biju Das
---
Changes in v2:
* Moved .mode_valid from crtc to encoder as
The DPI_OE bit is removed from the latest RZ/G2UL and RZ/G2L hardware
manual. So, drop this macro.
Fixes: b330f1480172 ("drm: renesas: rz-du: Add RZ/G2UL DU Support")
Signed-off-by: Biju Das
---
v1->v2:
* Added Fixes tag.
---
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 8 +---
1 file ch
Add job that executes the IGT test suite for sm8350-hdk.
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vignesh Raman
---
v2:
- Add gitlab issue link for flake tests.
---
drivers/gpu/drm/ci/arm64.config | 7 +-
drivers/gpu/drm/ci/build.sh
Add jobs that execute the IGT test suite for sm8350-hdk and dedede.
Dropped the refactor software-driver stage jobs patch from this series.
I will send it as a separate patch.
Successful pipeline link,
https://gitlab.freedesktop.org/vigneshraman/linux/-/pipelines/1294877
Vignesh Raman (2):
drm
Hi!
> > Sorry for taking a bit long to respond.
> >
> > This "illumination" subsystem would (from my perspective) act like some
> > sort of LED subsystem
> > for devices with a high count of LEDs, like some RGB keyboards.
> >
> > This would allow us too:
> > - provide an abstract interface for
Add job that executes the IGT test suite for acer-cb317-1h-c3z6-dedede.
dedede boards use 64 bit Intel Jasper Lake processors.
Signed-off-by: Vignesh Raman
---
v2:
- Add gitlab issue link for flake tests.
---
drivers/gpu/drm/ci/test.yml | 9
drivers/gpu/drm/ci/xfails
Hi!
> > Personally I really like the idea to just emulate a HID LampArray device
> > for this instead or rolling our own API. I believe there need to be
> > strong arguments to go with some alternative NIH API and I have not
> > heard such arguments yet.
>
> Agreed on everything Hans said.
>
>
Register the on-die nvm device with the mtd subsystem.
Refcount nvm object on _get and _put mtd callbacks.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Enable runtime PM in mtd driver to notify graphics driver that
whole card should be kept awake while nvm operations are
performed through this driver.
CC: Lucas De Marchi
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 73 +-
1 file changed,
Enable access to internal non-volatile memory on DGFX
with GSC/CSC devices via a child device.
The nvm child device is exposed via auxiliary bus.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe
Enable access to internal non-volatile memory on
DGFX devices via a child device.
The nvm child device is exposed via auxiliary bus.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/Make
GSC NVM controller HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 35 ++
1 file changed, 35 insertions(+)
diff --git a/drivers/
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---
drivers/gpu/drm/xe/xe_nvm.c | 33 ++
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/intel_nvm.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
Add driver for access to Intel discrete graphics card
internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide mtd driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
and "spi: add driver for Intel d
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS| 7 ++
drivers/mtd/devices/Kconfig|
Create new dma_addr array for dmabuf
BOs associated with VFs
config: x86_64-allyesconfig
(https://download.01.org/0day-ci/archive/20241022/202410221832.r04dr21j-...@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project
3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce
Hi Thomas,
On 12/03/2024 15:45, Thomas Zimmermann wrote:
Only TTM-based drivers use fbdev-generic. Rename it to fbdev-ttm and
change the symbol infix from _generic_ to _ttm_. Link the source file
into TTM helpers, so that it is only build if TTM-based drivers have
been selected. Select DRM_TTM_H
On 2024/10/22 9:04 PM, Alex Deucher wrote:
External email: Use caution opening links or attachments
On Tue, Oct 22, 2024 at 2:31 AM Kai-Heng Feng wrote:
Hi Luke,
On 2024/10/15 4:04 PM, Luke Jones wrote:
On Mon, 14 Oct 2024, at 5:25 PM, Mario Limonciello wrote:
From: Mario Limonciello
On 2024/10/18 16:12, Jinjie Ruan wrote:
>
>
> On 2024/10/18 15:55, Maxime Ripard wrote:
>> Hi,
>>
>> On Thu, Oct 17, 2024 at 02:31:21PM GMT, Jinjie Ruan wrote:
>>> Fix some memory leaks in drm tests.
>>>
>>> Changes in v3:
>>> - Adjust drm/drm_edid.h header to drm_kunit_helpers.c.
>>> - Drop t
On 10/23/2024, Marek Vasut wrote:
> On 10/22/24 7:59 AM, Liu Ying wrote:
>
> [...]
>
Anyway, I don't think it is necessary to manage the clk_set_rate()
function calls between this driver and mxsfb_kms or lcdif_kms
because "video_pll1" clock rate is supposed to be assigned in DT...
On Tue, Oct 22, 2024 at 11:52:10PM +0200, Peter Zijlstra wrote:
On Fri, Oct 18, 2024 at 02:46:31PM -0500, Lucas De Marchi wrote:
I will give this a try with i915 and/or xe.
Less horrible version here:
git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git
perf/pmu-unregister
I've
On 10/23/2024, Marek Vasut wrote:
> On 10/22/24 8:13 AM, Liu Ying wrote:
>
> [...]
>
>> This patch would cause the below in-flight LDB bridge driver
>> patch[1] fail to do display mode validation upon display modes
>> read from LVDS to HDMI converter IT6263's DDC I2C bus.
>
>
Am 22.10.24 um 19:09 schrieb Li, Yunxiang (Teddy):
[AMD Official Use Only - AMD Internal Distribution Only]
It sounds like it makes the most sense to ignore the BOs that have no placement
or private placements then, it would simplify the code too.
Yeah, that works for me.
Regards,
Christian.
Hi
Am 22.10.24 um 17:36 schrieb Jon Hunter:
We'd turn a linker/modpost error into a compiler error. Likely makes
no difference. And AFAICT every driver that selects TTM also selects
TTM_HELPER. Drivers without TTM should not use this header.
Yes I also noted that all the current drivers se
Hi
Am 23.10.24 um 01:29 schrieb li...@treblig.org:
From: "Dr. David Alan Gilbert"
drm_client_framebuffer_flush() was explicitly added in 2020
by
commit c9c03e3cf072 ("drm/client: Add drm_client_framebuffer_flush()")
but has never been used.
Remove it.
I had a patchset to use this helper for
Hi Sakari, again
> > diff --git a/drivers/of/property.c b/drivers/of/property.c
> > index 11b922fde7af..6a5d27dd0c64 100644
> > --- a/drivers/of/property.c
> > +++ b/drivers/of/property.c
> > @@ -630,6 +630,43 @@ struct device_node *of_graph_get_port_by_id(struct
> > device_node *parent, u32 id
On 10/22/24 07:51, Kasireddy, Vivek wrote:
> Hi Dmitry,
>
>>
>> On 8/13/24 06:49, Vivek Kasireddy wrote:
>>> +long virtgpu_dma_buf_import_sgt(struct virtio_gpu_mem_entry **ents,
>>> + unsigned int *nents,
>>> + struct virtio_gpu_object *bo,
>>> +
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, September 26, 2024 3:44 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: Re: [PATCH 1/7] drm/i915/histogram: Define regist
On Tue, Oct 22, 2024 at 04:10:51PM +0800, Liu Ying wrote:
> Hi Maxime,
>
> On 10/22/2024, Maxime Ripard wrote:
> > On Tue, Oct 22, 2024 at 03:36:47PM +0800, Liu Ying wrote:
> >> Hi Maxime,
> >>
> >> On 10/21/2024, Maxime Ripard wrote:
> >>> On Mon, Oct 21, 2024 at 02:44:43PM +0800, Liu Ying wrote:
On Thu, 17 Oct 2024 12:38:06 +0200, AngeloGioacchino Del Regno wrote:
> Changes in v13:
> - Added comment in commit description of patch [1/3] to warn about
>new port scheme.
> - The series is now fully reviewed, tested, hence *ready*.
>
> Changes in v12:
> - Added comment to describe graph
Create new dma_addr array for dmabuf
BOs associated with VFs
config: i386-buildonly-randconfig-003-20241022
(https://download.01.org/0day-ci/archive/20241022/202410221702.flgkndgm-...@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build):
(https://download.01.o
Hi, Jason:
Jason-JH.Lin 於 2024年10月9日 週三 上午11:46寫道：
>
> Some SoCs do not support the ignore_pixl_alpha flag, which breaks the
> XRGB format. Some SoCs do not support pre-multiplied pixel formats
> and extending configuration of OVL pre-multiplied color formats,
> such as MT8173.
>
> Fix the So
next-20241022]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Vivek-Kas
Hi, Hsin-te:
Hsin-Te Yuan 於 2024年10月16日 週三 下午10:17寫道：
>
> In commit 9f428b95ac89 ("drm/mediatek: Add new color format MACROs in
> OVL"), some new color formats are defined in the MACROs to make the
> switch statement more concise. That commit was intended to be a no-op
> cleanup. However, there a
On Tue, Oct 22, 2024 at 2:31 AM Kai-Heng Feng wrote:
>
> Hi Luke,
>
> On 2024/10/15 4:04 PM, Luke Jones wrote:
> > On Mon, 14 Oct 2024, at 5:25 PM, Mario Limonciello wrote:
> >> From: Mario Limonciello
> >>
> >> The ASUS GA605W has a NVIDIA PCI VGA device and an AMD PCI display device.
> >>
> >>
On Tue, Oct 22, 2024 at 09:46:24AM +, CK Hu (胡俊光) wrote:
> Hi, Ville:
>
> On Thu, 2024-10-03 at 14:18 +0300, Ville Syrjala wrote:
> >
> > External email : Please do not click links or open attachments until you
> > have verified the sender or the content.
> > From: Ville Syrjälä
> >
Hi Maxime,
On 10/21/2024, Maxime Ripard wrote:
> On Mon, Oct 21, 2024 at 02:44:43PM +0800, Liu Ying wrote:
>> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
>> + struct drm_bridge_state *bridge_state,
>> + struct
Am 18.10.24 um 15:33 schrieb Yunxiang Li:
Before, every time fdinfo is queried we try to lock all the BOs in the
VM and calculate memory usage from scratch. This works okay if the
fdinfo is rarely read and the VMs don't have a ton of BOs. If either of
these conditions is not true, we get a massiv
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