On 07/08/2024, Krzysztof Kozlowski wrote:
> On 08/07/2024 08:51, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Hi
Am 09.07.24 um 08:10 schrieb Aditya Garg:
Hi Thomas
I found upstreamed drivers which may be using this routine.
https://elixir.bootlin.com/linux/latest/A/ident/DRM_FORMAT_BGR888
These drivers support BGR888 in hardware. They don't convert pixel
format on the fly.
I guess the same log
Hi
Am 08.07.24 um 10:37 schrieb Aditya Garg:
On 8 Jul 2024, at 1:59 PM, Thomas Zimmermann wrote:
Hi
Am 08.07.24 um 10:10 schrieb Aditya Garg:
Hi
I see. Best would be to submit this patch together with the driver for review.
Although it’s your take, but I really doubt whether the driver
@Bjorn, @Krzysztof
On Mon, 2024-07-08 at 21:46 +, Ashish Kalra wrote:
> With this patch applied, we are observing unloading and then
> reloading issues with the AMD Crypto (CCP) driver:
Thank you very much for digging into this, Ashish
Could you give me some pointers how one could test CCP b
On 2024/6/12 21:52, Tomeu Vizoso wrote:
This initial version supports the NPU as shipped in the RK3588 SoC and
described in the first part of its TRM, in Chapter 36.
This NPU contains 3 independent cores that the driver can submit jobs
to.
This commit adds just hardware initialization and power
Hi Thomas
I found upstreamed drivers which may be using this routine.
https://elixir.bootlin.com/linux/latest/A/ident/DRM_FORMAT_BGR888
I guess the same logic was used to upstream all these:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/drm_format_hel
Hi Felix,
Thank you for your email. It has been received and a member of the team will
be in contact as soon as possible. We are usually able to respond to queries
within 1-2 working days.
(If not already given, please let us know your full name, order number, and
purchase date to aid us in
Modules that load firmware from various paths at runtime must declare
those paths at compile time, via the MODULE_FIRMWARE macro, so that the
firmware paths are included in the module's metadata.
The accel/ivpu driver loads firmware but lacks this metadata,
preventing dracut from correctly locatin
On 07/09/2024, Rob Herring wrote:
> On Mon, Jul 08, 2024 at 02:30:37PM +0800, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified conc
On 08/07/2024 19:52, Douglas Anderson wrote:
Commit d7d473d8464e ("drm/panel: sharp-lq101r1sx01: Don't call disable
at shutdown/remove") had a subtle bug. We should be calling
sharp_panel_del() when the "sharp" variable is non-NULL, not when it's
NULL. Fix.
Fixes: d7d473d8464e ("drm/panel: sharp
Each plane has its own capability or interoperability based on the
harware restrictions. If this is exposed to the user, then user can read
it once on boot and store this. Later can be used as a lookup table to
check a corresponding capability is supported by plane then only go
ahead with the frame
On Tue, 02 Jul 2024 16:30:16 +0200, Sebastian Wick wrote:
> The initial idea of the Colorspace prop was that this maps 1:1 to
> InfoFrames/SDP but KMS does not give user space enough information nor
> control over the output format to figure out which variants can be used
> for a given KMS commit.
Hello Philipp,
On 7/9/2024 2:21 AM, Philipp Stanner wrote:
> @Bjorn, @Krzysztof
>
> On Mon, 2024-07-08 at 21:46 +, Ashish Kalra wrote:
>> With this patch applied, we are observing unloading and then
>> reloading issues with the AMD Crypto (CCP) driver:
> Thank you very much for digging into th
Hello Andy,
On 2024-07-08 09:46, Andy Yan wrote:
At 2024-07-04 18:35:42, "Dragan Simic" wrote:
On 2024-07-04 04:10, Andy Yan wrote:
At 2024-07-04 07:32:02, "Dragan Simic" wrote:
After the additional firmware-related module information was
introduced by
the commit c0677e41a47f ("drm/rockchip
https://bugzilla.kernel.org/show_bug.cgi?id=219007
The Linux kernel's regression tracker (Thorsten Leemhuis)
(regressi...@leemhuis.info) changed:
What|Removed |Added
C
https://bugzilla.kernel.org/show_bug.cgi?id=219007
--- Comment #3 from The Linux kernel's regression tracker (Thorsten Leemhuis)
(regressi...@leemhuis.info) ---
Forgot: I'll forward this report by mail, as it's a regression, so no need to
do anything for you. But it's not the first bug I see from
https://bugzilla.kernel.org/show_bug.cgi?id=219007
--- Comment #4 from The Linux kernel's regression tracker (Thorsten Leemhuis)
(regressi...@leemhuis.info) ---
And one more comment: could you please share a dmesg from the VM so we know
what drm driver is used.
--
You may reply to this email to
On 1/6/24 17:54, Christophe JAILLET wrote:
> If drm_dev_register() fails, a call to drv_load() must be undone, as
> already done in the remove function.
>
> Fixes: b759012c5fa7 ("drm/stm: Add STM32 LTDC driver")
> Signed-off-by: Christophe JAILLET
Hi Christophe,
After some delay: applied on d
Add a parameter to the blit function, to upscale the image.
This is necessary to draw QR-code, otherwise, the pixels are usually
too small to be readable by most QR-code reader.
It can also be used later for drawing fonts on high-DPI display.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/dr
Move logo rectangle initialisation, and logo drawing in separate
functions, so they can be re-used by different panic screens.
It prepares the introduction of the QR-code panic screen.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_panic.c | 57 +
1 fi
Check if two rectangles overlap.
It's a bit similar to drm_rect_intersect() but this won't modify
the rectangle.
Simplifies a bit drm_panic.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_panic.c | 3 +--
include/drm/drm_rect.h | 15 +++
2 files changed, 16 insertions(+
This patch adds a new panic screen, with a QR code and the kmsg data
embedded.
If DRM_PANIC_SCREEN_QR_CODE_URL is set, then the kmsg data will be
compressed with zlib and encoded as a numerical segment, and appended
to the url as a url parameter. This allows to save space, and put
about ~7500 bytes
This series adds a new panic screen, with the kmsg data embedded in a QR-code.
The main advantage of QR-code, is that you can copy/paste the debug data to a
bug report.
The QR-code encoder is written in rust, and is very specific to drm_panic.
The reason is that it is called in a panic handler,
>From c24bd5b66e798a341caf183fb7cdbdf235502d90 Mon Sep 17 00:00:00 2001
From: Philipp Stanner
Date: Tue, 9 Jul 2024 09:45:48 +0200
Subject: [PATCH] PCI: Fix pcim_intx() recursive calls
pci_intx() calls into pcim_intx() in managed mode, i.e., when
pcim_enable_device() had been called. This recursi
In cdv_intel_lvds_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_mode_duplicate(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: 6a227d5fd6c4 ("gma500: Add support for Cedarview")
Signed-off-b
On 03/07/2024 17:58, Yao Zi wrote:
Allocated canvases may not be released on the error exit path of
meson_drv_bind_master(), leading to resource leaking. Rewrite exit path
to release canvases on error.
Fixes: 2bf6b5b0e374 ("drm/meson: exclusively use the canvas provider module")
Signed-off-by: Y
To avoid reports of NULL_RETURN warning, we should add
otg_master NULL check.
Cc: sta...@vger.kernel.org
Fixes: c51d87202d1f ("drm/amd/display: do not attempt ODM power optimization if
minimal transition doesn't exist")
Signed-off-by: Ma Ke
---
Changes in v2:
- added the recipient's email addres
Hi Draqan,
At 2024-07-09 16:17:06, "Dragan Simic" wrote:
>Hello Andy,
>
>On 2024-07-08 09:46, Andy Yan wrote:
>> At 2024-07-04 18:35:42, "Dragan Simic" wrote:
>>> On 2024-07-04 04:10, Andy Yan wrote:
At 2024-07-04 07:32:02, "Dragan Simic" wrote:
> After the additional firmware-related
On Tue, Jul 09, 2024 at 10:40:10AM +0200, Jocelyn Falempe wrote:
> +config DRM_PANIC_SCREEN_QR_CODE_URL
> + string "Base url of the QR code in the panic screen"
> + depends on DRM_PANIC_SCREEN_QR_CODE
> + help
> + This option sets the base url to report the kernel panic. If it's s
On Tue, Jul 09, 2024 at 11:11:35AM +0200, Greg KH wrote:
> On Tue, Jul 09, 2024 at 10:40:10AM +0200, Jocelyn Falempe wrote:
> > +config DRM_PANIC_SCREEN_QR_CODE_URL
> > + string "Base url of the QR code in the panic screen"
> > + depends on DRM_PANIC_SCREEN_QR_CODE
> > + help
> > + This o
In psb_intel_lvds_get_modes(), the return value of drm_mode_duplicate() is
assigned to mode, which will lead to a possible NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: 89c78134cc54 ("gma500: Add Poulsbo support")
Signed-of
…
> Signed-off-by: Ma Ke
Are you going to adjust this information anyhow?
The usage of mailing list addresses is probably undesirable for
the Developer's Certificate of Origin, isn't it?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patc
In drm_client_modeset_probe(), the return value of drm_mode_duplicate() is
assigned to modeset->mode, which will lead to a possible NULL pointer
dereference on failure of drm_mode_duplicate(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: cf13909aee05 ("drm/fb-helper: Move out modese
--
发件人：Felix Kuehling
发送时间：2024年7月9日(星期二) 06:40
收件人：周春明(日月) ; Tvrtko Ursulin ;
dri-devel@lists.freedesktop.org ;
amd-...@lists.freedesktop.org ; Dave Airlie
; Daniel Vetter ; criu
抄 送："Errabolu, Ramesh" ; "Christian König"
主 题：R
On Mon, Jul 08, 2024 at 04:29:06PM -0400, Hamza Mahfooz wrote:
> We would like to be able to adjust the vblank off delay dynamically for
> a given CRTC. Since, it will allow drivers to apply static screen
> optimizations more quickly and consequently allow users to benefit more
> so from the power
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
> Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
> enable PSR more quickly for displays that support it.
>
> Signed-off-by: Hamza Mahfooz
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++-
Hi Jocelyn,
A quick docs-only review of the Rust side (some of these apply in
several cases -- I just wanted to give an overview for you to
consider).
On Tue, Jul 9, 2024 at 10:45 AM Jocelyn Falempe wrote:
>
> +//! This is a simple qr encoder for DRM panic.
> +//!
> +//! Due to the Panic constra
On Tue, Jul 9, 2024 at 10:45 AM Jocelyn Falempe wrote:
>
> This patch adds a new panic screen, with a QR code and the kmsg data
> embedded.
> If DRM_PANIC_SCREEN_QR_CODE_URL is set, then the kmsg data will be
> compressed with zlib and encoded as a numerical segment, and appended
> to the url as a
On 3.07.2024 7:57 AM, Amirreza Zarrabi wrote:
> Qualcomm TEE hosts Trusted Applications (TAs) and services that run in
> the secure world. Access to these resources is provided using MinkIPC.
> MinkIPC is a capability-based synchronous message passing facility. It
> allows code executing in one dom
On 09/07/2024 11:12, Greg KH wrote:
On Tue, Jul 09, 2024 at 11:11:35AM +0200, Greg KH wrote:
On Tue, Jul 09, 2024 at 10:40:10AM +0200, Jocelyn Falempe wrote:
+config DRM_PANIC_SCREEN_QR_CODE_URL
+ string "Base url of the QR code in the panic screen"
+ depends on DRM_PANIC_SCREEN_
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
> On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
> > Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
> > enable PSR more quickly for displays that support it.
> >
> > Signed-off-by: Hamza Mahfooz
>
Hi,
Just two more comments and we are good to go.
On 09.07.2024 02:25, Alexander F. Lent wrote:
> +/* Add module metadata for the production firmware paths.
> + * This needs to be kept in sync with fw_names above.
> + */
I would prefer:
/* Production fw_names from the table above */
> +MODULE_F
On 2024-07-09 11:10, Andy Yan wrote:
At 2024-07-09 16:17:06, "Dragan Simic" wrote:
On 2024-07-08 09:46, Andy Yan wrote:
At 2024-07-04 18:35:42, "Dragan Simic" wrote:
On 2024-07-04 04:10, Andy Yan wrote:
At 2024-07-04 07:32:02, "Dragan Simic" wrote:
After the additional firmware-related mo
On Tue, Jul 09, 2024 at 12:04:02PM +0200, Jocelyn Falempe wrote:
>
>
> On 09/07/2024 11:12, Greg KH wrote:
> > On Tue, Jul 09, 2024 at 11:11:35AM +0200, Greg KH wrote:
> > > On Tue, Jul 09, 2024 at 10:40:10AM +0200, Jocelyn Falempe wrote:
> > > > +config DRM_PANIC_SCREEN_QR_CODE_URL
> > > > +
On 30.06.2024 12:29 PM, Akhil P Oommen wrote:
> On Tue, Jun 25, 2024 at 08:28:09PM +0200, Konrad Dybcio wrote:
>> There is no need to reinvent the wheel for simple read-match-set logic.
>>
>> Make speedbin discovery and assignment generation independent.
>>
>> This implicitly removes the bogus 0x80
On 30.06.2024 12:25 PM, Akhil P Oommen wrote:
> On Tue, Jun 25, 2024 at 08:28:06PM +0200, Konrad Dybcio wrote:
>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>> abstracted through SMEM, instead of being directly available in a fuse.
>>
>> Add support for SMEM-based speed bin
Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore,
but instead rely on a set of combinations of "feature code" (FC) and
"product code" (PC) identifiers to match the bins. This series adds
support for that.
I suppose a qcom/for-soc immutable branch would be in order if we want
to
Add speebin data for A740, as found on SM8550 and derivative SoCs.
For non-development SoCs it seems that "everything except FC_AC, FC_AF
should be speedbin 1", but what the values are for said "everything" are
not known, so that's an exercise left to the user..
Reviewed-by: Dmitry Baryshkov
Sig
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.
Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that le
In preparation for commonizing the speedbin handling code.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a
There is no need to reinvent the wheel for simple read-match-set logic.
Make speedbin discovery and assignment generation independent.
This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
which has no representation in hardware whatshowever.
Signed-off-by: Konrad Dybcio
---
drive
Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.
Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
1 f
Hi Dragan，
At 2024-07-09 18:10:51, "Dragan Simic" wrote:
>On 2024-07-09 11:10, Andy Yan wrote:
>> At 2024-07-09 16:17:06, "Dragan Simic" wrote:
>>> On 2024-07-08 09:46, Andy Yan wrote:
At 2024-07-04 18:35:42, "Dragan Simic" wrote:
> On 2024-07-04 04:10, Andy Yan wrote:
>> At 2024-
Am 08.07.24 um 17:34 schrieb Matthew Brost:
On Mon, Jul 08, 2024 at 05:29:30PM +0200, Christian König wrote:
Am 08.07.24 um 17:23 schrieb Matthew Brost:
On Sun, Jul 07, 2024 at 05:49:16PM +0200, Thomas Hellström wrote:
Christian, Matthew,
I think I addressed all review comments and a couple o
On Tue, Jul 09, 2024 at 12:10:51PM GMT, Dragan Simic wrote:
> On 2024-07-09 11:10, Andy Yan wrote:
> > At 2024-07-09 16:17:06, "Dragan Simic" wrote:
> > > On 2024-07-08 09:46, Andy Yan wrote:
> > > > At 2024-07-04 18:35:42, "Dragan Simic" wrote:
> > > > > On 2024-07-04 04:10, Andy Yan wrote:
> >
if (IS_ERR(gpu->gpu_cx))
gpu->gpu_cx = NULL;
- gpu->pdev = pdev;
platform_set_drvdata(pdev, &gpu->adreno_smmu);
msm_devfreq_init(gpu);
---
base-commit: 0b58e108042b0ed28a71cd7edf517555b233
change-id: 20240709-topic-adreno_crash2-1c9fffd9bce8
Best regards,
--
Konrad Dybcio
On 7/9/24 5:50 AM, Doug Anderson wrote:
> Hi,
>
> On Fri, Jun 28, 2024 at 11:25 AM Tejas Vipin wrote:
>>
>> +/**
>> + * mipi_dsi_dcs_set_page_address_multi() - define the column extent of the
>> + * frame memory accessed by the host processor
>> + * @ctx: Context for multiple DSI transacti
6.9-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Hellström
commit d99fbd9aab624fc030934e21655389ab1765dc94 upstream.
Bos can be put with multiple unrelated dma-resv locks held. But
imported bos attempt to grab the bo dma-resv during dm
In cdv_intel_lvds_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_mode_duplicate(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: 6a227d5fd6c4 ("gma500: Add support for Cedarview")
Signed-off-b
On 09/07/2024 12:12, Greg KH wrote:
On Tue, Jul 09, 2024 at 12:04:02PM +0200, Jocelyn Falempe wrote:
On 09/07/2024 11:12, Greg KH wrote:
On Tue, Jul 09, 2024 at 11:11:35AM +0200, Greg KH wrote:
On Tue, Jul 09, 2024 at 10:40:10AM +0200, Jocelyn Falempe wrote:
+config DRM_PANIC_SCREEN_QR_C
…
> Signed-off-by: Ma Ke
Are you going to adjust this information anyhow?
> ---
> Changes in v4:
> - revised the recipient email list, apologize for the inadvertent mistake.
…
The usage of mailing list addresses is probably undesirable for
the Developer's Certificate of Origin, isn't it?
https
Hi Maxime,
On Mon, Jul 08, 2024 at 04:57:49PM +0200, Maxime Ripard wrote:
> On Fri, Jul 05, 2024 at 05:14:36PM GMT, Alain Volmat wrote:
> > Hi Krzysztof, Daniel, and Maxime,
> >
> > On Fri, Jul 05, 2024 at 03:41:26PM +0200, Daniel Vetter wrote:
> > > On Fri, Jul 05, 2024 at 01:33:38PM +0200, Krzy
We're seeing a GPU HANG issue on a CHV platform, which was caused by
bac24f59f454 ("drm/i915/execlists: Enable coarse preemption boundaries for
gen8").
Gen8 platform has only timeslice and doesn't support a preemption mechanism
as engines do not have a preemption timer and doesn't send an irq if
On 30.06.24 01:18, Mikhail Gavrilov wrote:
> On Sat, Jun 29, 2024 at 9:46 PM Rodrigo Siqueira Jordao
> wrote:
>>
>> I'm trying to reproduce this issue, but until now, I've been unable to
>> reproduce it. I tried some different scenarios with the following
>> components:
>>
>> 1. Displays: I tried
Hello everyone,
Thank you a lot for your prompt feedbacks.
I'm really sorry for all the mistakes, it is the first time that I try to
submit a patch and i thought I followed the guideline but clearly that was
not the case.
@Marek Vasut About your question to why disabling
burst-mode:
- I agree w
Hi,
On Mon, 01 Jul 2024 14:28:34 +0530, Manikandan Muralidharan wrote:
> This patch series adds panel himax display controller support for the
> Microchip's AC40T08A MIPI display.
>
> yaml file is validated using the following commands
>
> make dt_binding_check DT_SCHEMA_FILES=
> make CHECK_DTBS
Hi,
On Thu, 04 Jul 2024 12:50:14 +0800, Cong Yang wrote:
> This series support for Melfas lmfbx101117480 MIPI-DSI panel with
> jadard-jd9365da controller.
> Add compatible for melfas lmfbx101117480 in dt-bindings.
> Break some CMDS into helper functions.
>
> Changes in v2:
> - PATCH 1/3: No chang
+
4 files changed, 313 insertions(+)
---
base-commit: 97e1ea2dc264da85da53b6ae5726a130bef690a3
change-id: 20240709-topic-sdm450-upstream-tbx605f-panel-f13d55fbd444
Best regards,
--
Neil Armstrong
Document the 1200x1920 BOE TV101WUM-LL2 DSI Display Panel found
in the Lenovo Smart Tab M10 tablet. The controller is unknown.
Signed-off-by: Neil Armstrong
---
.../bindings/display/panel/boe,tv101wum-ll2.yaml | 63 ++
1 file changed, 63 insertions(+)
diff --git
a/Documen
Add support for the 1200x1920 BOE TV101WUM-LL2 DSI Display Panel found
in the Lenovo Smart Tab M10 tablet. The controller is unknown.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/
The Starry is a 10.1" WXGA TFT LCD panel. Because Starry-er88577
and boe-th101mb31ig002 have very similar inti_code, after
discussing with Dmitry Baryshkov, We will modify it based on the
panel-boe-th101mb31ig002-28a.c driver instead of using a separate
driver.
Changes between V6 and V5:
- PAT
This driver currently only applies to one panel. Modify it to be
compatible with other panels.
Signed-off-by: Zhaoxiong Lv
---
Changes between V6 and V5:
- 1. Corrected the use of "->init" in struct panel_desc,
- 2. Modify indentation in "boe_th101mb31ig002_of_match[]"
v5:
https://lore.kernel
Switch the driver to use devm_gpiod_get_optional() on reset_gpio to avoid
driver probe issues when reset line is not specified.
Signed-off-by: Zhaoxiong Lv
---
Changes between V6 and V5:
- 1. No changes.
v5:
https://lore.kernel.org/all/20240704072958.27876-3-lvzhaoxi...@huaqin.corp-partner.goog
-
2 files changed, 9 insertions(+), 19 deletions(-)
---
base-commit: 0b58e108042b0ed28a71cd7edf517555b233
change-id: 20240709-dpu-fix-wb-6cd57e3eb182
Best regards,
--
Dmitry Baryshkov
In order to prevent any errors on connector being disabled, move the
state->crtc check upfront. This should fix the issues during suspend
when the writeback connector gets forcebly disabled.
Fixes: 71174f362d67 ("drm/msm/dpu: move writeback's atomic_check to
dpu_writeback.c")
Cc: sta...@vger.kern
DPU debugging macros need to be converted to a proper drm_debug_*
macros, however this is a going an intrusive patch, not suitable for a
fix. Wire DPU_DEBUG and DPU_DEBUG_DRIVER to always use DRM_DEBUG_DRIVER
to make sure that DPU debugging messages always end up in the drm debug
messages and are c
Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to
simplify driver's init/enable/exit code.
Convert the hex in init_code from UPPERCASE to lowercase.
Signed-off-by: Zhaoxiong Lv
Reviewed-by: Neil Armstrong
---
Changes between V6 and V5:
- 1. No changes.
v5:
https://lore.
The starry-er88577 is a 10.1" WXGA TFT-LCD panel, and the init_code
of the starry-er88577 panel is very similar to the boe-th101mb31ig002
panel, so We will add a new configuration based on
"boe,th101mb31ig002-28a.yaml".
Because the panel used reset gpio before but did not add the definition
of "re
The init_code of the starry-er88577 panel is very similar to the
panel-boe-th101mb31ig002-28a.c driver, so we make it compatible with
the panel-boe-th101mb31ig002-28a.c driver
Signed-off-by: Zhaoxiong Lv
Reviewed-by: Neil Armstrong
---
Changes between V6 and V5:
- 1. Add two lines of init_code
This patch series aims to add support for RZ/G2UL DU.
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
The output of LCDC is connected display parallel interface (DPI) and
supports a maximum resolution of WXGA along with
Document DU found in RZ/G2UL SoC. The DU block is identical to RZ/G2L
SoC, but has only DPI interface.
While at it, add missing required property port@1 for RZ/G2L and RZ/V2L
SoCs. Currently there is no user for the DPI interface and hence there
won't be any ABI breakage for adding port@1 as requi
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
It has DPI interface and supports a maximum resolution of WXGA along
with 2 RPFs to support the blending of two picture layers and raster
operations (ROPs).
The DU module i
Add vspd node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das
---
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index
Add fcpvd node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das
---
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index
Add DU node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das
---
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
Enable DU and link with the HDMI add-on board connected with
the parallel connector on RZ/G2UL SMARC EVK.
Signed-off-by: Biju Das
---
v1->v2:
* No change.
---
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 111 ++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/
Hello,
syzbot found the following issue on:
HEAD commit:661e504db04c Merge tag 'for-6.10-rc6-tag' of git://git.ker..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=144e9f9998
kernel config: https://syzkaller.appspot.com/x/.config?x=864caee5f78cab51
das
On 09/07/2024 15:47, Zhaoxiong Lv wrote:
This driver currently only applies to one panel. Modify it to be
compatible with other panels.
Signed-off-by: Zhaoxiong Lv
---
Changes between V6 and V5:
- 1. Corrected the use of "->init" in struct panel_desc,
- 2. Modify indentation in "boe_th101mb31
On 09/07/2024 15:47, Zhaoxiong Lv wrote:
Switch the driver to use devm_gpiod_get_optional() on reset_gpio to avoid
driver probe issues when reset line is not specified.
Signed-off-by: Zhaoxiong Lv
---
Changes between V6 and V5:
- 1. No changes.
v5:
https://lore.kernel.org/all/20240704072958.2
On 7/9/24 06:09, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
enable PSR more quickly for displays that support it.
Signed-o
On 09/07/2024 13:53, Nitin Gote wrote:
We're seeing a GPU HANG issue on a CHV platform, which was caused by
bac24f59f454 ("drm/i915/execlists: Enable coarse preemption boundaries for
gen8").
Gen8 platform has only timeslice and doesn't support a preemption mechanism
as engines do not have a p
On 7/9/24 2:45 PM, Stefano Radaelli wrote:
Hello everyone,
Hi,
Thank you a lot for your prompt feedbacks.
I'm really sorry for all the mistakes, it is the first time that I try to
submit a patch and i thought I followed the guideline but clearly that was
not the case.
@Marek Vasut About y
Hi Marek,
Actually this property is specific also to DSI8x bridge, as you can see
from the screenshot below taken from official datasheet:
[image: image.png]
And it's the sn65dsi8x driver that tells MIPI driver which flags to use
during attachment.
So, for example, this bridge can work also for
On 6/29/24 5:18 PM, Mikhail Gavrilov wrote:
On Sat, Jun 29, 2024 at 9:46 PM Rodrigo Siqueira Jordao
wrote:
Hi Mikhail,
I'm trying to reproduce this issue, but until now, I've been unable to
reproduce it. I tried some different scenarios with the following
components:
1. Displays: I tried w
On 7/9/24 6:41 AM, Linux regression tracking (Thorsten Leemhuis) wrote:
On 30.06.24 01:18, Mikhail Gavrilov wrote:
On Sat, Jun 29, 2024 at 9:46 PM Rodrigo Siqueira Jordao
wrote:
I'm trying to reproduce this issue, but until now, I've been unable to
reproduce it. I tried some different scen
On 7/9/24 4:44 PM, Stefano Radaelli wrote:
Hi Marek,
Hi,
Actually this property is specific also to DSI8x bridge, as you can see
from the screenshot below taken from official datasheet:
[image: image.png]
And it's the sn65dsi8x driver that tells MIPI driver which flags to use
during attachm
On 7/9/24 3:10 AM, Ma Ke wrote:
To avoid reports of NULL_RETURN warning, we should add
otg_master NULL check.
Cc: sta...@vger.kernel.org
Fixes: c51d87202d1f ("drm/amd/display: do not attempt ODM power optimization if
minimal transition doesn't exist")
Signed-off-by: Ma Ke
---
Changes in v2:
-
On 09/07/2024 11:41, Miguel Ojeda wrote:
Hi Jocelyn,
A quick docs-only review of the Rust side (some of these apply in
several cases -- I just wanted to give an overview for you to
consider).
Thanks, I'll fix all typo/grammar you mentioned.
On Tue, Jul 9, 2024 at 10:45 AM Jocelyn Falempe
On 09/07/2024 11:41, Alice Ryhl wrote:
On Tue, Jul 9, 2024 at 10:45 AM Jocelyn Falempe wrote:
This patch adds a new panic screen, with a QR code and the kmsg data
embedded.
If DRM_PANIC_SCREEN_QR_CODE_URL is set, then the kmsg data will be
compressed with zlib and encoded as a numerical seg
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