The following changes since commit 1ddaaa244021aba8496536a6627b4ad2bc0f936a:
Merge tag 'amd-drm-next-6.11-2024-06-07' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2024-06-11 14:01:55
+1000)
are available in the Git repository at:
https://github.com/HabanaAI/drivers.accel.ha
On Sat, 15 Jun 2024 00:58:51 +0300, Danila Tikhonov wrote:
> This series adds MDSS and DPU support for SM7150.
>
> Changes in v3:
> - Swap DPU and MDSS patches (Krzysztof)
> - Add an explanation of the abbreviation DPU in patch 1 (Krzysztof)
> - Switch qseed3_1_4 on qseed3_2_4 in patch 2 (Dmitry
On Thu, 09 May 2024 19:52:04 +0200, Barnabás Czémán wrote:
> CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> so better to skip CTL irq callback register/unregister
> make dpu_ctl_cfg be able to define without intr_start.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: g
On Thu, 13 Jun 2024 20:05:03 +0300, Dmitry Baryshkov wrote:
> Command-mode DSI panels need to signal the display controlller when
> vsync happens, so that the device can start sending the next frame. Some
> devices (Google Pixel 3) use a non-default pin, so additional
> configuration is required.
On Tue, 14 May 2024 15:55:06 +0300, Jani Nikula wrote:
> Convert more drivers to struct drm_edid.
>
> Compile tested only.
>
> Jani Nikula (11):
> drm/rockchip: cdn-dp: get rid of drm_edid_raw()
> drm/sti/sti_hdmi: convert to struct drm_edid
> drm/bridge: analogix_dp: convert to struct dr
On Thu, 20 Jun 2024 13:17:30 -0700, Abhinav Kumar wrote:
> clear_pending_flush() ctl op is always assigned irrespective of the DPU
> hardware revision. Hence there is no needed to check whether the op has
> been assigned before calling it.
>
> Drop the checks across the driver for clear_pending_
On Fri, 07 Jun 2024 16:22:57 +0300, Dmitry Baryshkov wrote:
> This patchset sits on top Maxime's HDMI connector patchset ([1]).
>
> Currently this is an RFC exploring the interface between HDMI bridges
> and HDMI connector code. This has been lightly verified on the Qualcomm
> DB820c, which has
On Tue, 23 Apr 2024 00:36:58 +0200, Konrad Dybcio wrote:
> Shaving off some cruft
>
> obj files seem to be identical pre and post cleanup which is always
> a good sign
>
>
Applied, thanks!
[1/2] drm/msm/dsi: Remove dsi_phy_read/write()
https://gitlab.freedesktop.org/lumag/msm/-/commit/
On Thu, 30 May 2024 13:56:44 +0800, Jun Nie wrote:
> This is follow up update to Jonathan's patch set.
>
> Changes vs V5:
> - Add hardware version check for compression bit change in cfg2 register
>
> Changes vs V4:
> - Polish width calculation with helper function
> - Split cfg2 compression bi
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 4:51
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.co
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 5:14
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.co
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 5:08
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.co
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 4:53
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.co
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月21日 23:25
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.c
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 5:06
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.co
Hi Maxime：
> -Original Message-
> From: Maxime Ripard
> Sent: 2024年5月22日 15:25
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com; maarten.lankho...@linux.intel.com
On 6/21/24 13:30, Sunil Kovvuri Goutham wrote:
+
+What:
/sys/kernel/debug/habanalabs_cn/hbl_cn/nic_disable_decap
+What:
/sys/kernel/debug/habanalabs_cn/hbl_cn/nic_inject_rx_err
+What:
>> /sys/kernel/debug/habanalabs_cn/hbl_cn/nic_mac_lane_remap
>>
Hi,
On 6/23/24 03:29, Dmitry Torokhov wrote:
In case of non-OF match (which
includes the case where you use software nodes) the match data is coming
from matching spi_device_id entry in the driver.
We don't care about much how it is probed now, rather, after the driver
probed by a non-OF way,
On Sun, Jun 23, 2024 at 03:38:23PM +0800, Sui Jingfeng wrote:
> Hi,
>
> On 6/23/24 03:29, Dmitry Torokhov wrote:
> > > In case of non-OF match (which
> > > > includes the case where you use software nodes) the match data is coming
> > > > from matching spi_device_id entry in the driver.
> > >
> >
On 23/06/2024 01:25, Barnabás Czémán wrote:
> Add the compatible for the MDP5 found on MSM8937.
>
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Krzysztof Kozlowski
---
This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process,
On 23/06/2024 01:25, Barnabás Czémán wrote:
> The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new
> compatible for it.
>
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
Not all platforms provide correct PWM backlight capabilities through ATIF.
Use the generic drm backlight quirk infrastructure to override the
capabilities where necessary.
Signed-off-by: Thomas Weißschuh
---
drivers/gpu/drm/amd/amdgpu/Kconfig| 1 +
drivers/gpu/drm/amd/display/am
Panels using a PWM-controlled backlight source without an do not have a
standard way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI through driver-specific tables.
The built-in ranges are not necessarily correct, or may grow stale if an
older device can be retrofitted w
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Add a generic quirk infrastructure for backlight configuration to
override the settings provided by the firmware.
Also add amdgpu as a user of that infrastruct
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Add a quirk to override that the minimum backlight PWM to "0" which
leads to a much lower minimum brightness, which is still visible.
Tested on a Framework AM
Are you planning on submitting a bogus CVE for this patch too?
- Joshie 🐸✨
On June 22, 2024 9:22:19 AM GMT+01:00, Ma Ke wrote:
>In amdgpu_connector_add_common_modes(), the return value of drm_cvt_mode()
>is assigned to mode, which will lead to a NULL pointer dereference on
>failure of drm_cvt_mo
On Sun, Jun 23, 2024 at 7:59 AM Dmitry Baryshkov
wrote:
>
> On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> > From: Daniil Titov
> >
> > Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
> >
> > Signed-off-by: Daniil Titov
> > Signed-off-by: Barnabás Czémán
> >
This series adds support for the Adreno X1-85 GPU found in Qualcomm's
compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
naming scheme for Adreno GPU, 'X' stands for compute series, '1' denotes
1st generation and '8' & '5' denotes the tier and the SKU which it
belongs.
X1-85 has m
Add support in drm/msm driver for the Adreno X185 gpu found in
Snapdragon X1 Elite chipset.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++
drivers/gpu/drm/msm/adreno/adreno_device.c |
Document Adreno X185 GMU in the dt-binding specification.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/
Add the necessary dt nodes for gpu support in X1E80100.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +
1 file changed, 195 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
inde
On 23/06/2024 13:06, Akhil P Oommen wrote:
> This series adds support for the Adreno X1-85 GPU found in Qualcomm's
> compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
> naming scheme for Adreno GPU, 'X' stands for compute series, '1' denotes
> 1st generation and '8' & '5' denotes
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Document Adreno X185 GMU in the dt-binding specification.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Add the necessary dt nodes for gpu support in X1E80100.
>
> Signed-off-by: Akhil P Oommen
> ---
> + gmu: gmu@3d6a000 {
> + compatible = "qcom,adreno-gmu-x185.1",
> "qcom,adreno-gmu";
> + reg = <0x0 0
We expect each schema with variable number of clocks, to have the widest
constrains in top-level "properties:". This is more readable and also
makes binding stricter, if there is no "if:then:" block for given
variant.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/disp
All devices should (and actually do) have same order of entries, if
possible. That's the case for reg/reg-names, so define the reg-names in
top-level to enforce that.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 -
1 file changed, 4 inser
MMIO address space is known per each variant of Adreno GPU, so we can
constrain the reg/reg-names entries for each variant. There is no DTS
for A619, so that part is not accurate but could be corrected later.
Signed-off-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/msm/gpu.yaml |
On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2024 13:06, Akhil P Oommen wrote:
> > Add the necessary dt nodes for gpu support in X1E80100.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> > + gmu: gmu@3d6a000 {
> > + compatible = "qcom
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Document Adreno X185 GMU in the dt-binding specification.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindin
On 23/06/2024 14:28, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
>> On 23/06/2024 13:06, Akhil P Oommen wrote:
>>> Add the necessary dt nodes for gpu support in X1E80100.
>>>
>>> Signed-off-by: Akhil P Oommen
>>> ---
>>> + gmu: gmu@3d6a000
dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for
given binding validation if the schema contains compatible list with
pattern and a const fallback. This leads to binding being a no-op - not
being applied at all. Issue should be fixed in the dtschema but for now
add a wor
From: Krzysztof Kozlowski
[ Upstream commit 1f3512cdf8299f9edaea9046d53ea324a7730bab ]
Core in platform_driver_register() already sets the .owner, so driver
does not need to. Whatever is set here will be anyway overwritten by
main driver calling platform_driver_register().
Signed-off-by: Krzys
From: Douglas Anderson
[ Upstream commit c38896ca6318c2df20bbe6c8e3f633e071fda910 ]
Based on grepping through the source code this driver appears to be
missing a call to drm_atomic_helper_shutdown() at system shutdown
time. Among other things, this means that if a panel is in use that it
won't b
From: Tobias Jakobi
[ Upstream commit f74fb5df429ebc6a614dc5aa9e44d7194d402e5a ]
Similar to the other Aya Neo devices this one features
again a portrait screen, here with a native resolution
of 1600x2560.
Signed-off-by: Tobias Jakobi
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede
Li
From: Douglas Anderson
[ Upstream commit 0320ca14c6fb68ad19aa72e55a1a21c061b2946b ]
Based on grepping through the source code, this driver appears to be
missing a call to drm_atomic_helper_shutdown() at system shutdown time.
This is important because drm_atomic_helper_shutdown() will cause
panel
From: Krzysztof Kozlowski
[ Upstream commit 1f3512cdf8299f9edaea9046d53ea324a7730bab ]
Core in platform_driver_register() already sets the .owner, so driver
does not need to. Whatever is set here will be anyway overwritten by
main driver calling platform_driver_register().
Signed-off-by: Krzys
From: Tobias Jakobi
[ Upstream commit f74fb5df429ebc6a614dc5aa9e44d7194d402e5a ]
Similar to the other Aya Neo devices this one features
again a portrait screen, here with a native resolution
of 1600x2560.
Signed-off-by: Tobias Jakobi
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede
Li
From: Douglas Anderson
[ Upstream commit c38896ca6318c2df20bbe6c8e3f633e071fda910 ]
Based on grepping through the source code this driver appears to be
missing a call to drm_atomic_helper_shutdown() at system shutdown
time. Among other things, this means that if a panel is in use that it
won't b
From: Tobias Jakobi
[ Upstream commit f74fb5df429ebc6a614dc5aa9e44d7194d402e5a ]
Similar to the other Aya Neo devices this one features
again a portrait screen, here with a native resolution
of 1600x2560.
Signed-off-by: Tobias Jakobi
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede
Li
On Sun, Jun 23, 2024 at 02:00:26PM +0200, Krzysztof Kozlowski wrote:
> MMIO address space is known per each variant of Adreno GPU, so we can
> constrain the reg/reg-names entries for each variant. There is no DTS
> for A619, so that part is not accurate but could be corrected later.
>
> Signed-of
On Sun, Jun 23, 2024 at 02:00:25PM +0200, Krzysztof Kozlowski wrote:
> All devices should (and actually do) have same order of entries, if
> possible. That's the case for reg/reg-names, so define the reg-names in
> top-level to enforce that.
>
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Cono
On Sun, Jun 23, 2024 at 02:00:24PM +0200, Krzysztof Kozlowski wrote:
> We expect each schema with variable number of clocks, to have the widest
> constrains in top-level "properties:". This is more readable and also
> makes binding stricter, if there is no "if:then:" block for given
> variant.
>
Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
and then configures the Pixel PLL register.
This is a preparatory patch for further rework, where tc_pxl_pll_calc()
will also be used to find out the exact
The only information in the datasheet regarding this divider is a note
in SYS_PLLPARAM register documentation which states that when LSCLK is
270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
confirms using LSCLK
The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
image contains jittering empty lines.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Dani
This line_pixel_subtract is no longer needed now that the bridge can
request and obtain specific pixel clock on input to the bridge, with
clock frequency that matches the Pixel PLL frequency.
The line_pixel_subtract is now always 0, so drop it entirely.
The line_pixel_subtract was not reliable as
This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.
With clock improvements in place, this seems to be no longer
necessary. Set the CLRSIPO to default setting recommended by
manufacturer.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jernej
Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
pass it down the display pipeline to obtain exactly this frequency on input
into this bridge.
The precise input frequency that matches the Pixel
> > But what about when the system is under memory pressure? You say it
> > allocates memory. What happens if those allocations fail. Does
> > changing the MTU take me from a working system to a dead system? It is
> > good practice to not kill a working system under situations like
> > memory press
On 6/20/24 22:14, Andrew Lunn wrote:
> On Thu, Jun 20, 2024 at 06:51:35AM -0700, Jakub Kicinski wrote:
>> On Thu, 20 Jun 2024 08:43:34 + Omer Shpigelman wrote:
You support 400G, you really need to give the user the ability
to access higher pages.
>>>
>>> Actually the 200G and 400G m
> > If there is no netdev, what is the point of putting it into loopback?
> > How do you send packets which are to be looped back? How do you
> > receive them to see if they were actually looped back?
> >
> > Andrew
>
> To run RDMA test in loopback.
What is special about your RDMA? Why do yo
On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2024 14:28, Akhil P Oommen wrote:
> > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
> >> On 23/06/2024 13:06, Akhil P Oommen wrote:
> >>> Add the necessary dt nodes for gpu support in X1E80100.
>
On 20/06/2024 21:18, Doug Anderson wrote:
Hi,
On Thu, Jun 20, 2024 at 11:12 AM Tejas Vipin wrote:
Use functions introduced in commit 966e397e4f60 ("drm/mipi-dsi:
Introduce mipi_dsi_*_write_seq_multi()") and commit f79d6d28d8fe
("drm/mipi-dsi: wrap more functions for streamline handling") for
On 23/06/2024 16:13, Conor Dooley wrote:
> On Sun, Jun 23, 2024 at 02:00:26PM +0200, Krzysztof Kozlowski wrote:
>> MMIO address space is known per each variant of Adreno GPU, so we can
>> constrain the reg/reg-names entries for each variant. There is no DTS
>> for A619, so that part is not accurat
On 6/22/24 1:56 PM, Conor Dooley wrote:
On Fri, Jun 21, 2024 at 05:53:53PM +0200, Marek Vasut wrote:
Document default DP port preemphasis configurable via new DT property
"toshiba,pre-emphasis". This is useful in case the DP link properties
are known and starting link training from preemphasis s
On Sun, Jun 23, 2024 at 04:48:47PM +0200, Marek Vasut wrote:
> On 6/22/24 1:56 PM, Conor Dooley wrote:
> > On Fri, Jun 21, 2024 at 05:53:53PM +0200, Marek Vasut wrote:
> > > Document default DP port preemphasis configurable via new DT property
> > > "toshiba,pre-emphasis". This is useful in case th
On 6/3/2024 9:55 AM, Jeff Johnson wrote:
> make allmodconfig && make W=1 C=1 reports:
> WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/char/agp/amd64-agp.o
> WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/char/agp/intel-agp.o
> WARNING: modpost: missing MODULE_DESCRIPTION() in
…
> Signed-off-by: keith
Should the personal name be more unique
(according to the Developer's Certificate of Origin)?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.10-rc4#n438
…
> +++ b/drivers/gpu/drm/bridge/innosilic
Commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") re-used
amd,imageon compatible for the SM8150 just to enable headless mode due
to missing display controller nodes. This work-around was later
narrowed to the SM8150 MTP board in commit 1642ab96efa4 ("arm64: dts:
qcom: sm8150: Don't st
The SM8150 MTP board does not have magically different GPU than the
SM8150, so it cannot use amd,imageon compatible, also pointed by
dtbs_check:
sm8150-mtp.dtb: gpu@2c0: compatible: 'oneOf' conditional failed, one must
be fixed:
['qcom,adreno-640.1', 'qcom,adreno', 'amd,imageon'] is too
devicetree/bindings/display/msm/gpu.yaml | 27 ++
1 file changed, 23 insertions(+), 4 deletions(-)
---
base-commit: d47fa80a484f97ea51991c9547636a799c264652
change-id: 20240623-qcom-adreno-dts-bindings-driver-87521a145260
Best regards,
--
Krzysztof Kozlowski
All devices should (and actually do) have same order of entries, if
possible. That's the case for reg/reg-names, so define the reg-names in
top-level to enforce that.
Acked-by: Conor Dooley
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 -
Regex for newer Adreno compatibles can be simpler.
Suggested-by: Conor Dooley
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml
dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for
given binding validation if the schema contains compatible list with
pattern and a const fallback. This leads to binding being a no-op - not
being applied at all. Issue should be fixed in the dtschema but for now
add a wor
We expect each schema with variable number of clocks, to have the widest
constrains in top-level "properties:". This is more readable and also
makes binding stricter, if there is no "if:then:" block for given
variant.
Acked-by: Conor Dooley
Signed-off-by: Krzysztof Kozlowski
---
Documentation/
On 23/06/2024 17:16, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
>> On 23/06/2024 14:28, Akhil P Oommen wrote:
>>> On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Add the nece
On Fri, Jun 21, 2024 at 05:52:32PM GMT, Daniel Vetter wrote:
> On Fri, Jun 21, 2024 at 09:40:09AM -0600, Jeffrey Hugo wrote:
> > On 6/21/2024 5:19 AM, Dmitry Baryshkov wrote:
> > > On Fri, 21 Jun 2024 at 09:19, Bjorn Andersson
> > > wrote:
> > > >
> > > > On Wed, Jun 12, 2024 at 09:28:39PM GMT,
On 6/23/2024 03:51, Thomas Weißschuh wrote:
Panels using a PWM-controlled backlight source without an do not have a
standard way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI through driver-specific tables.
The built-in ranges are not necessarily correct, or may grow
This patch series adds support for the MDP and DSI PHY as found on the
MSM8937 platform.
Signed-off-by: Barnabás Czémán
---
Changes in v2:
- Remove MDP_CAP_SRC_SPLIT from mdp5_cfg
- Link to v1: https://lore.kernel.org/r/20240623-dsi-v1-0-4ab560eb5...@gmail.com
---
Barnabás Czémán (2):
dt
Add the compatible for the MDP5 found on MSM8937.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
b/
From: Daniil Titov
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 88
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/m
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 +
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 +
From: Daniil Titov
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only
difference from existing msm8916 configuration is number of phy
and io_start addresses.
Signed-off-by: Daniil Titov
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/dsi/ph
On Sun, Jun 23, 2024 at 08:46:30PM GMT, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
> > On 23/06/2024 14:28, Akhil P Oommen wrote:
> > > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
> > >> On 23/06/2024 13:06, Akhil P Oommen w
Hi Keith,
On Sun, Jun 23, 2024 at 07:16:47AM GMT, Keith Zhao wrote:
> > On Tue, May 21, 2024 at 06:58:11PM +0800, keith wrote:
> > > +}
> > > +
> > > +static inline void dc_set_clear(struct dc_hw *hw, u32 reg, u32 set, u32
> > > clear)
> > > +{
> > > + u32 value = dc_read(hw, reg);
> > > +
> > >
On Sun, Jun 23, 2024 at 07:17:01AM GMT, Keith Zhao wrote:
> Hi Dmitry:
>
> > -Original Message-
> > From: Dmitry Baryshkov
Please drop such headers from your replies. A simple "On 1st of January
John Doe wrote" is more than enough.
--
With best wishes
Dmitry
On Sun, Jun 23, 2024 at 07:17:07AM GMT, Keith Zhao wrote:
> >
> > On Tue, May 21, 2024 at 06:58:13PM +0800, keith wrote:
> > > add plane funs and helper funs
> > > add vs drm common struct and funs
> > >
> > > Signed-off-by: keith
> > > ---
> > > drivers/gpu/drm/verisilicon/Makefile | 3 +-
>
Hi,
On 6/23/24 10:20 PM, Mario Limonciello wrote:
> On 6/23/2024 03:51, Thomas Weißschuh wrote:
>> Panels using a PWM-controlled backlight source without an do not have a
>> standard way to communicate their valid PWM ranges.
>> On x86 the ranges are read from ACPI through driver-specific tables.
On Sun, Jun 23, 2024 at 07:17:04AM GMT, Keith Zhao wrote:
> > On Tue, May 21, 2024 at 06:58:14PM +0800, keith wrote:
> > > add crtc funs and helper funs
> > >
> > > Signed-off-by: keith
> > > ---
> > > drivers/gpu/drm/verisilicon/Makefile | 3 +-
> > > drivers/gpu/drm/verisilicon/vs_crtc.c | 2
On Sun, Jun 23, 2024 at 03:40:06PM -0500, Bjorn Andersson wrote:
> On Sun, Jun 23, 2024 at 08:46:30PM GMT, Akhil P Oommen wrote:
> > On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
> > > On 23/06/2024 14:28, Akhil P Oommen wrote:
> > > > On Sun, Jun 23, 2024 at 01:17:16PM +0200
On Sun, Jun 23, 2024 at 07:16:57AM GMT, Keith Zhao wrote:
> > On Tue, May 21, 2024 at 06:58:15PM +0800, keith wrote:
> > > Add vs DRM master driver for JH7110 SoC ADD DMA GEM driver
> > >
> > > Signed-off-by: keith
> > > ---
> > > drivers/gpu/drm/verisilicon/Makefile | 3 +-
> > > drivers/gpu/d
On Sun, Jun 23, 2024 at 07:17:09AM GMT, Keith Zhao wrote:
> Hi Dmitry:
>
> > On Tue, May 21, 2024 at 06:58:17PM +0800, keith wrote:
> > > +
> > > "starfive,syscon",
> > > + 2, args
On Sun, Jun 23, 2024 at 12:48:53PM GMT, Barnabás Czémán wrote:
> On Sun, Jun 23, 2024 at 7:59 AM Dmitry Baryshkov
> wrote:
> >
> > On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> > > From: Daniil Titov
> > >
> > > Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
On Sun, Jun 23, 2024 at 04:36:29PM GMT, Akhil P Oommen wrote:
> Add support in drm/msm driver for the Adreno X185 gpu found in
> Snapdragon X1 Elite chipset.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
> drivers/gpu/drm/msm/ad
On Sun, Jun 23, 2024 at 04:36:30PM GMT, Akhil P Oommen wrote:
> Add the necessary dt nodes for gpu support in X1E80100.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +
> 1 file changed, 195 insertions(+)
>
> diff --git a/arch/
On Sun, Jun 23, 2024 at 01:11:48PM GMT, Krzysztof Kozlowski wrote:
> On 23/06/2024 13:06, Akhil P Oommen wrote:
> > This series adds support for the Adreno X1-85 GPU found in Qualcomm's
> > compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
> > naming scheme for Adreno GPU, 'X' sta
On Sun, Jun 23, 2024 at 10:30:37PM GMT, Barnabás Czémán wrote:
> From: Daniil Titov
>
> Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
>
> Signed-off-by: Daniil Titov
> Signed-off-by: Barnabás Czémán
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 88
>
Remove MDP_CAP_SRC_SPLIT from msm8x53_config because
it is not referenced in downstream.
Fixes: fb25d4474fa0 ("drm/msm/mdp5: Add configuration for MDP v1.16")
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
On 6/21/24 19:48, Mina Almasry wrote:
On Mon, Jun 17, 2024 at 7:17 AM Pavel Begunkov wrote:
...
static inline unsigned long netmem_to_pfn(netmem_ref netmem)
{
+ if (netmem_is_net_iov(netmem))
+ return 0;
IIRC 0 is a valid pfn. Not much of a concern since it's
used only
On 6/21/24 21:31, Mina Almasry wrote:
On Mon, Jun 17, 2024 at 9:36 AM Pavel Begunkov wrote:
On 6/13/24 02:35, Mina Almasry wrote:
The pages awaiting freeing are stored in the newly added
sk->sk_user_frags, and each page passed to userspace is get_page()'d.
This reference is dropped once the
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