The patch set initial support Cadence MHDP8501(HDMI/DP) DRM bridge
drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for Freescale i.MX8MQ.
The patch set compose of DRM bridge drivers and PHY drivers.
Both of them need patche #1 and #2 to pass build.
DRM bridges driver patches:
#1: drm: bridge:
MHDP8546 mailbox access functions will be share to other mhdp driver
and Cadence HDP-TX HDMI/DP PHY drivers.
Create a new mhdp helper driver and move all those functions into.
cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(),
because it use the DPTX command ID DPTX_WRITE_REGISTER.
New
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
Reviewed-by: D
Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.
Signed-off-by: Sandor Yu
Reviewed-by: Krzysztof Kozlowski
---
v9->v11:
*No change.
.../display/bridge/cdns,mhdp8501.yaml | 104 ++
1 file changed, 104 insertions(+)
create mode 100644
Documentation/devicetree
Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
SOC's ROM code. Bootload binary incl
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu
Reviewed-by: Rob Herring
---
v9->v11:
*No change.
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/fsl
Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
DisplayPort PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
---
v9->v11:
*No change.
drivers/phy/freescale/Kconfig
Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
HDMI PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
Tested-by: Alexander Stein
---
v9->v11:
*No change.
drivers/phy/freescale/Kco
Hi Jessica,
On Tue, 17 Oct 2023 at 03:41, Jessica Zhang wrote:
> On 9/24/2023 3:23 AM, Dmitry Baryshkov wrote:
> > On 22/09/2023 20:49, Jessica Zhang wrote:
> >>
> >>
> >> On 8/29/2023 1:22 AM, Pekka Paalanen wrote:
> >>> On Mon, 28 Aug 2023 17:05:13 -0700
> >>> Jessica Zhang wrote:
> >>>
>
On Fri, Oct 13, 2023 at 12:22:52PM +0200, Michel Dänzer wrote:
> On 10/13/23 11:41, Daniel Vetter wrote:
> > On Thu, Oct 12, 2023 at 02:19:41PM -0400, Ray Strode wrote:
> >> On Mon, Oct 09, 2023 at 02:36:17PM +0200, Christian König wrote:
> >> To be clear, my take is, if driver code is running
On Mon, Oct 16, 2023 at 1:12 PM Akhil P Oommen wrote:
>
> On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
> >
> > Some (many?) devices with A635 expect a ZAP shader to be loaded.
> >
> > Set the file name to allow for that.
> >
> > Signed-off-by: Konrad Dybcio
> > ---
> > drivers/
On Fri, Oct 13, 2023 at 10:04:02AM -0400, Ray Strode wrote:
> Hi
>
> On Fri, Oct 13, 2023 at 5:41 AM Daniel Vetter wrote:
> > > I mean we're not talking about scientific computing, or code
> > > compilation, or seti@home. We're talking about nearly the equivalent
> > > of `while (1) __asm__ ("nop
Hi David,
> > For drivers that would like to longterm-pin the pages associated
> > with a file, the pin_user_pages_fd() API provides an option to
> > not only FOLL_PIN the pages but also to check and migrate them
> > if they reside in movable zone or CMA block. For now, this API
> > can only work
Hi Chris,
Am Montag, 16. Oktober 2023, 20:26:58 CEST schrieb Chris Morgan:
> On Mon, Oct 16, 2023 at 08:18:25PM +0200, Heiko Stübner wrote:
> > Hi,
> >
> > Am Montag, 16. Oktober 2023, 18:07:52 CEST schrieb Dragan Simic:
> > > On 2023-10-16 17:52, Chris Morgan wrote:
> > > > Confirmed that those
Am 17.10.23 um 09:32 schrieb Daniel Vetter:
On Fri, Oct 13, 2023 at 12:22:52PM +0200, Michel Dänzer wrote:
On 10/13/23 11:41, Daniel Vetter wrote:
On Thu, Oct 12, 2023 at 02:19:41PM -0400, Ray Strode wrote:
On Mon, Oct 09, 2023 at 02:36:17PM +0200, Christian König wrote:
To be clear, my take
On Tue, Oct 10, 2023 at 04:27:24PM +0200, Thomas Hellström wrote:
> Dual-licence in order to make it possible for other non-GPL os'es
> to re-implement the code. The use of EXPORT_SYMBOL_GPL() is intentionally
> left untouched to prevent use of drm_gpuvm as a proxy for non-GPL drivers
> to access G
There are a few spelling mistakes and an minor grammatical issue in
some dml_print messages. Fix these.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/
On 10/17/23 09:54, Danilo Krummrich wrote:
On Tue, Oct 10, 2023 at 04:27:24PM +0200, Thomas Hellström wrote:
Dual-licence in order to make it possible for other non-GPL os'es
to re-implement the code. The use of EXPORT_SYMBOL_GPL() is intentionally
left untouched to prevent use of drm_gpuvm as
> -Original Message-
> From: Murthy, Arun R
> Sent: Monday, October 16, 2023 9:56 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Hogander, Jouni
> ; Nikula, Jani
> Subject: RE: [PATCH v7 4/6] drm/i915/panelreplay: Enable panel replay
Update the names of ast's VGA registers to follow the documentation
and put all constants into a separate header. The update make the
driver source code more grep-able. No functional changes.
Thomas Zimmermann (12):
drm/ast: Rename AST_IO_AR_PORT_WRITE to AST_IO_VGAARI_W
drm/ast: Rename AST_IO
Rename AST_IO_VGA_SEQ_PORT to AST_IO_VGASRI to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 22 +++---
2 files changed, 12 insertions(+), 12 dele
Improve readability by putting all register constants into a separate
header file. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 83 +
drivers/gpu/drm/ast/ast_reg.h | 99 +++
2 files changed
Rename AST_IO_GR_PORT to AST_IO_VGAGRI to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/driver
Rename AST_IO_INPUT_STATUS1_READ to AST_IO_VGAIR1_R to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
di
Rename AST_IO_MISC_PORT_WRITE to AST_IO_VGAMR_W to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_main.c | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 4 ++--
3 files changed, 4
Rename AST_IO_DAC_DATA to AST_IO_VGAPDR to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/d
Rename AST_IO_DAC_INDEX_READ to AST_IO_VGADRR to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gp
Rename AST_IO_AR_PORT_WRITE to AST_IO_VGAARI_W to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
d
Rename AST_IO_VGA_ENABLE_PORT to AST_IO_VGAER to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_main.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Rename AST_IO_DAC_INDEX_WRITE to AST_IO_VGADWR to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Rename AST_IO_CRTC_PORT to AST_IO_VGACRI to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_dp.c| 70 +++
drivers/gpu/drm/ast/ast_dp501.c | 38 -
drivers/gpu/drm/ast/ast_drv.h | 2 +-
Rename AST_IO_MISC_PORT_READ to AST_IO_VGAMR_R to align naming
in the driver with documentation. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_mode.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
On Fri, Oct 06, 2023 at 09:25:29AM -0600, Jeffrey Hugo wrote:
> On 10/3/2023 12:42 AM, Stanislaw Gruszka wrote:
> > From: Jacek Lawrynowicz
> >
> > Fix a bug on some platforms where FLR causes complete system
> > hang when CPU is low power states (C8 or above).
>
> Why does FLR cause a complete
On Tue, Oct 17, 2023 at 10:14:59AM +0200, Thomas Hellström wrote:
>
> On 10/17/23 09:54, Danilo Krummrich wrote:
> > On Tue, Oct 10, 2023 at 04:27:24PM +0200, Thomas Hellström wrote:
> > > Dual-licence in order to make it possible for other non-GPL os'es
> > > to re-implement the code. The use of
From: Simon Ser
If the driver supports it, allow user-space to supply the
DRM_MODE_PAGE_FLIP_ASYNC flag to request an async page-flip.
Set drm_crtc_state.async_flip accordingly.
Document that drivers will reject atomic commits if an async
flip isn't possible. This allows user-space to fall back
Hi,
This work from me and Simon adds support for DRM_MODE_PAGE_FLIP_ASYNC through
the atomic API. This feature is already available via the legacy API. The use
case is to be able to present a new frame immediately (or as soon as
possible), even if after missing a vblank. This might result in teari
From: Simon Ser
This new field indicates whether the driver has the necessary logic
to support async page-flips via the atomic uAPI. This is leveraged by
the next commit to allow user-space to use this functionality.
All atomic drivers setting drm_mode_config.async_page_flip are updated
to also
From: Simon Ser
This new kernel capability indicates whether async page-flips are
supported via the atomic uAPI. DRM clients can use it to check
for support before feeding DRM_MODE_PAGE_FLIP_ASYNC to the kernel.
Make it clear that DRM_CAP_ASYNC_PAGE_FLIP is for legacy uAPI only.
Signed-off-by:
From: Simon Ser
amdgpu_dm_commit_planes() already sets the flip_immediate flag for
async page-flips. This flag is used to set the UNP_FLIP_CONTROL
register. Thus, no additional change is required to handle async
page-flips with the atomic uAPI.
Signed-off-by: Simon Ser
Reviewed-by: André Almeid
From: Pekka Paalanen
Specify how the atomic state is maintained between userspace and
kernel, plus the special case for async flips.
Signed-off-by: Pekka Paalanen
Signed-off-by: André Almeida
---
v7:
- add a note that drivers can make exceptions for ad-hoc prop changes
- add a note about flipp
Given that prop changes may lead to modesetting, which would defeat the
fast path of the async flip, refuse any atomic prop change for async
flips in atomic API. The only exceptions are the framebuffer ID to flip
to and the mode ID, that could be referring to an identical mode.
Signed-off-by: Andr
Il 16/10/23 12:39, Hsiao Chien Sung ha scritto:
Padding is a new hardware module on MediaTek MT8188,
add dt-bindings for it.
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del Regno
Il 16/10/23 12:39, Hsiao Chien Sung ha scritto:
Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
to align the naming rule of mtk_ovl_adaptor_comp_id.
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del Regno
Il 16/10/23 12:39, Hsiao Chien Sung ha scritto:
- Adjust indentation to align with other files
- Sort device table in alphabetical order
- Add sentinel to device table
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del Regno
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Sort OVL adaptor components' names in alphabetical order.
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del Regno
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Add component ID to component match structure so we can
configure them with a for-loop.
The main reason we do such code refactoring is that
there is a new hardware component called "Padding" since
MT8188, while MT8195 doesn't have this module, we c
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of clock control significantly.
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of component start/stop process.
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Padding is a new display module on MT8188, it provides ability
to add pixels to width and height of a layer with specified colors.
Due to hardware design, Mixer in VDOSYS1 requires width of a layer
to be 2-pixel-align, or 4-pixel-align when ETHDR i
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of clock control significantly.
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
---
.../gpu/drm/mediatek/mtk_disp_
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Add MT8188 Padding to OVL adaptor to probe the driver.
Signed-off-by: Hsiao Chien Sung
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dis
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Return the result of clk_prepare_enable() instead of
always returns 0.
Fixes: f8946e2b6bb2 ("drm/mediatek: Add display MDP RDMA support for MT8195")
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
Reviewed-by: AngeloGioacchino Del Regno
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
DPI input is in 1T2P mode on both MT8195 and MT8188.
Remove the redundant driver data to align the settings, or
the screen will glitch.
Fixes: 2847cd7e6403 ("drm/mediatek: Add mt8188 dpi compatibles and platform
data")
Reviewed-by: CK Hu
Signed-
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Do not reset Merge while using CMDQ because reset API doesn't
wait for frame done event as CMDQ does and could lead to
underrun when the layer is switching off.
Fixes: aaf94f7c3ae6 ("drm/mediatek: Add display merge async reset control")
Signed-off
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
Different from OVL, OVL adaptor is a pseudo device so we didn't
define it in the device tree, consequently, pm_runtime_resume_and_get()
called by .atomic_enable() powers on no device in OVL adaptor and
leads to power outage in the corresponding IOMM
On Fri, Oct 13, 2023 at 02:30:29PM +0200, Thomas Hellström wrote:
> On Mon, 2023-10-09 at 01:32 +0200, Danilo Krummrich wrote:
> > Add an abstraction layer between the drm_gpuva mappings of a
> > particular
> > drm_gem_object and this GEM object itself. The abstraction represents
> > a
> > combinat
Hi Sandor,
thanks for the update.
One small typo in the commit message: 'Creat' -> 'Create'
Am Dienstag, 17. Oktober 2023, 09:03:57 CEST schrieb Sandor Yu:
> MHDP8546 mailbox access functions will be share to other mhdp driver
> and Cadence HDP-TX HDMI/DP PHY drivers.
> Create a new mhdp helper
On Tuesday, October 17, 2023 2:15 AM, Heiko Stübner wrote:
> Hi,
Hi,
>
> Am Montag, 17. Juli 2023, 08:18:27 CEST schrieb Liu Ying:
> > To get better accuration, use pixel clock rate to calculate lbcc instead of
> > lane_mbps since the pixel clock rate is in KHz while lane_mbps is in MHz.
> > Wit
Reviewed-by: Simon Ser
Il 16/10/23 18:21, Krzysztof Kozlowski ha scritto:
On 12/10/2023 10:40, Moudy Ho wrote:
Add compatible string and GCE property for MT8195 SPLIT, of
which is operated by MDP3.
Signed-off-by: Moudy Ho
---
After feedback from Angelo:
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: AngeloGioa
Hi,
On 10/17/23 11:58, Danilo Krummrich wrote:
On Fri, Oct 13, 2023 at 02:30:29PM +0200, Thomas Hellström wrote:
On Mon, 2023-10-09 at 01:32 +0200, Danilo Krummrich wrote:
Add an abstraction layer between the drm_gpuva mappings of a
particular
drm_gem_object and this GEM object itself. The abs
Hi Amaranath,
On 16.10.2023 15:08, Somalapuram, Amaranath wrote:
On 10/16/2023 2:22 PM, Karolina Stolarek wrote:
Add tests for building blocks of the TTM subsystem, such as ttm_resource,
ttm_resource_manager, ttm_tt and ttm_buffer_object. This series covers
basic functions such as initializati
Vinay Belgaumkar writes:
> This bit does not cause an explicit L3 flush. We already use
> PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.
>
> Cc: Nirmoy Das
> Cc: Mikka Kuoppala
s/kk/k
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
> 1 file ch
On 10/17/2023 4:35 PM, Karolina Stolarek wrote:
Hi Amaranath,
On 16.10.2023 15:08, Somalapuram, Amaranath wrote:
On 10/16/2023 2:22 PM, Karolina Stolarek wrote:
Add tests for building blocks of the TTM subsystem, such as
ttm_resource,
ttm_resource_manager, ttm_tt and ttm_buffer_object. Thi
Il 17/10/23 12:50, Shawn Sung (宋孝謙) ha scritto:
Hi Angelo,
On Tue, 2023-10-17 at 11:47 +0200, AngeloGioacchino Del Regno wrote:
Il 16/10/23 12:40, Hsiao Chien Sung ha scritto:
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify t
Am 17.10.23 um 13:22 schrieb Somalapuram, Amaranath:
On 10/17/2023 4:35 PM, Karolina Stolarek wrote:
Hi Amaranath,
On 16.10.2023 15:08, Somalapuram, Amaranath wrote:
On 10/16/2023 2:22 PM, Karolina Stolarek wrote:
Add tests for building blocks of the TTM subsystem, such as
ttm_resource,
On 17.10.2023 13:57, Christian König wrote:
Am 17.10.23 um 13:22 schrieb Somalapuram, Amaranath:
On 10/17/2023 4:35 PM, Karolina Stolarek wrote:
Hi Amaranath,
On 16.10.2023 15:08, Somalapuram, Amaranath wrote:
On 10/16/2023 2:22 PM, Karolina Stolarek wrote:
Add tests for building blocks o
Am 17.10.23 um 14:06 schrieb Karolina Stolarek:
On 17.10.2023 13:57, Christian König wrote:
Am 17.10.23 um 13:22 schrieb Somalapuram, Amaranath:
On 10/17/2023 4:35 PM, Karolina Stolarek wrote:
Hi Amaranath,
On 16.10.2023 15:08, Somalapuram, Amaranath wrote:
On 10/16/2023 2:22 PM, Karolin
On Mon, Oct 16, 2023 at 10:00:51PM +, Simon Ser wrote:
> On Monday, October 16th, 2023 at 17:10, Ville Syrjälä
> wrote:
>
> > On Mon, Oct 16, 2023 at 05:52:22PM +0300, Pekka Paalanen wrote:
> >
> > > On Mon, 16 Oct 2023 15:42:16 +0200
> > > André Almeida andrealm...@igalia.com wrote:
> > >
Hi,
Am Dienstag, 17. Oktober 2023, 12:15:11 CEST schrieb Ying Liu:
> On Tuesday, October 17, 2023 2:15 AM, Heiko Stübner wrote:
> > Am Montag, 17. Juli 2023, 08:18:27 CEST schrieb Liu Ying:
> > > To get better accuration, use pixel clock rate to calculate lbcc instead
> > > of
> > > lane_mbps si
This reverts commit 645d694559cab36fe6a57c717efcfa27d9321396.
The commit cause issues with memory access from the device side.
Switch back to write-combined memory mappings until the issues
will be properly addressed.
Add extra wmb() needed when boot_params->save_restore_ret_address() is
modified
On 17/10/2023 10:31, Thomas Zimmermann wrote:
Update the names of ast's VGA registers to follow the documentation
and put all constants into a separate header. The update make the
driver source code more grep-able. No functional changes.
I think the previous name is more meaningful than the one
After discussing with André it seems like we missed a plane type check
here. We need to make sure FB_ID changes are only allowed on primary
planes.
Contain struct drm_flip_task and its helper functions
drm_flip_work_allocate_task() and drm_flip_work_queue_task() within
drm_flip_work.c There are no callers outside of the flip-work code.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_flip_work.c | 27 +++
inc
On 10/16/23 22:04, Arnd Bergmann wrote:
From: Arnd Bergmann
When QMP is in a loadable module, the A6xx GPU driver fails to link
as built-in:
x86_64-linux-ld: drivers/gpu/drm/msm/adreno/a6xx_gmu.o: in function
`a6xx_gmu_resume':
a6xx_gmu.c:(.text+0xd62): undefined reference to `qmp_send'
A
Hi Sandor,
thanks for the patch.
Am Dienstag, 17. Oktober 2023, 09:04:00 CEST schrieb Sandor Yu:
> Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
> used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
> standards according embedded Firmware running in the uCPU.
Hi Sandor,
thanks for the patch.
Am Dienstag, 17. Oktober 2023, 09:04:02 CEST schrieb Sandor Yu:
> Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort PHY mode is configurated i
On 17.10.2023 14:10, Christian König wrote:
Am 17.10.23 um 14:06 schrieb Karolina Stolarek:
On 17.10.2023 13:57, Christian König wrote:
Am 17.10.23 um 13:22 schrieb Somalapuram, Amaranath:
On 10/17/2023 4:35 PM, Karolina Stolarek wrote:
Hi Amaranath,
On 16.10.2023 15:08, Somalapuram, Amar
Hi Sandor,
thanks for the patch.
Am Dienstag, 17. Oktober 2023, 09:04:03 CEST schrieb Sandor Yu:
> Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> HDMI PHY mode is configurated in the driver.
On 10/13/23 15:00, Thomas Hellström wrote:
On Fri, 2023-10-13 at 13:51 +0200, Danilo Krummrich wrote:
On 10/13/23 13:38, Thomas Hellström wrote:
On Mon, 2023-10-09 at 01:32 +0200, Danilo Krummrich wrote:
Provide a common dma-resv for GEM objects not being used outside
of
this
GPU-VM. This is u
On Tue, Oct 17, 2023 at 12:52 AM Luben Tuikov wrote:
>
> A context priority value of AMD_CTX_PRIORITY_UNSET is now invalid--instead of
> carrying it around and passing it to the Direct Rendering Manager--and it
> becomes AMD_CTX_PRIORITY_NORMAL in amdgpu_ctx_ioctl(), the gateway to context
> creat
On 17/10/2023 06:28, André Almeida wrote:
Hi,
This work from me and Simon adds support for DRM_MODE_PAGE_FLIP_ASYNC through
the atomic API. This feature is already available via the legacy API. The use
case is to be able to present a new frame immediately (or as soon as
possible), even if aft
On 2023-10-17 09:22, Alex Deucher wrote:
> On Tue, Oct 17, 2023 at 12:52 AM Luben Tuikov wrote:
>>
>> A context priority value of AMD_CTX_PRIORITY_UNSET is now invalid--instead of
>> carrying it around and passing it to the Direct Rendering Manager--and it
>> becomes AMD_CTX_PRIORITY_NORMAL in amd
Hi Vinay,
> > > This bit does not cause an explicit L3 flush. We already use
> > At all? Or only on newer hardware? And as a genuine spec change or as a
> > bug / workaround?
> >
> > If the hardware has re-purposed the bit then it is probably worth at
> > least adding a comment to the bit definit
In Xe, the new Intel GPU driver, a choice has made to have a 1 to 1
mapping between a drm_gpu_scheduler and drm_sched_entity. At first this
seems a bit odd but let us explain the reasoning below.
1. In Xe the submission order from multiple drm_sched_entity is not
guaranteed to be the same completi
As a prerequisite to merging the new Intel Xe DRM driver [1] [2], we
have been asked to merge our common DRM scheduler patches first.
This a continuation of a RFC [3] with all comments addressed, ready for
a full review, and hopefully in state which can merged in the near
future. More details of t
Add scheduler wqueue ready, stop, and start helpers to hide the
implementation details of the scheduler from the drivers.
v2:
- s/sched_wqueue/sched_wqueue (Luben)
- Remove the extra white line after the return-statement (Luben)
- update drm_sched_wqueue_ready comment (Luben)
Cc: Luben Tuik
Rather than a global modparam for scheduling policy, move the scheduling
policy to scheduler so user can control each scheduler policy.
v2:
- s/DRM_SCHED_POLICY_MAX/DRM_SCHED_POLICY_COUNT (Luben)
- Only include policy in scheduler (Luben)
v3:
- use a ternary operator as opposed to an if-cont
DRM_SCHED_POLICY_SINGLE_ENTITY creates a 1 to 1 relationship between
scheduler and entity. No priorities or run queue used in this mode.
Intended for devices with firmware schedulers.
v2:
- Drop sched / rq union (Luben)
v3:
- Don't pick entity if stopped in drm_sched_select_entity (Danilo)
v4:
Also add a lockdep assert to drm_sched_start_timeout.
Signed-off-by: Matthew Brost
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/scheduler/sched_main.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers
Add a helper whereby a driver can invoke TDR immediately.
v2:
- Drop timeout args, rename function, use mod delayed work (Luben)
v3:
- s/XE/Xe (Luben)
- present tense in commit message (Luben)
- Adjust comment for drm_sched_tdr_queue_imm (Luben)
v4:
- Adjust commit message (Luben)
Cc: Luben
Rather than call free_job and run_job in same work item have a dedicated
work item for each. This aligns with the design and intended use of work
queues.
v2:
- Test for DMA_FENCE_FLAG_TIMESTAMP_BIT before setting
timestamp in free_job() work item (Danilo)
v3:
- Drop forward dec of drm_sc
On 10/17/23 09:33, Rob Clark wrote:
On Mon, Oct 16, 2023 at 1:12 PM Akhil P Oommen wrote:
On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
Some (many?) devices with A635 expect a ZAP shader to be loaded.
Set the file name to allow for that.
Signed-off-by: Konrad Dybcio
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