Hi All,
Gentle ping. Are we happy with this patch series?
Is anything to be improved? Please let me know.
Cheers,
Biju
> -Original Message-
> From: Biju Das
> Sent: Monday, October 2, 2023 8:15 AM
> Subject: RE: [PATCH v2 0/8] ADV7511 driver enhancements
> > -Original Message-
>
On 06/10/2023 18:54, Noralf Trønnes wrote:
On 10/6/23 16:35, Maxime Ripard wrote:
Hi Jocelyn,
On Thu, Oct 05, 2023 at 11:16:15AM +0200, Jocelyn Falempe wrote:
On 05/10/2023 10:18, Maxime Ripard wrote:
Hi,
On Tue, Oct 03, 2023 at 04:22:45PM +0200, Jocelyn Falempe wrote:
diff --git a/includ
Hi Noralf
Am 07.10.23 um 14:01 schrieb Noralf Trønnes:
On 10/5/23 11:04, Thomas Zimmermann wrote:
DRM's format-conversion helpers require temporary memory. Pass the
buffer from the caller and keep it allocated over several calls. Allow
the caller to preallocate the buffer memory.
The motivat
On 07/10/2023 14:38, Noralf Trønnes wrote:
On 10/3/23 16:22, Jocelyn Falempe wrote:
This module displays a user friendly message when a kernel panic
occurs. It currently doesn't contain any debug information,
but that can be added later.
v2
* Use get_scanout_buffer() instead of the drm clie
Hi Maxime
Am 06.10.23 um 16:49 schrieb Maxime Ripard:
Hi,
On Thu, Oct 05, 2023 at 11:04:20AM +0200, Thomas Zimmermann wrote:
DRM's format-conversion helpers require temporary memory. Pass the
buffer from the caller and keep it allocated over several calls. Allow
the caller to preallocate the b
Hi,
On Mon, Oct 09, 2023 at 09:47:49AM +0200, Jocelyn Falempe wrote:
> On 06/10/2023 18:54, Noralf Trønnes wrote:
> >
> >
> > On 10/6/23 16:35, Maxime Ripard wrote:
> > > Hi Jocelyn,
> > >
> > > On Thu, Oct 05, 2023 at 11:16:15AM +0200, Jocelyn Falempe wrote:
> > > > On 05/10/2023 10:18, Maxime
On 07/10/2023 00:43, Matthew Brost wrote:
On Fri, Oct 06, 2023 at 03:14:04PM +, Matthew Brost wrote:
On Fri, Oct 06, 2023 at 08:59:15AM +0100, Tvrtko Ursulin wrote:
On 05/10/2023 05:13, Luben Tuikov wrote:
On 2023-10-04 23:33, Matthew Brost wrote:
On Tue, Sep 26, 2023 at 11:32:10PM -04
Hi Javier
Am 05.10.23 um 15:38 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Preallocate the format-conversion state's storage in the plane's
atomic_check function if a format conversion is necessary. Allows
the update to fail if no memory is available. Avoids the
On Mon, Oct 09, 2023 at 09:27:02AM +0800, Huacai Chen wrote:
> Hi, all,
>
> On Tue, Sep 26, 2023 at 10:31 PM Huacai Chen wrote:
> >
> > Hi, all,
> >
> > On Tue, Sep 26, 2023 at 7:15 PM Linux regression tracking (Thorsten
> > Leemhuis) wrote:
> > >
> > > [CCing the regression list, as it should b
On Mon, Oct 9, 2023 at 4:45 PM Bagas Sanjaya wrote:
>
> On Mon, Oct 09, 2023 at 09:27:02AM +0800, Huacai Chen wrote:
> > Hi, all,
> >
> > On Tue, Sep 26, 2023 at 10:31 PM Huacai Chen wrote:
> > >
> > > Hi, all,
> > >
> > > On Tue, Sep 26, 2023 at 7:15 PM Linux regression tracking (Thorsten
> > >
On 07/10/2023 05:03, Ma Ke wrote:
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
Wrong function, it should be tpg110_get_modes()
Thanks,
Neil
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
On 07/10/2023 05:31, Ma Ke wrote:
In versatile_panel_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/panel/panel-arm-
On 07/10/2023 08:49, Ruihai Zhou wrote:
The sta_himax83102 panel sometimes shows abnormally flickering
horizontal lines. The front gate output will precharge the X point of
the next pole circuit before TP(TouchPanel Enable) term starts, and wait
until the end of the TP term to resume the CLK. For
Thomas Zimmermann writes:
Hello Thomas,
> Hi Javier
>
> Am 05.10.23 um 15:38 schrieb Javier Martinez Canillas:
>> Thomas Zimmermann writes:
[...]
>>> +static int simpledrm_primary_plane_helper_atomic_check(struct drm_plane
>>> *plane,
>>> + st
On 09/10/2023 00:33, Marek Vasut wrote:
Add missing .bus_flags = DRM_BUS_FLAG_DE_HIGH to this panel description,
ones which match both the datasheet and the panel display_timing flags .
Fixes: 1e29b840af9f ("drm/panel: simple: Add Innolux G101ICE-L01 panel")
Signed-off-by: Marek Vasut
---
Cc: D
Hi,
On 09/10/2023 00:32, Marek Vasut wrote:
The Innolux G101ICE-L01 datasheet [1] page 17 table
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
indicates that maximum vertical blanking time is 40 lines.
Currently the driver uses 29 lines.
Fix it, and since this panel is a DE panel, adjust the timings
to
[AMD Official Use Only - General]
Reviewed-by: Shashank Sharma
Regards
Shashank
-Original Message-
From: Icenowy Zheng
Sent: Sunday, October 8, 2023 8:47 AM
To: Deucher, Alexander ; Koenig, Christian
; Pan, Xinhui ; David Airlie
; Daniel Vetter ; Sharma, Shashank
; Yadav, Arvind
Cc:
In tpg110_get_modes(), the return value of drm_mode_duplicate() is
assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/panel/panel-tpo-tpg110.c | 2 ++
1 file changed, 2 insertions(
Hi,
On Tue, 19 Sep 2023 12:39:39 +0200, Uwe Kleine-König wrote:
> The .remove() callback for a platform driver returns an int which makes
> many driver authors wrongly assume it's possible to do error handling by
> returning an error code. However the value returned is ignored (apart
> from emitti
Hi,
On Fri, 06 Oct 2023 17:07:02 +0200, Michael Tretter wrote:
> I tested the i.MX8M Nano EVK with the NXP supplied MIPI-DSI adapter,
> which uses an ADV7535 MIPI-DSI to HDMI converter. I found that a few
> modes were working, but in many modes my monitor stayed dark.
>
> This series fixes the Sa
Hi,
On Fri, 29 Sep 2023 14:33:30 +0200, Johannes Zink wrote:
> Some LVDS panels, such as the innolux,g101ice-l01 support multiple LVDS
> data mapping modes, which can be configured by strapping a dataformat
> pin on the display to a specific voltage.
>
> This can be particularly useful for using
On 09/10/2023 11:04, Ma Ke wrote:
In tpg110_get_modes(), the return value of drm_mode_duplicate() is
assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/panel/panel-tpo-tpg110.c
Am Fr., 6. Okt. 2023 um 22:23 Uhr schrieb Kees Cook :
>
> On Mon, Sep 18, 2023 at 01:34:08PM +, Justin Stitt wrote:
> > `strncpy` is deprecated for use on NUL-terminated destination strings [1].
> >
> > We should prefer more robust and less ambiguous string interfaces.
> >
> > A suitable replac
Hi Javier
Am 09.10.23 um 10:58 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Hi Javier
Am 05.10.23 um 15:38 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
[...]
+static int simpledrm_primary_plane_helper_atomic_check(struct drm_plane *plane,
+
On Thu, Oct 05, 2023 at 08:49:09PM +0200, Duje Mihanović wrote:
> Add driver for the Kinetic KTD2801 backlight driver.
>
> Signed-off-by: Duje Mihanović
> ---
> MAINTAINERS | 6 ++
> drivers/video/backlight/Kconfig | 7 ++
> drivers/video/backlight/
Hi Devarsh,
On Mon, Oct 09, 2023 at 01:20:18PM +0530, Devarsh Thakkar wrote:
> Some SoC's such as AM62P have dedicated power domains
> for OLDI which need to be powered on separetely along
> with display controller.
>
> So during driver probe, power up all attached PM domains
> enumerated in devi
Thomas Zimmermann writes:
Hello Thomas,
> Hi Javier
>
> Am 09.10.23 um 10:58 schrieb Javier Martinez Canillas:
>> Thomas Zimmermann writes:
>>
>> Hello Thomas,
>>
>>> Hi Javier
>>>
>>> Am 05.10.23 um 15:38 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
>>
>> [...]
>>
The dpu_encoder_phys_ops::atomic_mode_set() callback is mostly
redundant. Implementations only set the IRQ indices there. Move
statically allocated IRQs to dpu_encoder_phys_*_init() and set
dynamically allocated IRQs in the irq_enable() callback.
Changes since v1:
- Split trace events into enable/
On Fri, Oct 06, 2023 at 03:08:42PM +0200, Duje Mihanović wrote:
> On Friday, October 6, 2023 2:30:14 PM CEST Daniel Thompson wrote:
> > On Thu, Oct 05, 2023 at 08:49:08PM +0200, Duje Mihanović wrote:
> > > + enable-gpios:
> > > +maxItems: 1
> >
> > Why "enable"? This is the line we are going t
Follow the _dpu_encoder_irq_control() change and split the
_dpu_encoder_resource_control_helper() into enable and disable parts.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 12 --
2
The single helper for both enable and disable cases is too complicated,
especially if we start adding more code to these helpers. Split it into
irq_enable and irq_disable cases.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ---
.../gpu/drm/msm/di
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.
For the CMD panel usecase some of IRQ indexes depend on the selected
resources. Move setti
On 09/10/2023 03:49, Helen Koike wrote:
Export the resultant kernel config, making it easier to verify if the
resultant config was correctly generated.
Suggested-by: Rob Clark
Signed-off-by: Helen Koike
Acked-by: Dmitry Baryshkov
I'd even say:
Appreciated-by: Dmitry Baryshkov
It will h
Since commit 00e7e698bff1 ("backlight: pwm_bl: Configure pwm only once
per backlight toggle") calling pwm_backlight_power_off() doesn't disable
the PWM any more. However this is necessary to suspend because PWM
drivers usually refuse to suspend if they are still enabled.
Also adapt shutdown and re
On 09/10/2023 10:28, Maxime Ripard wrote:
Hi,
On Mon, Oct 09, 2023 at 09:47:49AM +0200, Jocelyn Falempe wrote:
On 06/10/2023 18:54, Noralf Trønnes wrote:
On 10/6/23 16:35, Maxime Ripard wrote:
Hi Jocelyn,
On Thu, Oct 05, 2023 at 11:16:15AM +0200, Jocelyn Falempe wrote:
On 05/10/2023 10:18
On 07/10/2023 16:30, Noralf Trønnes wrote:
On 10/3/23 16:22, Jocelyn Falempe wrote:
Add support for the drm_panic module, which displays a message to
the screen when a kernel panic occurs.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/mgag200/mgag200_drv.c | 24 +++
On Mon, Oct 09, 2023 at 11:32:23AM +0200, Uwe Kleine-König wrote:
> Since commit 00e7e698bff1 ("backlight: pwm_bl: Configure pwm only once
> per backlight toggle") calling pwm_backlight_power_off() doesn't disable
> the PWM any more. However this is necessary to suspend because PWM
> drivers usuall
On Mon, 9 Oct 2023, Shyam Sundar S K wrote:
> On 10/4/2023 5:44 PM, Ilpo Järvinen wrote:
> > On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> >
> >> PMF driver sends changing inputs from each subystem to TA for evaluating
> >> the conditions in the policy binary.
> >>
> >> Add initial support of plu
Some SoC's such as AM62P have dedicated power domains
for OLDI which need to be powered on separetely along
with display controller.
So during driver probe, power up all attached PM domains
enumerated in devicetree node for DSS.
This also prepares base to add display support for AM62P.
Signed-of
On Mon, 9 Oct 2023, Shyam Sundar S K wrote:
>
>
> On 10/4/2023 4:20 PM, Ilpo Järvinen wrote:
> > On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> >
> >> AMD PMF driver loads the PMF TA (Trusted Application) into the AMD
> >> ASP's (AMD Security Processor) TEE (Trusted Execution Environment).
> >>
Hi Paloma,
On 28/07/2023 03:26, Paloma Arellano wrote:
Enable display compression (DSC v1.2) and CMD mode for 1080x2400 Visionox
VTDR6130 AMOLED DSI panel. In addition, this patch will set the default
to command mode with DSC enabled.
Note: This patch has only been validated DSC over command mo
Checking if a modifier is supported by a plane is normal behavior. It is
normal that a plane may not support certain modifiers. Failing the check
doesn't justify an error message in the kernel log and may mislead
users.
Demote the error message to drm_dbg_kms to only print the message if the
respe
On Mon, 9 Oct 2023, Shyam Sundar S K wrote:
> On 10/4/2023 5:30 PM, Ilpo Järvinen wrote:
> > On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> >
> >> PMF Policy binary is a encrypted and signed binary that will be part
> >> of the BIOS. PMF driver via the ACPI interface checks the existence
> >> of S
On Mon, 9 Oct 2023, Shyam Sundar S K wrote:
> On 10/4/2023 6:19 PM, Ilpo Järvinen wrote:
> > On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> >
> >> In order to provide GPU inputs to TA for the Smart PC solution to work, we
> >> need to have interface between the PMF driver and the AMDGPU driver.
>
cc +guilherme
On 06/10/2023 14:32, Rob Clark wrote:
From: Rob Clark
ssh logging is the default for mesa, as it is generally more reliable.
But if there are kernel issues, especially at boot, UART logging is
infinitely more useful.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/ci/gitlab-ci.y
On Mon, Oct 09, 2023 at 11:48:29AM +0200, Jocelyn Falempe wrote:
> On 09/10/2023 10:28, Maxime Ripard wrote:
> > Hi,
> >
> > On Mon, Oct 09, 2023 at 09:47:49AM +0200, Jocelyn Falempe wrote:
> > > On 06/10/2023 18:54, Noralf Trønnes wrote:
> > > >
> > > >
> > > > On 10/6/23 16:35, Maxime Ripard w
On Mon, Oct 09, 2023 at 08:42:24AM +0200, Christian König wrote:
> Am 06.10.23 um 20:48 schrieb Ray Strode:
> > Hi,
> >
> > On Fri, Oct 6, 2023 at 3:12 AM Christian König
> > wrote:
> >> When the operation busy waits then that *should* get accounted to the
> >> CPU time of the current process. Wh
Hi Kees,
On Fri, Oct 06, 2023 at 01:17:45PM -0700, Kees Cook wrote:
> Prepare for the coming implementation by GCC and Clang of the __counted_by
> attribute. Flexible array members annotated with __counted_by can have
> their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
> array
Am 09.10.23 um 14:19 schrieb Ville Syrjälä:
On Mon, Oct 09, 2023 at 08:42:24AM +0200, Christian König wrote:
Am 06.10.23 um 20:48 schrieb Ray Strode:
Hi,
On Fri, Oct 6, 2023 at 3:12 AM Christian König wrote:
When the operation busy waits then that *should* get accounted to the
CPU time of th
Am 07.10.23 um 11:50 schrieb Greg KH:
On Sun, Sep 10, 2023 at 03:43:01PM -0500, Bryan Jennings wrote:
This is also causing log spam on 5.15. It was included in 5.15.128 as
commit 4921792e04f2125b5eadef9dbe9417a8354c7eff. I encountered this and
found https://gitlab.freedesktop.org/drm/amd/-/iss
Hi all,
recently I've been looking at inconsistent frame times in one of our
graphics workloads and it seems the culprit lies within the MM
subsystem. During workload execution sporadically some graphics
buffers, which are typically single digit megabytes in size, are freed.
The pages are freed vi
On 10/9/23 01:32, Danilo Krummrich wrote:
Currently the DRM GPUVM offers common infrastructure to track GPU VA
allocations and mappings, generically connect GPU VA mappings to their
backing buffers and perform more complex mapping operations on the GPU VA
space.
However, there are more design
Hi Maxime,
Thanks for the review.
On 09/10/23 14:53, Maxime Ripard wrote:
> Hi Devarsh,
>
> On Mon, Oct 09, 2023 at 01:20:18PM +0530, Devarsh Thakkar wrote:
>> Some SoC's such as AM62P have dedicated power domains
>> for OLDI which need to be powered on separetely along
>> with display controlle
On 09/10/2023 13:33, Maxime Ripard wrote:
On Mon, Oct 09, 2023 at 11:48:29AM +0200, Jocelyn Falempe wrote:
On 09/10/2023 10:28, Maxime Ripard wrote:
Hi,
On Mon, Oct 09, 2023 at 09:47:49AM +0200, Jocelyn Falempe wrote:
On 06/10/2023 18:54, Noralf Trønnes wrote:
On 10/6/23 16:35, Maxime Ripa
DRM's format-conversion helpers require temporary memory. Pass the
buffer from the caller to allow the caller to preallocate the buffer
memory.
The motivation for this patchset is the recent work on a DRM panic
handler. [1] The panic handler requires format conversion to display an
error to the sc
Store an instance of struct drm_format_conv_state in the shadow-plane
state struct drm_shadow_plane_state. Many drivers with shadow planes
use DRM's format helpers to copy or convert the framebuffer data to
backing storage in the scanout buffer. The shadow plane provides the
necessary state and man
Preallocate the format-conversion state's storage in the plane's
atomic_check function if a format conversion is necessary. Allows
the update to fail if no memory is available. Avoids the same
allocation within atomic_update, which may not fail.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javie
Preallocate the format-conversion state's storage in the plane's
atomic_check function if a format conversion is necessary. Allows
the update to fail if no memory is available. Avoids the same
allocation within atomic_update, which may not fail.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javie
Pass an instance of struct drm_format_conv_state to DRM's format
conversion helpers. Update all callers.
Most drivers can use the format-conversion state from their shadow-
plane state. The shadow plane's destroy function releases the
allocated buffer. Drivers will later be able to allocate a buff
Preallocate the format-conversion state's storage in the plane's
atomic_check function if a format conversion is necessary. Allows
the update to fail if no memory is available. Avoids the same
allocation within atomic_update, which may not fail.
Also inline drm_plane_helper_atomic_check() into the
The plane's atomic_check returns -EINVAL if the CRTC has not been
set. This is the case for disabled planes, for which atomic_check
should return 0. For disabled planes, it also omits the mandatory
call to drm_atomic_helper_check_plane_state().
Replace the test with the boiler-plate code that firs
Hold temporary memory for format conversion in an instance of struct
drm_format_conv_state. Update internal helpers of DRM's format-conversion
code accordingly. Drivers will later be able to maintain this cache by
themselves.
Besides caching, struct drm_format_conv_state will be useful to hold
add
Thomas Zimmermann writes:
Hello Thomas,
> Store an instance of struct drm_format_conv_state in the shadow-plane
> state struct drm_shadow_plane_state. Many drivers with shadow planes
> use DRM's format helpers to copy or convert the framebuffer data to
> backing storage in the scanout buffer. Th
On 10/9/23 15:36, Thomas Hellström wrote:
On 10/9/23 01:32, Danilo Krummrich wrote:
Currently the DRM GPUVM offers common infrastructure to track GPU VA
allocations and mappings, generically connect GPU VA mappings to their
backing buffers and perform more complex mapping operations on the GPU
On Monday, October 9, 2023 11:21:03 AM CEST Daniel Thompson wrote:
> On Thu, Oct 05, 2023 at 08:49:09PM +0200, Duje Mihanović wrote:
> > +#define EW_DELAY 150
> > +#define EW_DET 270
> > +#define LOW_BIT_HIGH 5
> > +#define LOW_BIT_LOW(4 * HIGH_BIT_LOW)
> > +#define HIGH
On Mon, Oct 09, 2023 at 04:05:19PM +0200, Jocelyn Falempe wrote:
> > > - I find it risky to completely reconfigure the hardware in a panic
> > > handler.
> >
> > I would expect to only change the format and base address of the
> > framebuffer. I guess it can fail, but it doesn't seem that differe
On Tue, Jul 4, 2023 at 10:45 AM Dmitry Baryshkov
wrote:
>
> This patchset was left untouched for almost a year. Let's reiterate it
> in attempt to solve the long-standing issue.
>
> As discussed several times on IRC, move display subdriver resource
> allocation from kms_init to probe time to let i
bif.h | 12 ---
13 files changed, 120 insertions(+), 61 deletions(-)
---
base-commit: 9119cf579b4432b36be9d33a92f4331922067d92
change-id: 20231009-topic-sm8550-graphics-sspp-split-clk-43c32e37b6aa
Best regards,
--
Neil Armstrong
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
An optional clk_ctrl struct is added to the SSPP & WB caps,
which can be used by the setup_clk_force_ctrl() op.
Signed-off-by: Neil Armstrong
---
drivers/gpu/
Move the actual call to the MDP setup_clk_force_ctrl() op to
an helper which will call the correct op depending on the caps.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
Add an helper to setup the force clock control as it will
be used in multiple HW files.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +
drivers/gpu/drm/msm/disp/dpu
Now clk_ctrl IDs can be optional and the clk_ctrl_reg can be specified
on the SSPP & WB caps directly, pass the SSPP & WB hw struct to the
qos & limit params then call the clk_force_ctrl() op accordingly.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 4 +
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/ca
On Sun, Oct 08, 2023 at 02:49:40PM -0700, Randy Dunlap wrote:
> Correct typo of "its".
> Add commas for clarity.
> Capitalize L3.
>
> Signed-off-by: Randy Dunlap
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: intel-...@lists.freedesktop.org
> Cc: Maarten
Hi,
> From: Nirmoy Das
>
> Add a function for ratelimitted debug print.
>
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Thomas Zimmermann
> Cc: David Airlie
> Cc: Daniel Vetter
> Reviewed-by: Matthew Auld
> Reviewed-by: Andi Shyti
> Signed-off-by: Nirmoy Das
> Signed-off-by: Andi Sh
On 08/09/2023 22:33, Abhinav Kumar wrote:
To support high resolutions on sm8350, enable smartdma
in its catalog.
Signed-off-by: Abhinav Kumar
Tested-by: Dmitry Baryshkov
Reviewed-by: Dmitry Baryshkov
---
Notes:
only compile tested, to be landed after sufficient testing
--
With bes
Enable the SmartDMA / multirect support on the SM8450 platform to
support higher resoltion modes.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu
On 09/10/2023 19:36, Neil Armstrong wrote:
Add an helper to setup the force clock control as it will
be used in multiple HW files.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21
From: Maaz Mombasawala
There is no real need to have a separate pool for shareable and
non-shareable surfaces. Make all surfaces shareable, regardless of whether
the drm_vmw_surface_flag_shareable has been specified.
Signed-off-by: Maaz Mombasawala
Reviewed-by: Martin Krastev
Signed-off-by: Ma
From: Maaz Mombasawala
Update vmwgfx_drm.h with SPDX-License-Identifier:
(GPL-2.0 WITH Linux-syscall-note) OR MIT
Signed-off-by: Maaz Mombasawala
Reviewed-by: Martin Krastev
Signed-off-by: Maaz Mombasawala (VMware)
---
include/uapi/drm/vmwgfx_drm.h | 1 +
1 file changed, 1 insertion(+)
diff
On 09/10/2023 19:36, Neil Armstrong wrote:
Move the actual call to the MDP setup_clk_force_ctrl() op to
an helper which will call the correct op depending on the caps.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 15 +++
1 file changed, 11 insertio
On 09/10/2023 19:36, Neil Armstrong wrote:
Now clk_ctrl IDs can be optional and the clk_ctrl_reg can be specified
on the SSPP & WB caps directly, pass the SSPP & WB hw struct to the
qos & limit params then call the clk_force_ctrl() op accordingly.
Signed-off-by: Neil Armstrong
---
.../gpu/drm
On 09/10/2023 19:36, Neil Armstrong wrote:
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1 file changed, 15 insertions(+), 20 deletions(-)
This enables writeback on several platforms where I could actually test
it.
Dmitry Baryshkov (3):
drm/msm/dpu: enable writeback on SDM845
drm/msm/dpu: enable writeback on SM8350
drm/msm/dpu: enable writeback on SM8450
.../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 18 ++
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 18 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 --
2 files changed, 22 insertions(+), 2 deletions(-)
diff
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
b/drivers/gpu
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
b/drivers/gpu
On sc7280 there are two clk bits for WB2: control and status. While
programming the VBIF params of WB, the driver should be toggling the
former bit, while the sc7280_mdp struct lists the latter one.
Correct that to ensure proper programming sequence for WB2 on sc7280.
Fixes: 3ce166380567 ("drm/ms
I was not able to test it on my own, this is a call for testing for the
owners of these platforms. The git version of modetest now fully
supports writeback.
Compile libdrm/modetest from git version, run modetest -ac to determine
the writeback connector, cat /sys/kernel/debug/dri/0/state to determi
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
b/drivers/gpu
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
b/drivers/gp
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
b/drivers/gpu
Some display panels found in modern phones and laptops feature
non-standard display shapes with features like rounded corners, notches
(sections of the display that are cut-out from the edge), and cutouts
(such as circular "hole punch" camera cutouts, or wider pill-shaped
"islands").
Some discussi
On Sun, Jul 2, 2023 at 5:37 PM Dmitry Baryshkov
wrote:
>
> Currently both msm_drm_init() and msm_drm_uninit() functions are trying
> to handle both normal and headless Adreno cases. This results in a
> suboptimal code, since headless case still gets modesetting and atomic
> interfaces enabled. Two
This is a resend, since the previous submission got no responses. The
patches have been reviewed/acked by several maintainers. Can we please
gain some attention and either get it merged or understand what should
be changed / improved. This series is required to delivere HPD events
from altmode driv
In some cases the bridge drivers would like to receive hotplug events
even in the case new status is equal to the old status. In the DP case
this is used to deliver "attention" messages to the DP host. Stop
filtering the events in the drm_bridge_connector_hpd_cb() and let
drivers decide whether the
From: Bjorn Andersson
In some implementations, such as the Qualcomm platforms, the display
driver has no way to query the current HPD state and as such it's
impossible to distinguish between disconnect and attention events.
Add a parameter to drm_connector_oob_hotplug_event() to pass the HPD
sta
Implement the oob_hotplug_event() callback. Translate it to the HPD
notification sent to the HPD bridge in the chain.
Reviewed-by: Janne Grunau
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_bridge_connector.c | 31 +++---
1 file changed, 28 insertions(+), 3 deletio
This patchset was left untouched for almost a year. Let's reiterate it
in attempt to solve the long-standing issue.
As discussed several times on IRC, move display subdriver resource
allocation from kms_init to probe time to let it bail early.
Changes since v4:
- Rebased on top of linux-next
Cha
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