On Fri, 8 Sep 2023 06:05:16 +0300, Dmitry Baryshkov wrote:
> While debugging one of the features in DRM/MSM I noticed that MSM
> subdrivers still wrap private object access with manual modeset locking.
> Since commit b962a12050a3 ("drm/atomic: integrate modeset lock with
> private objects") this is
Hi,
On 9/7/23 16:49, Christian König wrote:
Am 07.09.23 um 16:47 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:37, Christian König wrote:
Am 07.09.23 um 15:53 schrieb Thomas Hellström:
While trying to replicate a weird drm_exec lock alloc tracking warning
using the drm_exec kunit test, the warn
On Thu, 7 Sep 2023 10:10:50 -0400
Harry Wentland wrote:
> On 2023-09-07 03:49, Pekka Paalanen wrote:
> > On Wed, 6 Sep 2023 16:15:10 -0400
> > Harry Wentland wrote:
> >
> >> On 2023-08-25 10:18, Melissa Wen wrote:
> >>> On 08/22, Pekka Paalanen wrote:
> On Thu, 10 Aug 2023 15:02:47
Hi Angelo,
On 07/09/23 16:16, AngeloGioacchino Del Regno wrote:
Il 25/08/23 14:24, Vignesh Raman ha scritto:
Enable regulator
Enable MT6397 RTC driver
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/arm64.config | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ci/a
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:2476
link_set_dpms_on() warn: if statement not indented.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6502
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/dis
On Mon, 04 Sep 2023 16:28:37 +0200, Maxim Schwalm wrote:
> On 28.08.23 17:59, Michael Tretter wrote:
> > Calculating the byte_clk in kHz is imprecise for a hs_clock of 55687500
> > Hz, which may be used with a pixel clock of 74.25 MHz with mode
> > 1920x1080-30.
> >
> > Fix the calculation by usin
On Thu, 7 Sep 2023 12:31:47 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: Pekka Paalanen
> > Sent: Tuesday, September 5, 2023 5:03 PM
> > To: Shankar, Uma
> > Cc: intel-...@lists.freedesktop.org; Borah, Chaitanya Kumar
> > ; dri-devel@lists.freedesktop.org; wayland-
> > d
Quoting Thomas Hellström (2023-08-22 19:21:32)
> This series adds a flag at VM_BIND time to pin the memory backing a VMA.
> Initially this is needed for long-running workloads on hardware that
> neither support mid-thread preemption nor pagefaults, since without it
> the userptr MMU notifier will w
Am 08.09.23 um 09:37 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:49, Christian König wrote:
Am 07.09.23 um 16:47 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:37, Christian König wrote:
Am 07.09.23 um 15:53 schrieb Thomas Hellström:
While trying to replicate a weird drm_exec lock alloc tracking
On 9/8/23 10:52, Christian König wrote:
Am 08.09.23 um 09:37 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:49, Christian König wrote:
Am 07.09.23 um 16:47 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:37, Christian König wrote:
Am 07.09.23 um 15:53 schrieb Thomas Hellström:
While trying to repl
Am 08.09.23 um 11:04 schrieb Thomas Hellström:
On 9/8/23 10:52, Christian König wrote:
Am 08.09.23 um 09:37 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:49, Christian König wrote:
Am 07.09.23 um 16:47 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:37, Christian König wrote:
Am 07.09.23 um 15:53
Hi
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * But there are two exceptions only for dumb buffers:
+ * * To support XRGB if it's not supported by the hardware.
+ * * Any driver is free to modify its internal representation of the
format,
+ * as long as
On Tue, 05 Sep 2023 18:06:06 +0900, 대인기/Tizen Platform Lab(SR)/삼성전자 wrote:
>
>
> > -Original Message-
> > From: dri-devel On Behalf Of
> > Michael Tretter
> > Sent: Monday, September 4, 2023 8:15 PM
> > To: Inki Dae
> > Cc: Neil Armstrong ; Robert Foss
> > ; Jonas Karlman ; dri-
> > de.
Hi,
On Fri, Sep 08, 2023 at 11:21:51AM +0200, Thomas Zimmermann wrote:
> Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
> [...]
> > + *
> > + * But there are two exceptions only for dumb buffers:
> > + * * To support XRGB if it's not supported by the hardware.
>
>
> > + * * Any dr
On 9/8/23 11:14, Christian König wrote:
Am 08.09.23 um 11:04 schrieb Thomas Hellström:
On 9/8/23 10:52, Christian König wrote:
Am 08.09.23 um 09:37 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:49, Christian König wrote:
Am 07.09.23 um 16:47 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:37, C
On Fri, 8 Sep 2023 11:21:51 +0200
Thomas Zimmermann wrote:
> Hi
>
> Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
> [...]
> > + *
> > + * But there are two exceptions only for dumb buffers:
> > + * * To support XRGB if it's not supported by the hardware.
>
>
> > + * * Any dri
Hi,
On Sat, Sep 2, 2023 at 7:42 AM Douglas Anderson wrote:
...
> @@ -952,6 +960,7 @@ static const struct dev_pm_ops mtk_drm_pm_ops = {
> static struct platform_driver mtk_drm_platform_driver = {
> .probe = mtk_drm_probe,
> .remove = mtk_drm_remove,
I think this patch, and perha
On 08/09/2023 13:23, Vignesh Raman wrote:
Hi Angelo,
On 07/09/23 16:16, AngeloGioacchino Del Regno wrote:
Il 25/08/23 14:24, Vignesh Raman ha scritto:
Enable regulator
Enable MT6397 RTC driver
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/arm64.config | 2 ++
1 file changed, 2 inse
Hi Maxime
Am 08.09.23 um 12:58 schrieb Maxime Ripard:
Hi,
On Fri, Sep 08, 2023 at 11:21:51AM +0200, Thomas Zimmermann wrote:
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * But there are two exceptions only for dumb buffers:
+ * * To support XRGB if it's not supported
Hi Jacopo Mondi,
Thanks for the review.
> Subject: Re: [PATCH v10 3/4] drm: renesas: Add RZ/G2L DU Support
>
> Hi Biju
>
> On Tue, Jul 04, 2023 at 10:04:46AM +0100, Biju Das wrote:
> > The LCD controller is composed of Frame Compression Processor (FCPVD),
> > Video Signal Processor (VSPD), and
On Friday, September 8th, 2023 at 22:22, Thomas Zimmermann
wrote:
> Am 08.09.23 um 12:58 schrieb Maxime Ripard:
>
> > Hi,
> >
> > On Fri, Sep 08, 2023 at 11:21:51AM +0200, Thomas Zimmermann wrote:
> >
> > > Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
> > > [...]
> > >
> > > > + *
> > > > +
Thomas Zimmermann writes:
Hello Thomas,
> Hi Maxime
>
> Am 08.09.23 um 12:58 schrieb Maxime Ripard:
>> Hi,
>>
>> On Fri, Sep 08, 2023 at 11:21:51AM +0200, Thomas Zimmermann wrote:
>>> Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
>>> [...]
+ *
+ * But there are two exceptions only
Hi
Am 08.09.23 um 13:16 schrieb Pekka Paalanen:
On Fri, 8 Sep 2023 11:21:51 +0200
Thomas Zimmermann wrote:
Hi
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * But there are two exceptions only for dumb buffers:
+ * * To support XRGB if it's not supported by the hardwa
On 08/09/2023 15:46, Javier Martinez Canillas wrote:
Thomas Zimmermann writes:
Hello Thomas,
Hi Maxime
Am 08.09.23 um 12:58 schrieb Maxime Ripard:
Hi,
On Fri, Sep 08, 2023 at 11:21:51AM +0200, Thomas Zimmermann wrote:
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * But th
Hi Javier
Am 08.09.23 um 15:46 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Hi Maxime
Am 08.09.23 um 12:58 schrieb Maxime Ripard:
Hi,
On Fri, Sep 08, 2023 at 11:21:51AM +0200, Thomas Zimmermann wrote:
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+
Hi Jocelyn
Am 08.09.23 um 16:06 schrieb Jocelyn Falempe:
[...]
And know I find that this patch (even in its v1) contains language that
retroactively legitimizes the mgag200 patch. I wrote 'apparently' I my
reply, as I assume that there's more to it, but how does it not look
like an attempt to sn
On 09/07, Pekka Paalanen wrote:
> On Wed, 6 Sep 2023 15:30:04 -0400
> Harry Wentland wrote:
>
> > On 2023-08-10 12:02, Melissa Wen wrote:
> > > Add 3D LUT property for plane gamma correction using a 3D lookup table.
> > > Since a 3D LUT has a limited number of entries in each dimension we want
>
On 09/06, Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
> > delinearizing and/or normalizing the color space before applying a 3D
> > LUT. Add pre-defined transfer function to enable delinearizing content
> >
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-10 12:03, Melissa Wen wrote:
> > From: Joshua Ashton
> >
> > Need to funnel the color caps through to these functions so it can check
> > that the hardware is capable.
> >
> > v2:
> > - remove redundant color caps assignment on plane degamma map
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-25 10:18, Melissa Wen wrote:
> > On 08/22, Pekka Paalanen wrote:
> >> On Thu, 10 Aug 2023 15:02:47 -0100
> >> Melissa Wen wrote:
> >>
> >>> Instead of relying on color block names to get the transfer function
> >>> intention regarding encoding pix
On 09/06, Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > From: Harry Wentland
> >
> > The region and segment calculation was incapable of dealing
> > with regions of more than 16 segments. We first fix this.
> >
> > Now that we can support regions up to 256 elements we can
>
On 2023-09-08 10:11, Melissa Wen wrote:
On 09/06, Harry Wentland wrote:
On 2023-08-10 12:02, Melissa Wen wrote:
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to
On Fri, 8 Sep 2023 15:56:51 +0200
Thomas Zimmermann wrote:
> Hi
>
> Am 08.09.23 um 13:16 schrieb Pekka Paalanen:
> > On Fri, 8 Sep 2023 11:21:51 +0200
> > Thomas Zimmermann wrote:
> >
> >> Hi
> >>
> >> Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
> >> [...]
> >>> + *
> >>> + * But the
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-10 12:03, Melissa Wen wrote:
> > Plane CTM for pre-blending color space conversion. Only enable
> > driver-specific plane CTM property on drivers that support both pre- and
> > post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
> >
On 9/8/23 13:13, Thomas Hellström wrote:
On 9/8/23 11:14, Christian König wrote:
Am 08.09.23 um 11:04 schrieb Thomas Hellström:
On 9/8/23 10:52, Christian König wrote:
Am 08.09.23 um 09:37 schrieb Thomas Hellström:
Hi,
On 9/7/23 16:49, Christian König wrote:
Am 07.09.23 um 16:47 schrieb
On 2023-09-08 10:41, Melissa Wen wrote:
On 09/06, Harry Wentland wrote:
On 2023-08-10 12:03, Melissa Wen wrote:
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DC
On 08/09/2023 15:56, Thomas Zimmermann wrote:
Hi
Am 08.09.23 um 13:16 schrieb Pekka Paalanen:
On Fri, 8 Sep 2023 11:21:51 +0200
Thomas Zimmermann wrote:
Hi
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * But there are two exceptions only for dumb buffers:
+ * * To suppo
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-10 12:03, Melissa Wen wrote:
> > Map the plane CTM driver-specific property to DC plane, instead of DC
> > stream. The remaining steps to program DPP block are already implemented
> > on DC shared-code.
> >
> > Signed-off-by: Melissa Wen
> > ---
On 09/06, Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > Hi all,
> >
> > Here is the next version of our work to enable AMD driver-specific color
> > management properties [1][2]. This series is a collection of
> > contributions from Joshua, Harry, and me to enhance the AMD KM
From: Yifan Zhang
Dropping bit 31:4 of page table base is wrong, it makes page table
base points to wrong address if phys addr is beyond 64GB; dropping
page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup
will do that. Also, while we are at it, cleanup the assignments using
upper_3
This reverts commit 5b7a256c982636ebc4f16b708b40ff56d33c8a86.
Since, we now have an actual fix for this issue, we can get rid of this
workaround as it can cause pin failures if enough VRAM isn't carved out
by the BIOS.
Cc: sta...@vger.kernel.org # 6.1+
Signed-off-by: Hamza Mahfooz
---
v2: new to
This is an early RFC set for a color pipeline API, along with a
sample implementation in VKMS. All the key API bits are here, but
I would like to show a larger variety of colorop types, as well
as examples of different possible color pipelines for a given plane.
The first patch is a doc patch that
Add a read-only TYPE property. The TYPE specifies the colorop
type, such as enumerated curve, 1D LUT, CTM, 3D LUT, PWL LUT,
etc.
For now we're only introducing an enumerated 1D LUT type to
illustrate the concept.
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Jonas Ådahl
Cc: Sebastian Wick
Cc: Shashank Sharma
Cc: Alexander Goins
Cc: Joshua Ashton
Cc: Michel Dänzer
Cc: Aleix Pol
Cc: Xaver Hugl
Cc: Victoria Brekenfeld
Cc:
This patches introduces a new drm_colorop mode object. This
object represents color transformations and can be used to
define color pipelines.
We also introduce the drm_colorop_state here, as well as
various helpers and state tracking bits.
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pe
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Jonas Ådahl
Cc: Sebastian Wick
Cc: Shashank Sharma
Cc: Alexander Goins
Cc: Joshua Ashton
Cc: Michel Dänzer
Cc: Aleix Pol
Cc: Xaver Hugl
Cc: Victoria Brekenfeld
Cc:
We'll construct color pipelines out of drm_colorop by
chaining them via the NEXT pointer. NEXT will point to
the next drm_colorop in the pipeline, or by 0 if we're
at the end of the pipeline.
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Cc: Harry Wentland
C
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Jonas Ådahl
Cc: Sebastian Wick
Cc: Shashank Sharma
Cc: Alexander Goins
Cc: Joshua Ashton
Cc: Michel Dänzer
Cc: Aleix Pol
Cc: Xaver Hugl
Cc: Victoria Brekenfeld
Cc:
We want to be able to bypass each colorop at all times.
Introduce a new BYPASS boolean property for this.
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Jonas Ådahl
Cc: Sebastian Wick
Cc: Shashank Sharma
Cc: Alexande
Since we created a new DRM object we need new IOCTLs (and
new libdrm functions) to retrieve those objects.
TODO: Can we make these IOCTLs and libdrm functions generic
to allow for new DRM objects in the future without the need
for new IOCTLs and libdrm functions?
Signed-off-by: Harry Wentland
Cc
Signed-off-by: Harry Wentland
Cc: Ville Syrjala
Cc: Pekka Paalanen
Cc: Simon Ser
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Jonas Ådahl
Cc: Sebastian Wick
Cc: Shashank Sharma
Cc: Alexander Goins
Cc: Joshua Ashton
Cc: Michel Dänzer
Cc: Aleix Pol
Cc: Xaver Hugl
Cc: Victoria Brekenfeld
Cc:
We're adding a new enum COLOR PIPELINE property. This
property will have entries for each COLOR PIPELINE by
referencing the DRM object ID of the first drm_colorop
of the pipeline. 0 disables the entire COLOR PIPELINE.
Userspace can use this to discover the available color
pipelines, as well as set
https://bugzilla.kernel.org/show_bug.cgi?id=217889
Bug ID: 217889
Summary: WARNING: CPU: 0 PID: 5172 at
drivers/gpu/drm/ttm/ttm_bo.c:362
ttm_bo_release+0x309/0x330 [ttm] after resolution
change
Product:
Series is
Acked-by: Harry Wentland
Harry
On 2023-09-08 10:55, Hamza Mahfooz wrote:
This reverts commit 5b7a256c982636ebc4f16b708b40ff56d33c8a86.
Since, we now have an actual fix for this issue, we can get rid of this
workaround as it can cause pin failures if enough VRAM isn't carved out
by t
Series is:
Reviewed-by: Alex Deucher
On Fri, Sep 8, 2023 at 10:56 AM Hamza Mahfooz wrote:
>
> From: Yifan Zhang
>
> Dropping bit 31:4 of page table base is wrong, it makes page table
> base points to wrong address if phys addr is beyond 64GB; dropping
> page_table_start/end bit 31:4 is unnecess
Hi
Am 08.09.23 um 16:41 schrieb Pekka Paalanen:
On Fri, 8 Sep 2023 15:56:51 +0200
Thomas Zimmermann wrote:
Hi
Am 08.09.23 um 13:16 schrieb Pekka Paalanen:
On Fri, 8 Sep 2023 11:21:51 +0200
Thomas Zimmermann wrote:
Hi
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * Bu
The patch series contains improvements, enabling new ci jobs which
enables testing for Mediatek MT8173, Qualcomm APQ 8016 and VirtIO GPU,
fixing issues with the ci jobs and updating the expectation files.
This series is intended for drm branch topic/drm-ci.
v2:
- Use fdtoverlay command to merge
/sys/kernel/debug/dri/*/state exist for every atomic KMS driver.
We do not test non-atomic drivers, so remove the todo.
Signed-off-by: Vignesh Raman
---
v2:
- No changes
v3:
- No changes
---
drivers/gpu/drm/ci/igt_runner.sh | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/
Due to the presence of the fastboot micro cable in the CI farm,
it causes the hardware to remain in gadget mode instead of host mode.
So it doesn't find the network, which results in failure to mount root
fs via NFS.
Add an overlay dtso file that sets the dr_mode to host, allowing
the USB controll
Force db410c to host mode to fix network issue which results in failure
to mount root fs via NFS.
See
https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/cb72a629b8c15c80a54dda510743cefd1c4b65b8
Compile the base device tree with overlay support and use fdtoverlay
command to merge base device tre
Update ci variables to fix the below error,
ERROR - Igt error: malloc(): corrupted top size
ERROR - Igt error: Received signal SIGABRT.
ERROR - Igt error: Stack trace:
ERROR - Igt error: #0 [fatal_sig_handler+0x17b]
Signed-off-by: Vignesh Raman
---
v2:
- No changes
v3:
- No changes
---
d
Enable CONFIG_REGULATOR_DA9211=y to fix mt8173 boot issue.
Signed-off-by: Vignesh Raman
---
v2:
- No changes
v3:
- Remove CONFIG_RTC_DRV_MT6397=y as it is already enabled in defconfig
---
drivers/gpu/drm/ci/arm64.config | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/c
Mediatek mt8173 board fails to boot with DA9211 regulator disabled.
Enabling CONFIG_REGULATOR_DA9211=y in drm-ci fixes the issue.
So enable it in the defconfig since kernel-ci also requires it.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Vignesh Raman
---
v3:
- New patch in the
Update amdgpu-stoney-fails, mediatek-mt8173-flakes,
mediatek-mt8173-fails, rockchip-rk3399-fails, rockchip-rk3399-flakes,
rockchip-rk3288-flakes, i915-cml-fails, i915-cml-flakes,
msm-apq8016-flakes files.
Add tests that fail sometimes into the *-flakes file and tests
that are failing into the *-fa
Enable the following jobs, as the issues noted in the
TODO comments have been resolved. This will ensure that these jobs
are now included and executed as part of the CI/CD pipeline.
msm:apq8016:
TODO: current issue: it is not fiding the NFS root. Fix and remove this rule.
mediatek:mt8173:
TODO: c
Instead of modifying files in git to enable/disable
configs, use scripts/config on the .config file which
will be used for building the kernel.
Suggested-by: Jani Nikula
Signed-off-by: Vignesh Raman
---
v2:
- Added a new patch in the series to use scripts/config to enable/disable
configs
v3
Hi
Am 08.09.23 um 16:48 schrieb Jocelyn Falempe:
On 08/09/2023 15:56, Thomas Zimmermann wrote:
Hi
Am 08.09.23 um 13:16 schrieb Pekka Paalanen:
On Fri, 8 Sep 2023 11:21:51 +0200
Thomas Zimmermann wrote:
Hi
Am 25.08.23 um 16:04 schrieb Jocelyn Falempe:
[...]
+ *
+ * But there are two e
https://bugzilla.kernel.org/show_bug.cgi?id=217889
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Reso
Reading fence timestamp always need to check the corresponding flag bit
before to make sure the write is actually visible, otherwise we can read
garbage here.
Fixes: 1774baa64f93 ("drm/scheduler: Change scheduled fence track v2")
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/scheduler/sched_mai
It's certainly possible that for large resolutions a single DPU SSPP
cannot process the image without exceeding the MDP clock limits but
it can still process it in multirect mode because the source rectangles
will get divided and can fall within the MDP clock limits.
If the SSPP cannot process the
Currently, dpu_plane_atomic_check() does not check whether the
plane can process the image without exceeding the per chipset
limits for MDP clock. This leads to underflow issues because the
SSPP is not able to complete the processing for the data rate of
the display.
Fail the dpu_plane_atomic_chec
On Thu, Sep 07, 2023 at 03:44:39AM +, Lin, Wayne wrote:
> [AMD Official Use Only - General]
>
> > -Original Message-
> > From: Imre Deak
> > Sent: Friday, August 25, 2023 9:56 PM
> > To: Lin, Wayne
> > Cc: dri-devel@lists.freedesktop.org; amd-...@lists.freedesktop.org;
> > ly...@redh
From: Marek Vasut
[ Upstream commit 362fa8f6e6a05089872809f4465bab9d011d05b3 ]
This bridge seems to need the HSE packet, otherwise the image is
shifted up and corrupted at the bottom. This makes the bridge
work with Samsung DSIM on i.MX8MM and i.MX8MP.
Signed-off-by: Marek Vasut
Reviewed-by: S
From: Ralph Campbell
[ Upstream commit 98d4cb705bc00afd4a9a71cc1e84f7111682639a ]
The OSVR virtual reality headset HDK 2.0 uses a different EDID
vendor and device identifier than the HDK 1.1 - 1.4 headsets.
Add the HDK 2.0 vendor and device identifier to the quirks table so
that window managers
From: Marek Vasut
[ Upstream commit 14806c6415820b1c4bc317655c40784d050a2edb ]
Wait until the command transfer FIFO is empty before loading in the next
command. The previous behavior where the code waited until command transfer
FIFO was not full suffered from transfer corruption, where the last
From: Philip Yang
[ Upstream commit bf80d34b6c58ad1c4f76067ecd460a148eab9d39 ]
Retry faults are delegated to soft IH ring and then processed by
deferred worker. Current soft IH ring size PAGE_SIZE can store 128
entries, which may overflow and drop retry faults, causes HW stucks
because the retry
From: George Shen
[ Upstream commit 974764180838516f80a13257da67a1ec6afb87d4 ]
[Why]
Current BW calculations do not account for the additional padding added
for uncompressed pixel-to-symbol packing.
This results in X.Y being too low for 128b/132b SST streams in certain
scenarios. If X.Y is too
From: Lijo Lazar
[ Upstream commit 6cb209ed68e45c8e4b71d97a037ac6b7dbce9b50 ]
Not all rings have scheduler associated. Only update scheduler data for
rings with scheduler. It could result in out of bound access as total
rings are more than those associated with particular IPs.
Signed-off-by: Li
From: Martin Tsai
[ Upstream commit 6917b0b711713b9d84d7e0844e9aa613997a51b2 ]
[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Ma
From: Leo Ma
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by:
From: Maíra Canal
[ Upstream commit a0e6a017ab56936c0405fe914a793b241ed25ee0 ]
Currently, it is possible for the composer to be set as enabled and then
as disabled without a proper call for the vkms_vblank_simulate(). This
is problematic, because the driver would skip one CRC output, causing CRC
Hey Harry,
Thank you and Simon for this great document. Really happy about it, but
obviously I've got a few notes and questions inline.
On Fri, Sep 08, 2023 at 11:02:26AM -0400, Harry Wentland wrote:
> Signed-off-by: Harry Wentland
> Cc: Ville Syrjala
> Cc: Pekka Paalanen
> Cc: Simon Ser
> Cc
From: Austin Zheng
[ Upstream commit 4a30cc2bd281fa176a68b5305cd3695d636152ad ]
[Why]
Flash of corruption observed when UCLK switching after transitioning
from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config
Scenario where DPREFCLK is required instead of DTBCLK is not expected
[How]
Always
From: Leo Chen
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
Sign
From: Leo Chen
[ Upstream commit 4c6107a653ccf361cb1b6ba35d558a1a5e6e57ac ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN314 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
Sig
From: Alvin Lee
[ Upstream commit 2b1b838ea8e5437ef06a29818d16e9efdfaf0037 ]
[Description]
In overclocking scenarios the max memclk could be higher
than the DC mode limit. However, for configs that don't
support MCLK switching we need to set the max memclk to
the overclocked max instead of the D
From: Rob Clark
[ Upstream commit 459f9e26e7d49f80f587d7592ccb78e00ab458e4 ]
Rather than just open coding a list of gpu-id matches.
Signed-off-by: Rob Clark
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Patchwork: https://patchwork.freedesktop.org/patch/549764/
Signed-off-by: Sash
From: Rob Clark
[ Upstream commit 155668ef412fc82ff3172666831d95770141cdd6 ]
It is better to explicitly list it. With the move to opaque chip-id's
for future devices, we should avoid trying to infer things like
generation from the numerical value.
Signed-off-by: Rob Clark
Reviewed-by: Konrad
From: Tuo Li
[ Upstream commit 2e63972a2de14482d0eae1a03a73e379f1c3f44c ]
The variable crtc->state->event is often protected by the lock
crtc->dev->event_lock when is accessed. However, it is accessed as a
condition of an if statement in exynos_drm_crtc_atomic_disable() without
holding the lock:
From: AngeloGioacchino Del Regno
[ Upstream commit fd70e2019bfbcb0ed90c5e23839bf510ce6acf8f ]
Change logging from drm_{err,info}() to dev_{err,info}() in functions
mtk_dp_aux_transfer() and mtk_dp_aux_do_transfer(): this will be
essential to avoid getting NULL pointer kernel panics if any kind
o
From: Marek Vasut
[ Upstream commit 362fa8f6e6a05089872809f4465bab9d011d05b3 ]
This bridge seems to need the HSE packet, otherwise the image is
shifted up and corrupted at the bottom. This makes the bridge
work with Samsung DSIM on i.MX8MM and i.MX8MP.
Signed-off-by: Marek Vasut
Reviewed-by: S
From: Ralph Campbell
[ Upstream commit 98d4cb705bc00afd4a9a71cc1e84f7111682639a ]
The OSVR virtual reality headset HDK 2.0 uses a different EDID
vendor and device identifier than the HDK 1.1 - 1.4 headsets.
Add the HDK 2.0 vendor and device identifier to the quirks table so
that window managers
From: Marek Vasut
[ Upstream commit 14806c6415820b1c4bc317655c40784d050a2edb ]
Wait until the command transfer FIFO is empty before loading in the next
command. The previous behavior where the code waited until command transfer
FIFO was not full suffered from transfer corruption, where the last
From: George Shen
[ Upstream commit 974764180838516f80a13257da67a1ec6afb87d4 ]
[Why]
Current BW calculations do not account for the additional padding added
for uncompressed pixel-to-symbol packing.
This results in X.Y being too low for 128b/132b SST streams in certain
scenarios. If X.Y is too
From: Martin Tsai
[ Upstream commit 6917b0b711713b9d84d7e0844e9aa613997a51b2 ]
[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Ma
From: Leo Ma
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by:
From: Maíra Canal
[ Upstream commit a0e6a017ab56936c0405fe914a793b241ed25ee0 ]
Currently, it is possible for the composer to be set as enabled and then
as disabled without a proper call for the vkms_vblank_simulate(). This
is problematic, because the driver would skip one CRC output, causing CRC
From: Austin Zheng
[ Upstream commit 4a30cc2bd281fa176a68b5305cd3695d636152ad ]
[Why]
Flash of corruption observed when UCLK switching after transitioning
from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config
Scenario where DPREFCLK is required instead of DTBCLK is not expected
[How]
Always
From: Leo Chen
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
Sign
From: Tuo Li
[ Upstream commit 2e63972a2de14482d0eae1a03a73e379f1c3f44c ]
The variable crtc->state->event is often protected by the lock
crtc->dev->event_lock when is accessed. However, it is accessed as a
condition of an if statement in exynos_drm_crtc_atomic_disable() without
holding the lock:
1 - 100 of 144 matches
Mail list logo
