The first patch ensures that the mappings needed for handling mmap
operation would be managed by using the pfn instead of struct page.
The second patch restores support for mapping hugetlb pages where
subpages of a hugepage are not directly used anymore (main reason
for revert) and instead the huge
A user or admin can configure a VMM (Qemu) Guest's memory to be
backed by hugetlb pages for various reasons. However, a Guest OS
would still allocate (and pin) buffers that are backed by regular
4k sized pages. In order to map these buffers and create dma-bufs
for them on the Host, we first need to
Add VM_PFNMAP to vm_flags in the mmap handler to ensure that
the mappings would be managed without using struct page.
And, in the vm_fault handler, use vmf_insert_pfn to share the
page's pfn to userspace instead of directly sharing the page
(via struct page *).
Cc: David Hildenbrand
Cc: Daniel V
This patch series adds support for migrating pages associated with
a udmabuf out of the movable zone or CMA to avoid breaking features
such as memory hotunplug.
The first patch exports check_and_migrate_movable_pages() function
out of GUP so that the udmabuf driver can leverage it for page
migrati
For drivers that would like to migrate pages out of the movable
zone (or CMA) in order to pin them (longterm) for DMA, using
check_and_migrate_movable_pages() directly provides a convenient
option instead of duplicating similar checks (e.g, checking
the folios for zone, hugetlb, etc) and calling mi
Since udmabuf could potentially pin pages that may reside in the
movable zone or CMA and thereby break features such as memory
hotunplug, it makes sense to migrate the pages out of these
areas. In order to accomplish this, we note the mapping and the
index of each page and then call check_and_migra
Since the memfd pages associated with a udmabuf may be migrated
as part of udmabuf create, we need to verify the data coherency
after successful migration. The new tests added in this patch try
to do just that using 4k sized pages and also 2 MB sized huge
pages for the memfd.
Successful completion
iced that this patch has
been dropped from linux-next for some unknown reasons. I also cannot
find it in today's linux-next (next-20230817):
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/drivers/gpu/drm/bridge/samsung-dsim.c?h=next-20230817
Any idea what has happened?
On 8/14/2023 8:03 PM, Alex Deucher wrote:
On Mon, Aug 14, 2023 at 3:35 AM Arvind Yadav wrote:
This patch adds a function which will allow to
change the GPU power profile based on a submitted job.
This can optimize the power performance when the
workload is on.
A few minor comments inline bel
Hi,
this small series improves debugging the tc358767 driver by using dev_err_probe
for additional information (patch 1) and print IRQ debug output only if hotplug
status actually changed.
Best regards,
Alexander
Alexander Stein (2):
drm/bridge: tc358767: Use dev_err_probe
drm: bridge: tc358
The function calls preceding these returns can return -EPROBE_DEFER. So
use dev_err_probe to add some information to
/sys/kernel/debug/devices_deferred
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a
Currently the output the following output is printed upon each interrupt:
tc358767 1-000f: GPIO0:
This spams the kernel log while debugging an IRQ storm from the bridge.
Only print the debug output if the GPIO hotplug event actually happened.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/b
On 8/14/2023 9:35 PM, Shashank Sharma wrote:
Ah, Thanks for pointing that out Alex.
@Arvind, please refer to the patch
(https://patchwork.freedesktop.org/patch/504854/?series=109060&rev=4)
in previous series of SMU workload hints with UAPI (here:
https://patchwork.freedesktop.org/series/109
https://bugzilla.kernel.org/show_bug.cgi?id=217664
--- Comment #14 from popus_czy_to_ty (pentelja...@o2.pl) ---
after resume fan is spinning, tried to reconnect over ssh from client its not
possible.
tlp is not installed. biggest success it was when i played with drivers i was
able to backlight ke
On 8/14/2023 8:28 PM, Shashank Sharma wrote:
Hey Arvind,
On 14/08/2023 09:34, Arvind Yadav wrote:
This patch adds a function which will allow to
change the GPU power profile based on a submitted job.
This can optimize the power performance when the
workload is on.
Cc: Shashank Sharma
Cc: Ch
On Thu, Aug 10, 2023 at 06:33:09PM +0530, Ankit Nautiyal wrote:
> Separate out functions for getting maximum and minimum input BPC based
> on platforms, when DSC is used.
>
> v2: Use HAS_DSC macro instead of platform check while getting min input
> bpc. (Stan)
>
> Signed-off-by: Ankit Nautiyal
Hi,
this series improves the regmap usage by cleaning up current usage as well as
adding more registers to the list of volatile registers. SYSSTAT is added
to the list of precious registers as it is cleared upon read.
This series is based on [1].
Best regards,
Alexander
[1]
https://lore.kernel.
Using ranges it is easier to add more register where writing is not allowed,
especially for sequences of registers.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/t
Use the register names from the datasheet. No functional change intended.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm
These registers might change their value without any host write operation.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm/bridge/tc358767.c
index b56dd3861dc2a..f
This is the single register which clears its value upon read operation.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm/bridge/tc358767.c
index f1d9deabae39b.
Sort the list by the starting address to ease adding new entries.
No functional change intended.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm/bri
0x0510 is bigger than 0x50c, order them accordingly.
No functional change intended.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm/bridge/
While at it, also add missing register definitions. HDCP registers are
skipped as they are not named, range 0x0980 - 0x09ac.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/tc358767.c | 75 ++-
1 file changed, 74 insertions(+), 1 deletion(-)
diff --git a/dr
On Thu, Aug 17, 2023 at 01:18:12AM +0200, Karol Herbst wrote:
> do you have one of these? https://en.wikipedia.org/wiki/DMS-59
Ah, DMS == Dual Monitor Solution :-)
Yap, that's exactly what the GPU has. And the Y-cable is 2xDVI. It is
a Dell workstation and it came this way, meaning I haven't done
Add compatible for sam9x75 XLCD controller.
Signed-off-by: Manikandan Muralidharan
---
drivers/mfd/atmel-hlcdc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c
index 3c2414ba4b01..1daa7410468a 100644
--- a/drivers/mfd/atmel-hlcdc.c
+++ b
Add is_xlcdc flag in driver data to differentiate XLCDC and HLCDC code
within the atmel-hlcdc driver files.
Signed-off-by: Manikandan Muralidharan
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
This patch series aims to add support for XLCDC IP of sam9x7 SoC family
to the DRM subsystem.XLCDC IP has additional registers and new
configuration bits compared to the existing register set of HLCDC IP.
The new compatible string "microchip,sam9x75-xlcdc" is defined for sam9x75
variant of the sam9
Add support for Display Pixel Interface (DPI) Compatible Mode
support in atmel-hlcdc driver for XLCDC IP along with legacy
pixel mapping.DPI mode BIT is configured in LCDC_CFG5 register.
Signed-off-by: Manikandan Muralidharan
[durai.manicka...@microchip.com: update DPI mode bit using is_xlcdc fla
- XLCDC in SAM9X7 has different sets of registers and additional
configuration bits when compared to previous HLCDC IP. Read/write
operation on the controller registers is now separated using the
XLCDC status flag.
- HEO scaling, window resampling, Alpha blending, YUV-to-RGB
conversion in X
update the LCDC_HEOCFG30 and LCDC_HEOCFG31 registers of XLCDC IP which
supports vertical and horizontal scaling with Bilinear and Bicubic
co-efficients taps for Chroma and Luma componenets of the Pixel.
Signed-off-by: Manikandan Muralidharan
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2
Add the LCD controller layer definition and descriptor structure for
sam9x75 for the following layers,
- Base Layer
- Overlay1 Layer
- Overlay2 Layer
- High End Overlay
Signed-off-by: Manikandan Muralidharan
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 97
1 file chang
From: Durai Manickam KR
The register address of the XLCDC IP used in SAM9X7 SoC family
are different from the previous HLCDC.Defining those address
space with valid macros.
Signed-off-by: Durai Manickam KR
[manikanda...@microchip.com: Remove unused macro definitions]
Signed-off-by: Manikandan M
Add support for the following DPI mode if the encoder type
is DSI as per the XLCDC IP datasheet:
- 16BPPCFG1
- 16BPPCFG2
- 16BPPCFG3
- 18BPPCFG1
- 18BPPCFG2
- 24BPP
Signed-off-by: Manikandan Muralidharan
[durai.manicka...@microchip.com: update output format using is_xlcdc flag]
Signed-off-by: Dur
On Thu, 10 Aug 2023, Ankit Nautiyal wrote:
> This series is an attempt to address multiple issues with DSC,
> scattered in separate existing series.
I think it's a good idea to have one person manage the series, and
combine it all together, because it touches the same areas.
However, once you ha
On Thu, Aug 17, 2023 at 10:10 AM Borislav Petkov wrote:
>
> On Thu, Aug 17, 2023 at 01:18:12AM +0200, Karol Herbst wrote:
> > do you have one of these? https://en.wikipedia.org/wiki/DMS-59
>
> Ah, DMS == Dual Monitor Solution :-)
>
> Yap, that's exactly what the GPU has. And the Y-cable is 2xDVI.
On Thu, Aug 17, 2023 at 11:58 AM Karol Herbst wrote:
>
> On Thu, Aug 17, 2023 at 10:10 AM Borislav Petkov wrote:
> >
> > On Thu, Aug 17, 2023 at 01:18:12AM +0200, Karol Herbst wrote:
> > > do you have one of these? https://en.wikipedia.org/wiki/DMS-59
> >
> > Ah, DMS == Dual Monitor Solution :-)
On 08/08/2023 11:32, Sandor Yu wrote:
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
On Thu, Aug 17, 2023 at 12:00:47PM +0200, Karol Herbst wrote:
> btw, what would help is to know where `nvkm_uconn_uevent` actually
> fails, or rather, are you running into this "/* TODO: support DP IRQ
> on ANX9805 and remove this hack. */" condition?
Send me a diff, I'll run it here and catch out
https://bugzilla.kernel.org/show_bug.cgi?id=201847
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Reso
On Thu, Aug 17, 2023 at 12:11 PM Borislav Petkov wrote:
>
> On Thu, Aug 17, 2023 at 12:00:47PM +0200, Karol Herbst wrote:
> > btw, what would help is to know where `nvkm_uconn_uevent` actually
> > fails, or rather, are you running into this "/* TODO: support DP IRQ
> > on ANX9805 and remove this h
On 8/15/23 20:57, André Almeida wrote:
> From: Pekka Paalanen
>
> Specify how the atomic state is maintained between userspace and
> kernel, plus the special case for async flips.
>
> Signed-off-by: Pekka Paalanen
> Signed-off-by: André Almeida
[...]
> +An atomic commit with the flag DRM_MOD
On 8/17/23 12:37, Michel Dänzer wrote:
> On 8/15/23 20:57, André Almeida wrote:
>> From: Pekka Paalanen
>>
>> Specify how the atomic state is maintained between userspace and
>> kernel, plus the special case for async flips.
>>
>> Signed-off-by: Pekka Paalanen
>> Signed-off-by: André Almeida
>
Hi all,
To make reviewing and updating easier, I've chosen to split the previous
patchset[1] into the following three parts:
part 1: some cleanups and preparations
part 2: introduce new APIs and convert all shrinnkers to use these
part 3: implement lockless slab shrink
This series is the part 1
The following functions are only used inside the mm subsystem, so it's
better to move their declarations to the mm/internal.h file.
1. shrinker_debugfs_add()
2. shrinker_debugfs_detach()
3. shrinker_debugfs_remove()
Signed-off-by: Qi Zheng
Reviewed-by: Muchun Song
---
include/linux/shrinker.h
The mm/vmscan.c file is too large, so separate the shrinker-related
code from it into a separate file. No functional changes.
Signed-off-by: Qi Zheng
Reviewed-by: Muchun Song
---
mm/Makefile | 4 +-
mm/internal.h | 2 +
mm/shrinker.c | 709 +
The debugfs_remove_recursive() will wait for debugfs_file_put() to return,
so the shrinker will not be freed when doing debugfs operations (such as
shrinker_debugfs_count_show() and shrinker_debugfs_scan_write()), so there
is no need to hold shrinker_rwsem during debugfs operations.
Signed-off-by:
Currently, the synchronize_shrinkers() is only used by TTM pool. It only
requires that no shrinkers run in parallel.
After we use RCU+refcount method to implement the lockless slab shrink,
we can not use shrinker_rwsem or synchronize_rcu() to guarantee that all
shrinker invocations have seen an up
Currently, we maintain two linear arrays per node per memcg, which are
shrinker_info::map and shrinker_info::nr_deferred. And we need to resize
them when the shrinker_nr_max is exceeded, that is, allocate a new array,
and then copy the old array to the new array, and finally free the old
array by R
Buffer 'afmt_status' of size 6 could overflow, since index 'afmt_idx' is
checked after access.
Fixes: 5cc4e5fc293b ("drm/radeon: Cleanup HDMI audio interrupt handling for
evergreen")
Co-developed-by: Ivanov Mikhail
Signed-off-by: Konstantin Meskhidze
---
drivers/gpu/drm/radeon/evergreen.c | 7
On Tue, Aug 15, 2023 at 01:19:07PM +0300, Jani Nikula wrote:
> This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
>
> Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
> EDID detailed mode sync parsing. Unfortunately, there are quite a few
> displays out there that
Paul Menzel writes:
Hello Paul,
> Dear Linux folks,
>
>
> On the Dell OptiPlex 7021 with a dedicated Nvidia card, the monitor is
> only connect to that, Linux 6.1.39 does not display any messages, and
> the GRUB messages stay until the X.Org X Server starts.
>
It's a known issue. The Nvidia p
On Thu, 17 Aug 2023, Ville Syrjälä wrote:
> On Tue, Aug 15, 2023 at 01:19:07PM +0300, Jani Nikula wrote:
>> This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
>>
>> Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
>> EDID detailed mode sync parsing. Unfortunately
On Thu, 17 Aug 2023, Dirk Lehmann wrote:
> VESA Enhanced EDID Standard does not clearly describe how display
> panel vendors should setup the Sync Signal Defintions (bit 4 & 3) in
> the Detailed Timing Definition (relative offset 17, absolute offset
> 47h[+18]) for Digital Video Signal Interfaces
On 8/17/23 07:33, Christian König wrote:
Am 16.08.23 um 18:33 schrieb Danilo Krummrich:
On 8/16/23 16:59, Christian König wrote:
Am 16.08.23 um 14:30 schrieb Danilo Krummrich:
On 8/16/23 16:05, Christian König wrote:
Am 16.08.23 um 13:30 schrieb Danilo Krummrich:
Hi Matt,
On 8/11/23 04:31,
Hi
I've cherry-picked the patch into drm-misc-next-fixes, so it will show
up in upstream soon.
Am 11.08.23 um 13:36 schrieb Karolina Stolarek:
Satisfy MMU dependency when testing TTM with KUnit. This fixes
compilation errors on platforms that don't select this option
by default.
Signed-off-b
On 2023-07-13 20:13, Andrew Davis wrote:
This new export type exposes to userspace the SRAM area as a DMA-BUF Heap,
this allows for allocations of DMA-BUFs that can be consumed by various
DMA-BUF supporting devices.
Signed-off-by: Andrew Davis
---
Changes from v2:
- Make sram_dma_heap_alloca
Hi Dave and Daniel,
this is the PR for drm-misc-next-fixes.
Best regards
Thomas
drm-misc-next-fixes-2023-08-17:
Short summary of fixes pull:
* Add MMU dependency to TTM unit tests
* panel: Fix Innolux G156HCE-L01 LVDS clock
The following changes since commit a8b273a8fd9c88cee038ffdae05b7eca06
Am 17.08.23 um 13:13 schrieb Danilo Krummrich:
On 8/17/23 07:33, Christian König wrote:
[SNIP]
The hardware seems to work mostly the same for all vendors, but you
somehow seem to think that filling the ring is somehow beneficial
which is really not the case as far as I can see.
I think that'
These declarations are not implemented now, remove them.
Signed-off-by: Yue Haibing
---
drivers/gpu/drm/gma500/gma_display.h | 1 -
drivers/gpu/drm/gma500/psb_intel_drv.h | 14 --
2 files changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/gma500/gma_display.h
b/drivers/gpu/dr
Hi
Am 15.08.23 um 21:59 schrieb Rob Clark:
On Tue, Aug 15, 2023 at 12:23 PM Dave Airlie wrote:
Otherwise, there should be something like a drm-ci tree, from which you
can fetch the changes directly.
I asked for a pull request so that I could also merge it to msm-next
so that I can do CI th
Hi,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2023-08-17:
One EPROBE_DEFER handling fix for the JDI LT070ME05000, a timing fix for
the AUO G121EAN01 panel, an integer overflow and a memory leak fixes for
the qaic accel, a use-after-free fix for nouveau and a revert for an
alleged
Am 11.08.23 um 04:31 schrieb Matthew Brost:
Rather than call free_job and run_job in same work item have a dedicated
work item for each. This aligns with the design and intended use of work
queues.
I would rather say we should get completely rid of the free_job callback.
Essentially the job is
Hi Shashank,
Em 17/08/2023 03:41, Shashank Sharma escreveu:
Hello Andre,
On 15/08/2023 21:50, André Almeida wrote:
Instead of storing coredump information inside amdgpu_device struct,
move if to a proper separated struct and allocate it dynamically. This
will make it easier to further expand t
On 8/17/2023 3:19 PM, Jani Nikula wrote:
On Thu, 10 Aug 2023, Ankit Nautiyal wrote:
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
I think it's a good idea to have one person manage the series, and
combine it all together, because it tou
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is als
From: Jani Nikula
This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
EDID detailed mode sync parsing. Unfortunately, there are quite a few
displays out there that have bogus (zero) sync field that are broken by
th
VESA Enhanced EDID Standard does not clearly describe how display
panel vendors should setup the Sync Signal Defintions (bit 4 & 3) in
the Detailed Timing Definition (relative offset 17, absolute offset
47h[+18]) for Digital Video Signal Interfaces (bit 7 at offset 14h).
In practice many eDP panel
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is als
https://bugzilla.kernel.org/show_bug.cgi?id=201847
--- Comment #6 from Simon Fogliato (simonfogli...@gmail.com) ---
I copied my info and created an issue here:
https://gitlab.freedesktop.org/drm/nouveau/-/issues/256
--
You may reply to this email to add a comment.
You are receiving this mail b
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
Move the check for limiting compressed bits_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
v2: Fix typo in commit message. (Ankit)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file change
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
v2: Use HAS_DSC macro instead of platform check while getting min input
bpc. (Stan)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
driv
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: St
Use checks for src and sink limits before computing compressed bpp for
eDP.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 ++---
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/dr
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 5-6 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
v5: Added note for 2 PPC. (Stan)
Signed-off-by: Ankit Nautiyal
Re
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal
R
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2
Currently for testing an output format with DSC, we just force the
output format, without checking if it can be supported.
This also creates an issue where there is a PCON which might need to
convert from forced output format to the format to sink format.
Signed-off-by: Ankit Nautiyal
Reviewed-by
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/di
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
On 8/17/23 15:35, Christian König wrote:
Am 17.08.23 um 13:13 schrieb Danilo Krummrich:
On 8/17/23 07:33, Christian König wrote:
[SNIP]
The hardware seems to work mostly the same for all vendors, but you
somehow seem to think that filling the ring is somehow beneficial
which is really not the
Hi Dave and Daniel,
I'm covering for Tvrtko on this week's fixes flow.
These 3 patches were queued since last week, but I had hold
because I had some doubts about the CI results.
I have confirmed those issues were not related to these 3
patches, so, here they are.
drm-intel-fixes-2023-08-17:
- F
Supporting DP/USB-C can result in a chain of several transparent
bridges (PHY, redrivers, mux, etc). This results in drivers having
similar boilerplate code for such bridges.
Next, these drivers are susceptible to -EPROBE_DEFER loops: the next
bridge can either be probed from the bridge->attach ca
Define a helper for creating simple transparent bridges which serve the
only purpose of linking devices into the bridge chain up to the last
bridge representing the connector. This is especially useful for
DP/USB-C bridge chains, which can span across several devices, but do
not require any additio
Switch to using the new DRM_AUX_BRIDGE helper to create the
transparent DRM bridge device instead of handcoding corresponding
functionality.
Reviewed-by: Heikki Krogerus
Signed-off-by: Dmitry Baryshkov
---
drivers/usb/typec/mux/Kconfig | 2 +-
drivers/usb/typec/mux/nb7vpq904m.c | 44 ++---
Switch to using the new DRM_AUX_BRIDGE helper to create the
transparent DRM bridge device instead of handcoding corresponding
functionality.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig | 2 +-
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 44 ++---
Implement DisplayPort support for the Qualcomm RB5 platform.
Note: while testing this, I had link training issues with several
dongles with DP connectors. Other DisplayPort-USB-C dongles (with HDMI
or VGA connectors) work perfectly.
Dependencies: [1]
Soft-dependencies: [2], [3]
[1]
https://lore
Add the nb7vpq904m, onboard USB-C redriver / retimer.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 52 +++-
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/dts/qcom/qr
Declare the displayport controller present on the Qualcomm SM8250 SoC.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 89
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm825
Enable the onboard displayport controller, connect it to QMP PHY.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
i
Add displayport altmode declaration to the Type-C controller node to
enable DP altmode negotiation.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/
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