Am 10.08.23 um 00:50 schrieb Danilo Krummrich:
drm_exec_prepare_obj() and drm_exec_prepare_array() both reserve
dma-fence slots and hence a dma_resv_list without ever freeing it.
Make sure to call drm_gem_private_object_fini() for each GEM object
passed to drm_exec_prepare_obj()/drm_exec_prepare
Am 09.08.23 um 15:58 schrieb Yue Haibing:
Commit cd3a8a596214 ("drm/ttm: remove ttm_bo_(un)lock_delayed_workqueue")
removed the implementations but not the declarations.
Signed-off-by: Yue Haibing
Reviewed and pushed to drm-misc-next.
Thanks,
Christian.
---
include/drm/ttm/ttm_bo.h | 2 -
Am 08.08.23 um 11:51 schrieb Karolina Stolarek:
This series introduces KUnit[1] tests for TTM (Translation Table Manager)
subsystem, a memory manager used by graphics drivers to create and manage
memory buffers across different memory domains, such as system memory
or VRAM.
Unit tests implemente
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> The io_state variable in the vga_arb_write() function is declared with
> unsigned int type, while the vga_str_to_iostate() function takes 'int *'
> type. To keep them consistent, this patch replaceis the third argument of
> vga_str
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> Because there is no good way to get the mask member used to searching for
> devices that conform to a specific PCI class code, an application needs to
> process all PCI display devices can achieve its goal as follows:
This is mixi
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> The vga_update_device_decodes() function is not performance-critical.
> So drop the inline. This patch also makes the parameter consistent with
> the argument, using the 'unsigned int' type instead of the 'signed' type
> to store t
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> This patch replaces the leading space with a tab and removes the double
> blank line and fix various typos, no functional change.
>
> Reviewed-by: Andi Shyti
> Signed-off-by: Sui Jingfeng
> ---
> drivers/pci/vgaarb.c | 90 +++
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> 1) s/intereted/interested
> 2) s/hotplugable/hot-pluggable
>
> While at it, convert the comments to the conventional multi-line style,
> and rewrap to fill 78 columns.
>
> Fixes: deb2d2ecd43d ("PCI/GPU: implement VGA arbitration
Hi,
On Thu, 3 Aug 2023 at 23:04, Pintu Agarwal wrote:
>
> Hi,
>
> On Wed, 2 Aug 2023 at 15:17, Christoph Hellwig wrote:
> >
> > On Tue, Aug 01, 2023 at 10:39:04PM -0700, John Stultz wrote:
> > > So, forgive me, I've not had a chance to look into this, but my
> > > recollection was "reserved" is
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> In the vga_arbiter_notify_clients() function, the value of the 'new_state'
> variable will be 'false' on systems that have more than one VGA device.
> The value will be 'true' if there is only one VGA device or no VGA device
> at a
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
Changelog body is missing.
> Fixes: 934f992c763a ("drm/i915: Recognise non-VGA display devices")
> Signed-off-by: Sui Jingfeng
> ---
> drivers/pci/vgaarb.c | 15 ++-
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
Please add changelog text.
> Fixes: deb2d2ecd43d ("PCI/GPU: implement VGA arbitration on Linux")
> Signed-off-by: Sui Jingfeng
> ---
> drivers/pci/vgaarb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a
On 8/9/23 21:15, Marek Olšák wrote:
> On Wed, Aug 9, 2023 at 3:35 AM Michel Dänzer
> wrote:
>> On 8/8/23 19:03, Marek Olšák wrote:
>>> It's the same situation as SIGSEGV. A process can catch the signal,
>>> but if it doesn't, it gets killed. GL and Vulkan APIs give you a way
>>> to catch the GPU
Due to electrical and mechanical constraints in certain platform designs there
may be likely interference of relatively high-powered harmonics of the (G-)DDR
memory clocks with local radio module frequency bands used by Wifi 6/6e/7. To
mitigate possible RFI interference producers can advertise the
Due to electrical and mechanical constraints in certain platform designs
there may be likely interference of relatively high-powered harmonics of
the (G-)DDR memory clocks with local radio module frequency bands used
by Wifi 6/6e/7.
To mitigate this, AMD has introduced a mechanism that devices can
AMD has introduced an ACPI based mechanism to support WBRF for some
platforms with AMD dGPU + WLAN. This needs support from BIOS equipped
with necessary AML implementations and dGPU firmwares.
For those systems without the ACPI mechanism and developing solutions,
user can use/fall-back the generic
The newly added WBRF feature needs this interface for channel
width calculation.
Signed-off-by: Evan Quan
---
include/net/cfg80211.h | 8
net/wireless/chan.c| 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index
To support the WBRF mechanism, Wifi adapters utilized in the system must
register the frequencies in use(or unregister those frequencies no longer
used) via the dedicated calls. So that, other drivers responding to the
frequencies can take proper actions to mitigate possible interference.
Co-devel
Add those data structures to support Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
.../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 14 +-
.../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 14 +-
.../amd/pm/swsmu/inc/pmfw
With WBRF feature supported, as a driver responding to the frequencies,
amdgpu driver is able to do shadow pstate switching to mitigate possible
interference(between its (G-)DDR memory clocks and local radio module
frequency bands used by Wifi 6/6e/7).
Signed-off-by: Evan Quan
Reviewed-by: Mario
To protect PMFW from being overloaded.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 31 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/dr
Fulfill the SMU13.0.0 support for Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 +
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +
.../gpu/d
Fulfill the SMU13.0.7 support for Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
Hi
On Mon, Aug 07, 2023 at 03:45:15PM +0200, Jocelyn Falempe wrote:
> After discussions on IRC, the consensus is that the DRM drivers should
> not do software color conversion, and only advertise the supported formats.
> Update the doc accordingly so that the rule and exceptions are clear for
> ev
Add comments regarding new DRM_IVPU_PARAM_CAPABILITIES param.
Signed-off-by: Stanislaw Gruszka
---
include/uapi/drm/ivpu_accel.h | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/include/uapi/drm/ivpu_accel.h b/include/uapi/drm/ivpu_accel.h
index a58a14c9f2
Hi,
On Tue, Aug 08, 2023 at 11:02:45AM -0700, Nikita Zhandarovich wrote:
> Four hdmi_*_infoframe_init() functions that initialize different
> types of hdmi infoframes only return the default 0 value, contrary to
> their descriptions. Yet these functions are still unnecessarily checked
> against po
On Fri, Aug 4, 2023 at 11:07 PM Douglas Anderson wrote:
> As talked about in commit d2aacaf07395 ("drm/panel: Check for already
> prepared/enabled in drm_panel"), we want to remove needless code from
> panel drivers that was storing and double-checking the
> prepared/enabled state. Even if someon
On 01/08/2023 22.35, Nick Desaulniers wrote:
> I suspect it's possible to change the indirect goto into a direct goto
> with some further refactoring (macros can take block statements;
Well, with some somewhat subtle restrictions. C99, 6.10.3.11. "The
sequence of preprocessing tokens bounded by
Hi Dave and Daniel,
this is the PR for drm-misc-next; presumably the final one before
-rc6. Half of the patches update fbdev drivers to make them use the
provided helpers and macros. The big feature is nouveau's support
for tracking virtual memory on the GPU, which enables Vulkan sparse
binding an
On 09/08/2023 18:29, Simon Ser wrote:
Looks good to me.
Thanks for reviewing it.
Maybe the IN_FORMATS prop docs is a better place for this?
you mean to move it here ?:
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/drm_plane.c#L132
I don't have a preference since it's my f
I am seeing the following consistent crash at boot:
[ 61.211213][ T819] [drm] radeon kernel modesetting enabled.
[ 61.584870][ T819] vga_switcheroo: detected switching method
\_SB_.PCI0.GFX0.ATPX handle
[ 61.667507][ T819] ATPX version 1, functions 0x0033
[ 61.748228][ T819] gener
On Thu, 10 Aug 2023 05:35:02 -0400, "Valdis KlÄtnieks" said:
> I am seeing the following consistent crash at boot:
> Some quick digging indicates the most likely culprit is:
>
> commit cbd0606e6a776bf2ba10d4a6957bb7628c0da947
> Author: Srinivasan Shanmugam
> Date: Thu Jul 20 15:39:24 2023 +05
On Mon, Aug 07, 2023 at 12:46:46PM -0700, John Harrison wrote:
> On 8/3/2023 06:28, Andi Shyti wrote:
> > Hi John,
> >
> > On Wed, Aug 02, 2023 at 11:49:40AM -0700, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > It was noticed that if the very first 'stealing' request fai
On 10.08.2023 09:19, Christian König wrote:
Am 08.08.23 um 11:51 schrieb Karolina Stolarek:
This series introduces KUnit[1] tests for TTM (Translation Table Manager)
subsystem, a memory manager used by graphics drivers to create and manage
memory buffers across different memory domains, such as
'id' is an enum, thus cast of pointer on 64-bit compile test with W=1
causes:
lima_drv.c:387:13: error: cast to smaller integer type 'enum lima_gpu_id'
from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/lima/lima_drv.c | 2 +-
1 f
'type' is an enum, thus cast of pointer on 64-bit compile test with W=1
causes:
adv7511_drv.c:1214:19: error: cast to smaller integer type 'enum
adv7511_type' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/bridge/adv7511/adv75
Hi Krzysztof,
Thank you for the patch.
On Thu, Aug 10, 2023 at 11:59:22AM +0200, Krzysztof Kozlowski wrote:
> 'type' is an enum, thus cast of pointer on 64-bit compile test with W=1
> causes:
>
> adv7511_drv.c:1214:19: error: cast to smaller integer type 'enum
> adv7511_type' from 'const void
On 10/08/2023 09:45, Maxime Ripard wrote:
Hi
On Mon, Aug 07, 2023 at 03:45:15PM +0200, Jocelyn Falempe wrote:
After discussions on IRC, the consensus is that the DRM drivers should
not do software color conversion, and only advertise the supported formats.
Update the doc accordingly so that the
Am 10.08.23 um 03:57 schrieb Mina Almasry:
Changes in RFC v2:
--
The sticking point in RFC v1[1] was the dma-buf pages approach we used to
deliver the device memory to the TCP stack. RFC v2 is a proof-of-concept
that attempts to resolve this by implementing scatterlist support in
On Mon, Jul 24, 2023 at 1:04 PM Albert Esteve wrote:
>
>
> On Thu, Jul 20, 2023 at 9:32 PM Simon Ser wrote:
>
>> On Thursday, July 20th, 2023 at 21:28, Zack Rusin
>> wrote:
>>
>> > On Thu, 2023-07-20 at 09:07 +, Simon Ser wrote:
>> >
>> > > !! External Email
>> > >
>> > > On Thursday, July
Hello,
On 8/10/23 01:13, Maxime Ripard wrote:
> Hi,
>
> On Tue, Aug 08, 2023 at 11:02:45AM -0700, Nikita Zhandarovich wrote:
>> Four hdmi_*_infoframe_init() functions that initialize different
>> types of hdmi infoframes only return the default 0 value, contrary to
>> their descriptions. Yet thes
Hi,
On 2023/8/9 21:52, Ilpo Järvinen wrote:
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
From: Sui Jingfeng
Changelog body is missing.
I thought that probably the Fixes tag could be taken as the body of this commit,
since there are no warnings when I check the whole series with checkpatch.pl
Reviewed-by: Qiang Yu
On Thu, Aug 10, 2023 at 5:59 PM Krzysztof Kozlowski
wrote:
>
> 'id' is an enum, thus cast of pointer on 64-bit compile test with W=1
> causes:
>
> lima_drv.c:387:13: error: cast to smaller integer type 'enum lima_gpu_id'
> from 'const void *' [-Werror,-Wvoid-pointer-to-e
Hi,
On 2023/8/9 22:12, Ilpo Järvinen wrote:
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
From: Sui Jingfeng
1) s/intereted/interested
2) s/hotplugable/hot-pluggable
While at it, convert the comments to the conventional multi-line style,
and rewrap to fill 78 columns.
Fixes: deb2d2ecd43d ("PCI/
Use memdup_user_nul() helper instead of open-coding to simplify the code.
Signed-off-by: Ruan Jinjie
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adre
Hi,
On 2023/8/10 20:13, Ilpo Järvinen wrote:
On Thu, 10 Aug 2023, suijingfeng wrote:
On 2023/8/9 21:52, Ilpo Järvinen wrote:
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
From: Sui Jingfeng
Changelog body is missing.
I thought that probably the Fixes tag could be taken as the body of this
co
The encode_dma() function has some validation on in_trans->size but it
would be more clear to move those checks to find_and_map_user_pages().
The encode_dma() had two checks:
if (in_trans->addr + in_trans->size < in_trans->addr || !in_trans->size)
return -EINVAL;
The in_t
Abuse the vblank worker to make the changes as small as possible. We
need a way to sync flip_done, but if we wait on flip_done, all async
tests start failing.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_crtc.c| 21 ++--
drivers/gpu/drm/i915/display
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_cursor.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index b342fad180ca..ab25f019eda1 100644
--- a/driver
Hi,
On 2023/8/9 22:01, Ilpo Järvinen wrote:
On Wed, 9 Aug 2023, Sui Jingfeng wrote:
From: Sui Jingfeng
Because there is no good way to get the mask member used to searching for
devices that conform to a specific PCI class code, an application needs to
process all PCI display devices can ach
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 5-6 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
v2: Use HAS_DSC macro instead of platform check while getting min input
bpc. (Stan)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 35 +++--
1
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
v5: Added note for 2 PPC. (Stan)
Signed-off-by: Ankit Nautiyal
Re
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
driv
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
Reviewed-by:
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: St
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
Use checks for src and sink limits before computing compressed bpp for
eDP.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
registe
Currently for testing an output format with DSC, we just force the
output format, without checking if it can be supported.
This also creates an issue where there is a PCON which might need to
convert from forced output format to the format to sink format.
Signed-off-by: Ankit Nautiyal
Reviewed-by
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 ++---
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/dr
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal
R
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/di
On Mon, Aug 7, 2023 at 5:36 PM Frank Oltmanns wrote:
>
> Hi Icenowy,
>
> it is my understanding that you are the original author of the following
> patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
> branch. I assume it is because of merge conflicts as the part about
> setting the
Hi,
On 2023/7/20 20:39, Harshit Mogalapalli wrote:
There are two problems in lsdc_pixel_pll_setup()
1. If kzalloc() fails then call iounmap() to release the resources.
2. Both kzalloc and ioremap doesnot return error pointers on failure, so
using IS_ERR_OR_NULL() checks is a bit confusing a
On 8/10/2023 12:37 AM, Evan Quan wrote:
The newly added WBRF feature needs this interface for channel
width calculation.
Signed-off-by: Evan Quan
---
include/net/cfg80211.h | 8
net/wireless/chan.c| 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/n
On Thu, 10 Aug 2023, Wang Jinchao wrote:
> When CONFIG_PNP is not defined, i915 will fail to compile with error bellow:
> drivers/gpu/drm/i915/soc/intel_gmch.c:43:13: error: variable
> ‘mchbar_addr’ set but not used
> Fix it by surrounding variable declaration and assignment with ifdef
>
>
On 8/10/2023 2:07 AM, Stanislaw Gruszka wrote:
Add comments regarding new DRM_IVPU_PARAM_CAPABILITIES param.
Signed-off-by: Stanislaw Gruszka
---
include/uapi/drm/ivpu_accel.h | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/include/uapi/drm/ivpu_accel
On Thu, Aug 10, 2023 at 08:27:08AM -0600, Jeffrey Hugo wrote:
> On 8/10/2023 2:07 AM, Stanislaw Gruszka wrote:
> > Add comments regarding new DRM_IVPU_PARAM_CAPABILITIES param.
> >
> > Signed-off-by: Stanislaw Gruszka
> > ---
> > include/uapi/drm/ivpu_accel.h | 19 +--
> > 1 fi
On Thu, Aug 10, 2023 at 08:48:05AM +0200, Christian König wrote:
> Am 10.08.23 um 08:40 schrieb Boris Brezillon:
> > On Wed, 9 Aug 2023 08:37:55 -0700
> > Nathan Chancellor wrote:
> >
> > > Hi Christian,
> > >
> > > Can this be applied to drm-misc? Other drivers are starting to make use
> > > of
ShenZhen New Display Co., Limited is the manufacturer of the
NDS040480800-V3 LCD panel according the datasheet.
Signed-off-by: Luca Ceresoli
---
Changes in v2: none
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/de
Add a driver for the ILITEK ILI9806E 480x864 RGB LCD controller connected
over SPI, and implement the ShenZhen New Display Co NDS040480800-V3 480x800
panel.
Signed-off-by: Luca Ceresoli
---
Changes in v2:
- add ILI9806E_P1_DISCTRL1 bit description
---
MAINTAINERS
Add bindings for LCD panels based on the ILITEK ILI9806E RGB controller
connected over SPI and the "ShenZhen New Display Co NDS040480800-V3"
480x800 panel based on it.
Signed-off-by: Luca Ceresoli
---
Changes in v2:
- remove T: line form MAINTAINERS entry
- reference spi-peripheral-props.yaml
Hi everyone,
while working on i.MX6Q based board (arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts)
I noticed several warnings on dtbs_check. The first 5 patches should be pretty
much straight forward.
I'm not 100% sure on the sixth patch, as it might be affected by incorrect
compatible lists. Please ref
This property is defined in thermal-sensor.yaml. Reference this file and
constraint '#thermal-sensor-cells' to 0 for imx-thermal.
Fixes the warning:
arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dtb: tempmon:
'#thermal-sensor-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documen
Starting with commit 3e37c9d48f7a ("dt-bindings: hwmon: Convert lm75
bindings to yaml") 'national,lm75' has it's own dedicated (YAML) binding.
If kept in this file device specific properties as 'vs-supply' are
considered excessive. Remove compatible here so it can be checked with
more specific bind
Although defined in synopsys,dw-hdmi.yaml, they need to explicitly allowed
in fsl,imx6-hdmi.yaml. Fixes the warning:
arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dtb: hdmi@12: 'interrupts',
'reg' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/display
Since commit bad3db104f89 ("ARM: imx: source gpt per clk from OSC for
system timer") osc_per can be used for clocking the GPT which is not
scaled when entering low bus mode.
This clock source is available only on i.MX6Q (incl. i.MX6QP) and i.MX6DL.
Signed-off-by: Alexander Stein
---
Notes:
o
Currently the dtbs_check for imx6ul generates warnings like this:
['fsl,imx7d-gpt', 'fsl,imx6sx-gpt'] is too long
The driver has no special handling for fsl,imx7d-gpt, so fsl,imx6sx-gpt is
used. Therefore make imx7d GPT compatible to the imx6sx one to fix the
warning.
Signed-off-by: Alexander St
MAC address can be provided by a nvmem-cell, thus allow referencing a
source for the address. Fixes the warning:
arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dtb: ethernet@1: 'nvmem-cell-names',
'nvmem-cells' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/binding
On 8/10/2023 8:32 AM, Stanislaw Gruszka wrote:
On Thu, Aug 10, 2023 at 08:27:08AM -0600, Jeffrey Hugo wrote:
On 8/10/2023 2:07 AM, Stanislaw Gruszka wrote:
Add comments regarding new DRM_IVPU_PARAM_CAPABILITIES param.
Signed-off-by: Stanislaw Gruszka
---
include/uapi/drm/ivpu_accel.h | 19
On 8/10/23 06:31, Matthew Brost wrote:
On Thu, Aug 10, 2023 at 12:17:23AM +0200, Danilo Krummrich wrote:
With the current mental model every GPU scheduler instance represents
a single HW ring, while every entity represents a software queue feeding
into one or multiple GPU scheduler instances and
On Thu, Aug 10, 2023 at 08:04:24PM +0800, Ruan Jinjie wrote:
> Use memdup_user_nul() helper instead of open-coding to simplify the code.
>
> Signed-off-by: Ruan Jinjie
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
On 8/10/23 08:34, Christian König wrote:
Am 10.08.23 um 00:17 schrieb Danilo Krummrich:
With the current mental model every GPU scheduler instance represents
a single HW ring, while every entity represents a software queue feeding
into one or multiple GPU scheduler instances and hence into one o
On 8/10/23 00:37, Evan Quan wrote:
> diff --git a/Documentation/admin-guide/kernel-parameters.txt
> b/Documentation/admin-guide/kernel-parameters.txt
> index a1457995fd41..21f73a0bbd0b 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parame
Hello Rob,
On Wed, 9 Aug 2023 14:22:59 -0600
Rob Herring wrote:
> On Wed, Aug 9, 2023 at 10:53 AM Boris Brezillon
> wrote:
> >
> > I tried to Cc anyone that was involved in any development of the code
> > I picked from panfrost, so they can acknowledge the GPL2 -> MIT+GPL2
> > change. If I miss
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to 256 elements we can
define a better segment distribution for near-linear LUTs
for our maximum of 256 HW-supported point
Hi all,
Here is the next version of our work to enable AMD driver-specific color
management properties [1][2]. This series is a collection of
contributions from Joshua, Harry, and me to enhance the AMD KMS color
pipeline for Steam Deck/SteamOS by exposing additional pre-blending and
post-blending
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
-
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Reviewed-by: Harry Wentland
Reviewed-by: Liviu Dudau
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
driv
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Reviewed-by: Harry
Hook up driver-specific atomic operations for managing AMD color
properties. Create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`.
First add plane degamma LUT properties that means user-blob and its
size. We will add
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