On Fri, 21 Jul 2023, Alex Deucher wrote:
> On Fri, Jul 21, 2023 at 4:18 AM Ilpo Järvinen
> wrote:
> >
> > On Thu, 20 Jul 2023, Bjorn Helgaas wrote:
> >
> > > On Mon, Jul 17, 2023 at 03:04:57PM +0300, Ilpo Järvinen wrote:
> > > > Don't assume that only the driver would be accessing LNKCTL. ASPM
>
Hi,
On Wed, 2 Aug 2023 at 15:17, Christoph Hellwig wrote:
>
> On Tue, Aug 01, 2023 at 10:39:04PM -0700, John Stultz wrote:
> > So, forgive me, I've not had a chance to look into this, but my
> > recollection was "reserved" is the name we see on x86, but other names
> > are possibly provided via t
This series adds DPU support for Qualcomm SM7150 SoC.
Danila Tikhonov (2):
dt-bindings: display/msm: document DPU on SM7150
drm/msm/dpu: Add SM7150 support
.../bindings/display/msm/qcom,sm7150-dpu.yaml | 116
.../msm/disp/dpu1/catalog/dpu_5_2_sm7150.h| 277 ++
..
On 2023/8/3 16:52, Daniel Vetter wrote:
> On Thu, Aug 03, 2023 at 10:40:35AM +0200, Daniel Vetter wrote:
>> On Thu, Aug 03, 2023 at 10:09:39AM +0800, GUO Zihua wrote:
>>> fbcon_registered_fb and fbcon_num_registered_fb is not referred outside
>>> drivers/video/fbdev/core/fbcon.c, so make them stati
From: "baozhu.liu"
If komeda_pipeline_unbound_components() returns -EDEADLK,
it means that a deadlock happened in the locking context.
Currently, komeda is not dealing with the deadlock properly,producing the
following output when CONFIG_DEBUG_WW_MUTEX_SLOWPATH is enabled:
[ cut her
Add definitions for the display hardware used on the Qualcomm SM7150
platform.
Signed-off-by: Danila Tikhonov
---
.../msm/disp/dpu1/catalog/dpu_5_2_sm7150.h| 277 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
On 04/08/23 7:34 am, Nancy Lin (林欣螢) wrote:
> [You don't often get email from nancy@mediatek.com. Learn why this is
> important at https://aka.ms/LearnAboutSenderIdentification ]
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Hari,
>
On 03/08/23 3:18 pm, Nancy.Lin wrote:
> [You don't often get email from nancy@mediatek.com. Learn why this is
> important at https://aka.ms/LearnAboutSenderIdentification ]
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> fix Smatch static
From: "baozhu.liu"
If komeda_pipeline_unbound_components() returns -EDEADLK,
it means that a deadlock happened in the locking context.
Currently, komeda is not dealing with the deadlock properly,producing the
following output when CONFIG_DEBUG_WW_MUTEX_SLOWPATH is enabled:
[ cut her
So here too I add new sm7150_vig_sblk_0 and sm7150_vig_sblk_1 with v3lite?
static const struct dpu_sspp_sub_blks sm7150_vig_sblk_0 =
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_sub_blks sm7150_vig_sblk_1 =
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3LITE);
> +static con
1.org/0day-ci/archive/20230804/202308041431.xxkaxq8u-...@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce:
(https://download.01.org/0day-ci/archive/20230804/202308041431.xxkaxq8u-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new
On 04.08.23 08:39, Kasireddy, Vivek wrote:
Hi Alistair, David, Jason,
Right, the "the zero pages are changed into writable pages" in your
above comment just might not apply, because there won't be any
page
replacement (hopefully :) ).
If the page replacement does not happen when there are
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Signed-off-by: AngeloGioacchino Del Regno
Review
Changes in v10:
- Moved snippet from patch [7/15] to patch [6/15] as that was
intended to be there instead; fixes build issue for patch [6/15]
as pointed out by the kernel text robot (oops, sorry!)
Changes in v9:
- As per previous conversation with CK Hu, added a commit that
de-commoniz
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Note:
GAMMA should get enabled in between vblanks, but this requires many
efforts in order to make this happen, as that requires migrating al
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
Reviewed-by
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculation.
Signed-off-by: AngeloGioacchino De
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
While at it, also add a definition for LUT_BITS_DEFAULT.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
---
drivers/gpu/drm/med
In preparation for adding a 12-bits gamma support for the DISP_GAMMA
IP, remove the mtk_gamma_set_common() function and move the relevant
bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for
DISP_AAL: since the latter has no more support for gamma manipulation
(being moved to a differ
Add support for 12-bit gamma lookup tables and introduce the first
user for it: MT8195.
While at it, also reorder the variables in mtk_gamma_set_common()
and rename `lut_base` to `lut0_base` to improve readability.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
Reviewed-by:
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through in both DISP_GAMMA and DISP_AAL for gamma
setting.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jas
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
The mtk_disp_gamma structure was completely undocumented: add some
kerneldoc documentation to it.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp
Compress the entry for mediatek,mt8173-disp-aal, as it fits in one
line, and fix the style; while at it, also add the usual sentinel
comment to the last entry.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 7 ++
The kerneldoc for struct mtk_disp_aal was entirely wrong: rewrite it
to actually document the structure.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Sign
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
> The VCLK and VCLK_DIV clocks have supplementary bits.
>
> The VCLK has a "SOFT RESET" bit to toggle after the whole
> VCLK sub-tree rate has been set, this is implemented in
> the gate enable callback.
>
> The VCLK_DIV clocks as enable and re
Hi,
On Thu, Aug 03, 2023 at 08:01:37PM -0700, Randy Dunlap wrote:
> Three DRM bridge drivers select GENERIC_PHY_MIPI_DPHY when GENERIC_PHY
> might not be set. This causes Kconfig warnings and a build error.
>
> WARNING: unmet direct dependencies detected for GENERIC_PHY_MIPI_DPHY
> Depends on [
Hi Xiaoyong,
On 8/3/23 14:10, Xiaoyong Lu wrote:
Fix AV1 decoding failure when the iova is 36bit.
Before this fix, the decoder was accessing incorrect addresses with 36bit
iova tile buffer, leading to iommu faults.
Fixes: 2f5d0aef37c6 ("media: mediatek: vcodec: support stateless AV1 decoder")
No functional modification involved.
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:183 dpu_core_perf_crtc_check()
warn: inconsistent indenting.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6096
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/msm/disp/dpu1/d
Hi Marek,
On Thu, 3 Aug 2023 19:10:35 +0200
Marek Vasut wrote:
> On 8/3/23 17:06, Luca Ceresoli wrote:
> > Hi Marek,
> >
> > On Thu, 3 Aug 2023 16:25:37 +0200
> > Marek Vasut wrote:
> >
> >> On 8/3/23 16:23, Luca Ceresoli wrote:
> >>> Hi Marek,
> >>
> >> Hi,
> >>
> >>> On Mon, 31 Jul
On 04/08/2023 08:11, Sandor Yu wrote:
The ELD (EDID-Like Data) is not updated when the HDMI cable
is plugged into different HDMI monitors.
This is because the EDID is not updated in the HDMI HPD function.
As a result, the ELD data remains unchanged and may not reflect
the capabilities of the newl
On 02/08/2023 11:08, Dmitry Baryshkov wrote:
On Wed, 2 Aug 2023 at 11:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard 845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags:
- MIPI_DSI_MODE_VIDEO_NO_HSA
- MIPI_DSI_MO
Hi Marek,
On 03/08/2023 20:10, Marek Vasut wrote:
On 8/2/23 20:49, Rob Clark wrote:
On Wed, Aug 2, 2023 at 11:16 AM Dmitry Baryshkov
wrote:
Can we please end the argument, land the fix (this revert) for 6.5 and
work on the solution for 6.6 or 6.7?
Even if they were in-tree, breaking
Hi,
On Wed, 02 Aug 2023 10:52:22 +0200, Neil Armstrong wrote:
> This reverts commit [1] to fix display regression on the Dragonboard 845c
> (SDM845) devboard.
>
> There's a mismatch on the real action of the following flags:
> - MIPI_DSI_MODE_VIDEO_NO_HSA
> - MIPI_DSI_MODE_VIDEO_NO_HFP
> - MIPI_D
Hi,
On Fri, 04 Aug 2023 14:11:45 +0800, Sandor Yu wrote:
> The ELD (EDID-Like Data) is not updated when the HDMI cable
> is plugged into different HDMI monitors.
> This is because the EDID is not updated in the HDMI HPD function.
> As a result, the ELD data remains unchanged and may not reflect
>
Hi,
On 03/08/2023 22:13, Michael Riesch wrote:
Determine the orientation of the display based on the device tree and
propagate it.
Reviewed-by: Neil Armstrong
Signed-off-by: Michael Riesch
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 18 ++
1 file changed, 18 insert
Hi Michael,
On 18/07/2023 17:31, Michael Riesch wrote:
The ST7789V controller features support for the partial mode. Here,
the area to be displayed can be restricted in one direction (by default,
in vertical direction). This is useful for panels that are partial > occluded
by design. Add suppor
Hi Dave & Daniel,
Here goes the first drm-intel-gt-next PR for v6.6.
We have a fix for infinite GPU wait race condition found by CI,
then improved tweakability of RPS algo and fixes to GuC SLPC for
tuning the frequency behavior of the system.
OA report zeroing fix, Aux CCS invalidation fix on Ge
On 04/08/2023 09:33, Jerome Brunet wrote:
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
The VCLK and VCLK_DIV clocks have supplementary bits.
The VCLK has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.
The
On Thu, Aug 03, 2023 at 11:35:30AM +0200, Christian König wrote:
> Am 03.08.23 um 10:58 schrieb Daniel Vetter:
> > On Thu, 3 Aug 2023 at 10:53, Christian König
> > wrote:
> > > Am 01.08.23 um 22:50 schrieb Matthew Brost:
> > > > Add generic schedule message interface which sends messages to backe
On Fri, Jul 28, 2023 at 05:42:28PM -0400, Alex Deucher wrote:
> Hi Dave, Daniel,
>
> New stuff for 6.6.
>
> The following changes since commit 6725f33228077902ddac2a05e0ab361dee36e4ba:
>
> Merge tag 'drm-misc-next-fixes-2023-07-06' of
> git://anongit.freedesktop.org/drm/drm-misc into drm-next
Hi Wayne,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm/drm-next
linus/master v6.5-rc4 next-20230804]
[cannot apply to drm-intel/for-linux-next]
[If your patch is applied
Hi Rob,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Rob-Clark/PM-devfreq-Drop-unneed-locking-to-appease-lockdep/20230804-060505
base: git
Thank you for resolving this issue so quickly!
I've applied the patch locally and gone through the reproduction
steps. The kernel builds fine now.
Tested-by: Aleksandr Nogikh
On Fri, Aug 4, 2023 at 9:38 AM Guido Günther wrote:
>
> Hi,
> On Thu, Aug 03, 2023 at 08:01:37PM -0700, Randy Dunlap wr
Hi Neil,
On 8/4/23 10:41, Neil Armstrong wrote:
> Hi Michael,
>
> On 18/07/2023 17:31, Michael Riesch wrote:
>> The ST7789V controller features support for the partial mode. Here,
>> the area to be displayed can be restricted in one direction (by default,
>> in vertical direction). This is useful
When removing the core perf tune overrides, I also occasionaly removed the
initialisation of the clk_rate variable. Initialise it to 0 to let max()
correctly calculate the maximum of requested clock rates.
Reported-by: Dan Carpenter
Fixes: 6a4bc73915af ("drm/msm/dpu: drop separate dpu_core_perf_t
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
> Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
> SoCs, they are used to feed the VPU LCD Pixel encoder used for
> DSI display purposes.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/meson/g12a.c | 40
On 04/08/2023 11:59, Jerome Brunet wrote:
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
SoCs, they are used to feed the VPU LCD Pixel encoder used for
DSI display purposes.
Signed-off-by: Neil Armstrong
---
drivers/clk/me
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
> In order to setup the DSI clock, let's make the unused VCLK2 clock path
> configuration via CCF.
>
> The nocache option is removed from following clocks:
> - vclk2_sel
> - vclk2_input
> - vclk2_div
> - vclk2
> - vclk_div1
> - vclk2_div2_en
>
On Fri, Aug 4, 2023 at 4:47 AM Randy Dunlap wrote:
>
> On 8/3/23 19:42, Adam Ford wrote:
> > On Thu, Aug 3, 2023 at 9:37 PM Randy Dunlap wrote:
> >>
> >> On 8/3/23 19:26, Adam Ford wrote:
> >>> Where/how was the .config generated?
> >>>
> >>
> >> Aleksandr posted a link to the config file above.
d, 309 insertions(+), 118 deletions(-)
---
base-commit: b0e9267d4ccce9be9217337f4bc364ca24cf7f73
change-id: 20230804-tc358768-1b6949ef2e3d
Best regards,
--
Tomi Valkeinen
smatch reports:
drivers/gpu/drm/bridge/tc358768.c:223 tc358768_update_bits() error:
uninitialized symbol 'orig'.
Fix this by bailing out from tc358768_update_bits() if the
tc358768_read() produces an error.
Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Signed-off-by: Tomi Valkeinen
-
The driver has a few places where it does:
if (thing_is_enabled_in_config)
update_thing_bit_in_hw()
This means that if the thing is _not_ enabled, the bit never gets
cleared. This affects the h/vsyncs and continuous DSI clock bits.
Fix the driver to always update the bit.
Fixes: ff1ca63
As is quite common, some of TC358768's PLL register fields are to be
programmed with (value - 1). Specifically, the FBD and PRD, multiplier
and divider, are such fields.
However, what the driver currently does is that it considers that the
formula used for PLL rate calculation is:
RefClk * [(FBD
Simplify the code by capturing the priv->dev value to dev variable, and
use it.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c | 41 ---
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c
b/d
The Toshiba documentation talks about HSByteClk when referring to the
DSI HS byte clock, whereas the driver uses 'dsibclk' name. Also, in a
few places the driver calculates the byte clock from the DSI clock, even
if the byte clock is already available in a variable.
To align the driver with the do
The driver debug prints DSI related timings as raw register values in
hex. It is much more useful to see the "logical" value of the timing,
not the register value.
Change the prints to print the values separately, in case a single
register contains multiple values, and use %u to have it in a more
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c | 64 +++
1 file changed, 45 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c
b/drivers/gpu/drm/bridge/tc358768.c
index ea19de5509ed..a567f136ddc7 100644
--- a/dr
The tc358768_ns_to_cnt() is, most likely, supposed to do a div-round-up
operation, but it misses subtracting one from the dividend.
Fix this by just using DIV_ROUND_UP().
Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c
The driver defines TC358768_PRECISION as 1000, and uses "nsk" to refer
to clock periods. The original author does not remember where all this
came from. Effectively the driver is using picoseconds as the unit for
clock periods, yet referring to them by "nsk".
Clean this up by just saying the perio
The TC358768 documentation uses HFP, HBP, etc. values to deal with the
video mode, while the driver currently uses the DRM display mode
(htotal, hsync_start, etc).
Change the driver to convert the DRM display mode to struct videomode,
which then allows us to use the same units the documentation us
The DSI horizontal timing calculations done by the driver seem to often
lead to underflows or overflows, depending on the videomode.
There are two main things the current driver doesn't seem to get right:
DSI HSW and HFP, and VSDly. However, even following Toshiba's
documentation it seems we don't
: Add missing drm_bridge_attach call
drivers/gpu/drm/bridge/lontium-lt8912b.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
---
base-commit: b0e9267d4ccce9be9217337f4bc364ca24cf7f73
change-id: 20230804-lt8912b-9cbb79018632
Best regards,
--
Tomi Valkeinen
The driver calls lt8912_bridge_detach() from its lt8912_remove()
function. As the DRM core detaches bridges automatically, this leads to
calling lt8912_bridge_detach() twice. The code probably has tried to
manage the double-call with the 'is_attached' variable, but the driver
never sets the variabl
The driver does not call drm_bridge_attach(), which causes the next
bridge to not be added to the bridge chain. This causes the pipeline
init to fail when DRM_BRIDGE_ATTACH_NO_CONNECTOR is used.
Add the call to drm_bridge_attach().
Fixes: 30e2ae943c26 ("drm/bridge: Introduce LT8912B DSI to HDMI b
The lt8912b driver, in its bridge detach function, calls
drm_connector_unregister() and drm_connector_cleanup().
drm_connector_unregister() should be called only for connectors
explicitly registered with drm_connector_register(), which is not the
case in lt8912b.
The driver's drm_connector_funcs.
lt8912b only calls drm_bridge_hpd_enable() if it creates a connector and
the next bridge has DRM_BRIDGE_OP_HPD set. However, when calling
drm_bridge_hpd_disable() it misses checking if a connector was created,
calling drm_bridge_hpd_disable() even if HPD was nenver enabled. I don't
see any issues c
/gpu/drm/drm_framebuffer.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
---
base-commit: b0e9267d4ccce9be9217337f4bc364ca24cf7f73
change-id: 20230804-uninit-fixes-188f92d60ac3
Best regards,
--
Tomi Valkeinen
smatch reports:
drivers/gpu/drm/drm_file.c:967 drm_show_memory_stats() error: uninitialized
symbol 'supported_status'.
'supported_status' is only set in one code path. I'm not familiar with
the code to say if that path will always be ran in real life, but
whether that is the case or not, I think
smatch reports:
drivers/gpu/drm/drm_framebuffer.c:654 drm_mode_getfb2_ioctl() error:
uninitialized symbol 'ret'.
'ret' is possibly not set when there are no errors, causing the error
above. I can't say if that ever happens in real-life, but in any case I
think it is good to initialize 'ret' to 0
The driver depends on CONFIG_OF, so it is not necessary to use CONFIG_OF
and of_match_ptr() here, we remove them all.
Even for drivers that do not depend on CONFIG_OF, it's almost always
better to leave out the of_match_ptr(), since the only thing it can
possibly do is to save a few bytes of .text
On 8/3/23 17:52, Sebastian Wick wrote:
On Sun, Jul 30, 2023 at 12:51 AM Maíra Canal wrote:
After we flush the workqueue at the commit tale, we need to make sure
that no work is queued until we destroy the state. Currently, new work
can be queued in the workqueue, even after the commit tale, as
On Thu, Aug 3, 2023 at 10:01 PM Randy Dunlap wrote:
>
> Three DRM bridge drivers select GENERIC_PHY_MIPI_DPHY when GENERIC_PHY
> might not be set. This causes Kconfig warnings and a build error.
>
> WARNING: unmet direct dependencies detected for GENERIC_PHY_MIPI_DPHY
> Depends on [n]: GENERIC_
Fix indentation of the callbacks in struct drm_panel_funcs.
No functional changes.
Reviewed-by: Sebastian Reichel
Signed-off-by: Michael Riesch
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panel
Determine the orientation of the display based on the device tree and
propagate it.
Reviewed-by: Neil Armstrong
Reviewed-by: Sebastian Reichel
Signed-off-by: Michael Riesch
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 17 +
1 file changed, 17 insertions(+)
diff --git a
Hi all,
This series adds support for orientation specification in the device
tree to the Sitronix ST7789V panel driver.
This is can be seen as reduced version of [0] (some things of [0] have
been implemented in more general fashion in the scope of [1], other
things have been rejected).
Looking
The sitronix-st7789v driver now considers the rotation property.
Add the property to the documentation.
Acked-by: Conor Dooley
Reviewed-by: Sebastian Reichel
Signed-off-by: Michael Riesch
---
Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml | 2 ++
1 file changed, 2 insert
Hi Neil,
On 8/4/23 10:40, Neil Armstrong wrote:
> Hi,
>
> On 03/08/2023 22:13, Michael Riesch wrote:
>> Determine the orientation of the display based on the device tree and
>> propagate it.
>>
>> Reviewed-by: Neil Armstrong
>> Signed-off-by: Michael Riesch
>> ---
>> drivers/gpu/drm/panel/pan
Hi,
On Fri, 04 Aug 2023 13:23:07 +0200, Michael Riesch wrote:
> This series adds support for orientation specification in the device
> tree to the Sitronix ST7789V panel driver.
>
> This is can be seen as reduced version of [0] (some things of [0] have
> been implemented in more general fashion i
Hi!
On 02.08.23 23:28, Olaf Skibbe wrote:
> Dear Maintainers,
>
> Hereby I would like to report an apparent bug in the nouveau driver in
> linux/6.1.38-2.
Thx for your report. Maybe your problem is caused by a incomplete
backport. I Cced the maintainers for the drivers (and the regressions
and t
On Fri, Aug 4, 2023 at 2:02 PM Thorsten Leemhuis
wrote:
>
> Hi!
>
> On 02.08.23 23:28, Olaf Skibbe wrote:
> > Dear Maintainers,
> >
> > Hereby I would like to report an apparent bug in the nouveau driver in
> > linux/6.1.38-2.
>
> Thx for your report. Maybe your problem is caused by a incomplete
>
On Fri, Aug 04, 2023 at 06:39:22AM +, Kasireddy, Vivek wrote:
> No, adding HMM_PFN_REQ_WRITE still doesn't help in fixing the issue.
> Although, I do not have THP enabled (or built-in), shmem does not evict
> the pages after hole punch as noted in the comment in shmem_fallocate():
This is the
On Fri, Aug 4, 2023 at 2:48 PM Olaf Skibbe wrote:
>
> On Fri, 4 Aug 2023 at 14:15, Karol Herbst wrote:
>
> > mind retrying with only fb725beca62d and 62aecf23f3d1 reverted?
>
> I will do this later this day (takes some time, it is a slow machine).
>
> > Would be weird if the other two commits are
The commit c242f48433e7 ("drm: Make FB_CORE to be selected if DRM fbdev
emulation is enabled") changed DRM_FBDEV_EMULATION from 'depends on FB'
to an effective 'select FB_CORE', so any config that previously had DRM=y
and FB=n now has FB_CORE=y and FRAMEBUFFER_CONSOLE=y.
This leads to unmet direct
Javier Martinez Canillas writes:
> "Arnd Bergmann" writes:
>
> [adding Randy Dunlap who also reported the same issue]
>
> Hello Arnd,
>
>> On Thu, Jul 27, 2023, at 18:45, Javier Martinez Canillas wrote:
>>> Arthur Grillo Queiroz Cabral writes:
On 27/07/23 13:07, Javier Martinez Canillas wr
Add vendor prefix for Jasonic Technology Ltd., a manufacturer
of custom LCD panels.
Acked-by: Conor Dooley
Signed-off-by: Michael Riesch
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-pref
Hi all,
This series adds support for the partial display mode to the Sitronix
ST7789V panel driver. This is useful for panels that are partially
occluded by design, such as the Jasonic JT240MHQS-HWT-EK-E3. Support
for this particular panel is added as well.
Looking forward to your comments!
---
The Jasonic JT240MHQS-HWT-EK-E3 is a custom panel using the Sitronix
ST7789V controller. While the controller features a resolution of
320x240, only an area of 280x240 is visible by design.
Signed-off-by: Michael Riesch
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 29
The ST7789V controller features support for the partial mode. Here,
the area to be displayed can be restricted in one direction (by default,
in vertical direction). This is useful for panels that are partially
occluded by design. Add support for the partial mode.
Signed-off-by: Michael Riesch
---
Add compatible for the Jasonic Technology Ltd. JT240MHQS-HWT-EK-E3
display.
Acked-by: Conor Dooley
Signed-off-by: Michael Riesch
---
Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/displ
On Tue, Jun 27, 2023 at 10:23:23AM -0300, André Almeida wrote:
> Create a section that specifies how to deal with DRM device resets for
> kernel and userspace drivers.
>
> Acked-by: Pekka Paalanen
> Signed-off-by: André Almeida
> ---
>
> v4:
> https://lore.kernel.org/lkml/20230626183347.55118-
On 04/08/2023 15:02, Michael Riesch wrote:
The ST7789V controller features support for the partial mode. Here,
the area to be displayed can be restricted in one direction (by default,
in vertical direction). This is useful for panels that are partially
occluded by design. Add support for the part
On Fri, 4 Aug 2023 at 14:52, Javier Martinez Canillas
wrote:
>
> The commit c242f48433e7 ("drm: Make FB_CORE to be selected if DRM fbdev
> emulation is enabled") changed DRM_FBDEV_EMULATION from 'depends on FB'
> to an effective 'select FB_CORE', so any config that previously had DRM=y
> and FB=n
On 04/08/2023 15:02, Michael Riesch wrote:
The Jasonic JT240MHQS-HWT-EK-E3 is a custom panel using the Sitronix
ST7789V controller. While the controller features a resolution of
320x240, only an area of 280x240 is visible by design.
Signed-off-by: Michael Riesch
---
drivers/gpu/drm/panel/pane
On Wed, 2 Aug 2023 at 20:01, Jessica Zhang wrote:
>
> Drop vsync_event and vsync_event_work handlers as they are unnecessary.
> In addition drop the dpu_enc_ktime_template event class as it will be
> unused after the vsync_event handlers are dropped.
>
> Signed-off-by: Jessica Zhang
> ---
> Chang
On Fri, Jul 28, 2023 at 7:03 PM Jessica Zhang wrote:
>
> Add support for pixel_source property to drm_plane and related
> documentation. In addition, force pixel_source to
> DRM_PLANE_PIXEL_SOURCE_FB in DRM_IOCTL_MODE_SETPLANE as to not break
> legacy userspace.
>
> This enum property will allow u
1 - 100 of 193 matches
Mail list logo
