[adding Zack Rusin again who seems to have fallen from the Cc list]
Albert Esteve writes:
> On 6/10/22 10:59, Daniel Vetter wrote:
>> On Fri, Jun 10, 2022 at 10:41:05AM +0200, Daniel Vetter wrote:
[...]
>>> - third issue: These special virtual display properties arent documented.
>>>Aside
(I think this is the first cover letter I have ever written).
These patches are based on review and not from testing.
I found it quite complicated to track the buffer sizes. What happens
is the qaic_manage() gets a buffer user_msg->data[] which has
user_msg->len bytes. The qaic_manage() calls q
There are several issues in this code. The check at the start of the
loop:
if (user_len >= user_msg->len) {
This check does not ensure that we have enough space for the trans_hdr
(8 bytes). Instead the check needs to be:
if (user_len >= user_msg->len - sizeof(*trans_hdr)) {
Th
Copy the bounds checking from encode_message() to decode_message().
This patch addresses the following concerns. Ensure that there is
enough space for at least one header so that we don't have a negative
size later.
if (msg_hdr_len < sizeof(*trans_hdr))
Ensure that we have enough space
The encode_dma() function has integer overflow checks. The
encode_passthrough(), encode_activate() and encode_status() functions
did not. I added integer overflow checking everywhere. I also
updated the integer overflow checking in encode_dma() to use size_add()
so everything is consistent.
Fix
The integer overflow checking for find_and_map_user_pages() was done in
encode_dma(). Presumably this was to do it before the allocation. But
it's not super important that the failure path is a fast path and it
hurts readability to put the check so far from the where the variable is
used.
Move t
If get_user_pages_fast() allocates some pages but not as many as we
wanted, then the current code leaks those pages. Call put_page() on
the pages before returning.
Fixes: 129776ac2e38 ("accel/qaic: Add control path")
Signed-off-by: Dan Carpenter
---
drivers/accel/qaic/qaic_control.c | 7 +--
Some Android CTS is testing for that.
Signed-off-by: Christian König
CC: sta...@vger.kernel.org
---
drivers/dma-buf/dma-fence-unwrap.c | 11 +--
drivers/dma-buf/dma-fence.c| 5 +++--
drivers/gpu/drm/drm_syncobj.c | 2 +-
include/linux/dma-fence.h | 2 +-
4 files
Hi Lucas
>
> Instead of only tracking if the FE is running, use a enum to better
> describe the various states the GPU can be in. This allows some
> additional validation to make sure that functions that expect a
> certain GPU state are only called when the GPU is actually in that
> state.
>
> Sig
Hi,
On 2023/6/16 22:34, Alex Deucher wrote:
On Fri, Jun 16, 2023 at 10:22 AM Sui Jingfeng wrote:
On 2023/6/16 21:41, Alex Deucher wrote:
On Fri, Jun 16, 2023 at 3:11 AM Sui Jingfeng wrote:
Hi,
On 2023/6/16 05:11, Alex Deucher wrote:
On Wed, Jun 14, 2023 at 6:50 AM Sui Jingfeng wrote:
H
Hi Lucas
Am Mi., 7. Juni 2023 um 15:02 Uhr schrieb Lucas Stach :
>
> Now that it is only used to track the driver internal state of
> the MMU global and cmdbuf objects, we can get rid of this property
> by making the free/finit functions of those objects safe to call
> on an uninitialized object.
Hi Lucas
>
> The GPU is halted when it hits a MMU exception, so there is no point in
> waiting for the job timeout to expire or try to work out if the GPU is
> still making progress in the timeout handler, as we know that the GPU
> won't make any more progress.
>
> Signed-off-by: Lucas Stach
Rev
On Tue, 20 Jun 2023, André Almeida wrote:
> Implement get_reset ioctl for i915.
>
> Signed-off-by: André Almeida
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c| 18 ++
> drivers/gpu/drm/i915/gem/i915_gem_context.h| 2 ++
> .../gpu/drm/i915/gem/i915_gem_context_types
Am 21.06.23 um 02:57 schrieb André Almeida:
Implement get_reset ioctl for amdgpu
Well that pretty much won't work since the jobs are destroyed much later
than the contexts.
Christian.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-
drivers/gpu/drm/am
Am 21.06.23 um 02:57 schrieb André Almeida:
Hi,
This is a new version of the documentation for DRM device resets. As I dived
more in the subject, I started to believe that part of the problem was the lack
of a DRM API to get reset information from the driver. With an API, we can
better standardi
1. Fix build warning message in mtk_disp_ovl_adaptor.c
>> drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c:415:10:
warning: cast to smaller integer type 'enum mtk_ovl_adaptor_comp_type'
from 'const void *' [-Wvoid-pointer-to-enum-cast]
type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
On 16/06/2023 at 08:44, Manikandan M - I67131 wrote:
On 14/06/23 20:10, Nicolas Ferre wrote:
On 13/06/2023 at 20:21, Conor Dooley wrote:
On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote:
On 13/06/2023 09:04, Manikandan Muralidharan wrote:
Add new compatible string for the X
Hi
>
> From: Sui Jingfeng
>
> There is a Vivante GC1000 (v5037) in LS2K1000 and LS7A1000, this GPU is a
> PCI device, and it has 2D and 3D cores in the same core. This series is
> trying to add PCI device driver support to drm/etnaviv.
>
Is it possible to get the lspci output for the GPU? Someth
On Tue, Jun 20, 2023 at 12:33:28PM +0200, Thomas Zimmermann wrote:
> Dereference struct drm_device.dev_private in the helper function
> do_virtio_gpu_device(). The dev_private field is deprecated and
> drivers are advised not ot use it. Encapsulating it in a helper
> function will help with a later
On Tue, 20 Jun 2023 21:57:16 -0300
André Almeida wrote:
> Create a section that specifies how to deal with DRM device resets for
> kernel and userspace drivers.
>
> Signed-off-by: André Almeida
Hi André,
nice to see this! I ended up giving lots of grammar comments, but I'm
not a native speake
Am 20.06.23 um 17:55 schrieb Jeffrey Hugo:
On 6/20/2023 1:59 AM, Thomas Zimmermann wrote:
Unexport drm_gem_prime_fd_to_handle() and drm_gem_prime_handle_to_fd().
Both are only used internally within the PRIME code.
v2:
* reword docs as functions are now unexported (Simon)
Signed-off-by:
Hi
On 2023/6/21 15:55, Christian Gmeiner wrote:
Hi
From: Sui Jingfeng
There is a Vivante GC1000 (v5037) in LS2K1000 and LS7A1000, this GPU is a
PCI device, and it has 2D and 3D cores in the same core. This series is
trying to add PCI device driver support to drm/etnaviv.
Is it possible to
Am 20.06.23 um 12:33 schrieb Thomas Zimmermann:
Dereference struct drm_device.dev_private in the helper function
do_virtio_gpu_device(). The dev_private field is deprecated and
drivers are advised not ot use it. Encapsulating it in a helper
function will help with a later removal. No functional
Hi
Am 20.06.23 um 18:47 schrieb Laurent Pinchart:
Hi Thomas,
Thank you for the patch.
On Tue, Jun 20, 2023 at 02:03:21PM +0200, Thomas Zimmermann wrote:
Call __drm_gem_dma_create() to create an object for imported buffers,
instead of reimplementing the function within the driver. Reduces
cod
On Tue, Jun 20, 2023 at 06:47:36AM +, Jonas Karlman wrote:
> struct rockchip_crtc_state members such as output_type, output_bpc and
> enable_afbc is always reset to zero in the atomic_duplicate_state crtc
> funcs.
>
> Fix this by using kmemdup on the subclass rockchip_crtc_state struct.
>
> F
Hi,
Below is the gpu info cat from the debugfs,
I guess this is also what you want ?
[root@fedora 0]# cat gpu
:00:06.0 Status:
identity
model: 0x1000
revision: 0x5037
product_id: 0x0
customer_id: 0x0
eco_id: 0x0
features
major_features: 0xe0286eed
On Tue, Jun 20, 2023 at 06:47:37AM +, Jonas Karlman wrote:
> vop_plane_destroy and vop_crtc_destroy are plain wrappers around
> drm_plane_cleanup and drm_crtc_cleanup. Use them directly as plane and
> crtc funcs to closer match VOP2 driver.
>
> Signed-off-by: Jonas Karlman
Reviewed-by: Sasch
On Tue, Jun 20, 2023 at 06:47:38AM +, Jonas Karlman wrote:
> It's possible for users to try to duplicate the CRTC state even when the
> state doesn't exist. drm_atomic_helper_crtc_duplicate_state() (and other
> users of __drm_atomic_helper_crtc_duplicate_state()) already guard this
> with a WAR
On Tue, 20 Jun 2023 21:57:17 -0300
André Almeida wrote:
> Create a new DRM ioctl operation to get the numbers of resets for a
> given context. The numbers reflect just the resets that happened after
> the context was created, and not since the machine was booted.
>
> Create a debugfs interface t
Hello, this series is based on the RFC sent by Melssa Wen:
"[RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface"
https://lore.kernel.org/dri-devel/20230109143846.1966301-1-m...@igalia.com/
that introduces CRTC properties to control 3D LUT operations.
The R-Car DU peripheral has a post-blending colo
From: Alex Hung
A struct is defined for 3D LUT modes to be supported by hardware.
The elements includes lut_size, lut_stride, bit_depth, color_format
and flags.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hun
From: Melissa Wen
Add 3D LUT for gammar correction using a 3D lookup table. The position
in the color correction pipeline where 3D LUT is applied depends on hw
design, being after CTM or gamma. If just after CTM, a shaper lut must
be set to shape the content for a non-linear space. That details s
From: Melissa Wen
Shaper LUT is used to shape the content after blending, i.e.,
de-linearize or normalize space before applying a 3D LUT color
correction. In the next patch, we add 3D LUT property to DRM color
management after this shaper LUT and before the current gamma LUT.
Signed-off-by: Meli
From: Melissa Wen
DRM color function to create modes for lut3d mode property from an array
of drm_color_lut3d_mode modes supported by the HW and advertise to
userspace. Userspace can get the description of a specific mode in the
enum list from its blob data.
Signed-off-by: Melissa Wen
---
driv
From: Melissa Wen
If the driver supports user 3D LUT then it calls a drm function to
attach 3D LUT related properties according to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/drm_color_mgmt.c | 35
include/drm/drm_color_mgmt.h | 3 +++
2 files
Enable the 3D LUT in rcar_du_crtc by first creating a property for
the supported 3d lut modes and by calling the drm_crtc_enable_lut3d()
helper.
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_cmm.h | 14 ++
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 23 +++
From: Kieran Bingham
The CMM module provides a three-dimensional cubic look up table that
converts three-color-component data into desired three color components
by use of a lookup table.
While the 1D-LUT can only control each of three color components
separately, the 3D-CLU can be used for spec
From: Kieran Bingham
Link the DRM 3D-CLU configuration to the CMM setup configuration.
Signed-off-by: Kieran Bingham
Signed-off-by: Laurent Pinchart
Reviewed-by: Kieran Bingham
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 23 ++-
1 file change
From: Laurent Pinchart
To prepare for CLU support, expend the CMM API exposed to the DU driver
to separate the LUT table pointer from the LUT update decision. This
will be required, as we will need to update the LUT and CLU
independently.
Signed-off-by: Laurent Pinchart
Reviewed-by: Kieran Bing
On Tue, Jun 20, 2023 at 06:47:39AM +, Jonas Karlman wrote:
> Add missing call to crtc reset helper to properly vblank reset.
>
> Also move vop2_crtc_reset and call vop2_crtc_destroy_state to simplify
> and remove duplicated code.
>
> Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
> Sig
On 21/06/2023 04:23, Sandor Yu wrote:
>>> +
>>> +properties:
>>> + compatible:
>>> +enum:
>>> + - cdns,mhdp8501-dp
>>> + - cdns,mhdp8501-hdmi
>>> + - fsl,imx8mq-mhdp8501-dp
>>> + - fsl,imx8mq-mhdp8501-hdmi
>>
>> Is DP vs. HDMI fixed for a particular SoC implementation or it
Hi guys,
can I get a quick rb for this?
Going to add a Fixes tag before pushing.
Thanks,
Christian.
Am 21.06.23 um 09:57 schrieb Jessie Hao:
Hi Christian,
After applying the patch, the below android CTS cases can pass:
CtsDeqpTestCases dEQP-EGL.functional.get_frame_timestamps*
Thanks for taki
On 08/06/2023 12:12, AngeloGioacchino Del Regno wrote:
Instead of open coding calls to platform_get_resource() followed by
devm_ioremap_resource(), perform a single call to the helper
devm_platform_get_and_ioremap_resource().
This commit brings no functional changes.
Reviewed-by: Alexandre Mer
On Sun, Jun 18, 2023 at 10:50:43PM +0800, zhumao...@208suo.com wrote:
>
> Delete one of the rebundant word in comment.
>
> Signed-off-by: Zhu Mao
> ---
> drivers/dma-buf/heaps/cma_heap.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma-buf/heaps/cma_heap.c
>
On 6/20/23 20:07, Sumitra Sharma wrote:
On Tue, Jun 20, 2023 at 06:23:38AM -0700, Ira Weiny wrote:
Sumitra Sharma wrote:
On Sun, Jun 18, 2023 at 11:11:08AM -0700, Ira Weiny wrote:
Sumitra Sharma wrote:
kmap() has been deprecated in favor of the kmap_local_page()
due to high cost, restricted
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> Because getting IRQ from a device is platform-dependent, PCI devices have
> different methods for getting an IRQ. This patch is a preparation to extend
> this driver for supporting the PCI devices.
>
> Cc:
Hi,
On 2023/6/20 18:33, Thomas Zimmermann wrote:
Dereference struct drm_device.dev_private in the helper function
do_virtio_gpu_device().
Is the word "Dereference" accurate enough ?
I know what you means, I heard of de-reference a pointer frequently,
It stand for fetch the value of a pointe
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> Also rename the virtual master platform device as etnaviv_platform_device,
> for better reflection that it is a platform device, not a DRM device.
>
> Another benefit is that we no longer need to call of_no
Hi,
On 2023/6/21 17:07, Lucas Stach wrote:
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
From: Sui Jingfeng
Because getting IRQ from a device is platform-dependent, PCI devices have
different methods for getting an IRQ. This patch is a preparation to extend
this driver for
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> There are numerous members in the struct etnaviv_drm_private, which are
> shared by all GPU core. This patch introduces two dedicated functions for
> the construction and destruction of the instances of this
| 8
.../devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml | 8
3 files changed, 22 insertions(+)
---
base-commit: 15e71592dbae49a674429c618a10401d7f992ac3
change-id: 20230621-topic-sm8x50-upstream-mdss-bindings-dp-subnode-4fe367bf5cbe
Best regards,
--
Neil Armstrong
Document the optional document displayport controller subnode
of the SM8450 MDSS.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml | 8
1 file changed, 8 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm
Document the optional document displayport controller subnode
of the SM8550 MDSS.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml | 8
1 file changed, 8 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm
Document the optional document displayport controller subnode
of the SM8350 MDSS.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> Originally, component frameworks were used to bind multiple GPU cores to a
> virtual master. But there are chips that have only one GPU core integrated.
> The component framework can be avoided under some ci
On 08/06/2023 12:12, AngeloGioacchino Del Regno wrote:
Convert all instances of dev_err() -> return to dev_err_probe() and
where it makes sense to, change instances of `return ret` at the end
of probe functions to `return 0`, as errors are returned earlier.
Reviewed-by: Alexandre Mergnat
--
R
Hi,
On 2023/6/21 17:07, Lucas Stach wrote:
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
From: Sui Jingfeng
Because getting IRQ from a device is platform-dependent, PCI devices have
different methods for getting an IRQ. This patch is a preparation to extend
this driver for
On 08/06/2023 12:12, AngeloGioacchino Del Regno wrote:
Simplify the error path of return functions and drop the call to
pm_runtime_disable() in remove functions by switching to
devm_pm_runtime_enable() where possible.
Reviewed-by: Alexandre Mergnat
--
Regards,
Alexandre
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> This patch adds PCI driver support on top of what we already have, take
> the GC1000 in LS7A1000/LS2K1000 as the first instance which enjoy the PCI
> device driver. There is only one GPU core for the GC1000
From: Tvrtko Ursulin
With the typical model where the display server opens the file descriptor
and then hands it over to the client(*), we were showing stale data in
debugfs.
Fix it by updating the drm_file->pid on ioctl access from a different
process.
The field is also made RCU protected to a
Hi
On 2023/6/21 17:15, Lucas Stach wrote:
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
From: Sui Jingfeng
Also rename the virtual master platform device as etnaviv_platform_device,
for better reflection that it is a platform device, not a DRM device.
Another benefit is th
Hi Dave, Daniel,
A weekly collection of fixes for the drm-next/6.5 merge window:
One fix for incorrect error handling in the frame buffer mmap callback,
HuC init error handling fix, missing wakeref during GSC init and a build
fix when !CONFIG_PROC_FS.
Regards,
Tvrtko
drm-intel-next-fixes-2023-
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> Loongson CPUs maintain cache coherency by hardware, which means that the
> data in the CPU cache is identical to the data in main system memory. As
> for the peripheral device, most of Loongson chips chose t
Add a motivation for and description of asynchronous VM_BIND operation
v2:
- Fix typos (Nirmoy Das)
- Improve the description of a memory fence (Oak Zeng)
- Add a reference to the document in the Xe RFC.
- Add pointers to sample uAPI suggestions
Signed-off-by: Thomas Hellström
Acked-by: Nirmoy D
Am Mittwoch, dem 21.06.2023 um 17:20 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/21 17:07, Lucas Stach wrote:
> > Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> > > From: Sui Jingfeng
> > >
> > > Because getting IRQ from a device is platform-dependent, PCI devices have
>
1. Add casting before assign to avoid the unintentional integer
overflow or unintended sign extension.
2. Add a int varriable for multiplier calculation instead of calculating
different types multiplier with dma_addr_t varriable directly.
Fixes: 1a64a7aff8da ("drm/mediatek: Fix cursor plane
CERT-C Characters and Strings (CERT STR31-C)
all_drm_priv[cnt] evaluates to an address that could be at negative
offset of an array.
In mtk_drm_get_all_drm_priv():
Guarantee that storage for strings has sufficient space for character
data and the null terminator.
So change cnt to unsigned int and
Add this patch series to fix some mediatek-drm coverity issues.
Change in v3:
1. swap Fixes and Signed tag.
2. change cast (__u64) to '=' then ' *='.
Change in v2:
1. remove kfree(pkt) in mtk_drm_crtc_create_pkt().
2. change the statement of cnt reach to MAX_CRTC.
3. drop the mtk_gem_obj initiali
Fixing the coverity issue of:
mtk_drm_cmdq_pkt_destroy frees address of mtk_crtc->cmdq_handle
So remove the free function.
Fixes: 7627122fd1c0 ("drm/mediatek: Add cmdq_handle in mtk_crtc")
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_drm
Null-checking state suggests that it may be null, but it has already
been dereferenced on drm_atomic_get_new_plane_state(state, plane).
The parameter state will never be NULL currently, so just remove the
state is NULL flow in this function.
Fixes: 5ddb0bd4ddc3 ("drm/atomic: Pass the full state t
On Wed, 2023-06-21 at 13:45 +0800, Evan Quan wrote:
> To support AMD's WBRF interference mitigation mechanism, Wifi adapters
> utilized in the system must register the frequencies in use(or unregister
> those frequencies no longer used) via the dedicated APCI calls. So that,
> other drivers respond
Am Mittwoch, dem 21.06.2023 um 17:49 +0800 schrieb Sui Jingfeng:
> Hi
>
> On 2023/6/21 17:15, Lucas Stach wrote:
> > Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> > > From: Sui Jingfeng
> > >
> > > Also rename the virtual master platform device as etnaviv_platform_device,
>
On Wed, 21 Jun 2023 10:10:22 +0200
Jacopo Mondi wrote:
> Hello, this series is based on the RFC sent by Melssa Wen:
> "[RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface"
> https://lore.kernel.org/dri-devel/20230109143846.1966301-1-m...@igalia.com/
> that introduces CRTC properties to control 3D
Am 21.06.23 um 11:12 schrieb Sui Jingfeng:
Hi,
On 2023/6/20 18:33, Thomas Zimmermann wrote:
Dereference struct drm_device.dev_private in the helper function
do_virtio_gpu_device().
Is the word "Dereference" accurate enough ?
It's not really the correct word, you're right. 'Access' or 'rea
Hi
Am 19.06.23 um 16:22 schrieb Thomas Zimmermann:
Hi
Am 02.06.23 um 09:40 schrieb Keith Zhao:
This patch implements gem related APIs for JH7100 SoC.
please also see my other reply to this patch. My mail client had a bug
before I could finish it. Below are some more comments.
Signed-off
On Wed, Jun 21, 2023 at 09:32:04AM +0200, Christian König wrote:
> Some Android CTS is testing for that.
>
> Signed-off-by: Christian König
> CC: sta...@vger.kernel.org
> ---
> drivers/dma-buf/dma-fence-unwrap.c | 11 +--
> drivers/dma-buf/dma-fence.c| 5 +++--
> drivers/gpu/drm
On Wed, Jun 21, 2023 at 09:32:04AM +0200, Christian König wrote:
> Some Android CTS is testing for that.
>
> Signed-off-by: Christian König
> CC: sta...@vger.kernel.org
What commit id does this fix?
thanks,
greg k-h
Hi Keith
Am 02.06.23 um 09:40 schrieb Keith Zhao:
Add mode setting functions for JH7110 SoC.
Signed-off-by: Keith Zhao
---
drivers/gpu/drm/verisilicon/Makefile | 1 +
drivers/gpu/drm/verisilicon/vs_drv.c | 3 +
drivers/gpu/drm/verisilicon/vs_fb.c | 181 +++
On 15-06-23, 09:38, Sandor Yu wrote:
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of parameters
> should cover the potential
On 15-06-23, 09:38, Sandor Yu wrote:
> Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort PHY mode is configurated in the driver.
>
> Signed-off-by: Sandor Yu
> ---
> drivers/
Am 19.06.23 um 10:22 schrieb Thomas Zimmermann:
Am 19.06.23 um 03:57 schrieb Sui Jingfeng:
Hi,
Tested with ast2400
On 2023/6/16 21:52, Thomas Zimmermann wrote:
Ast sets up a managed release of the MMIO access flags. Move this
code next to the MMIO access code, so that it runs if other e
Hi,
On 2023/6/21 19:48, Thomas Zimmermann wrote:
Am 19.06.23 um 10:22 schrieb Thomas Zimmermann:
Am 19.06.23 um 03:57 schrieb Sui Jingfeng:
Hi,
Tested with ast2400
On 2023/6/16 21:52, Thomas Zimmermann wrote:
Ast sets up a managed release of the MMIO access flags. Move this
code next
On 15-06-23, 09:38, Sandor Yu wrote:
> Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> HDMI PHY mode is configurated in the driver.
>
> Signed-off-by: Sandor Yu
> ---
> drivers/phy/freescale
Hi,
On 2023/6/21 18:36, Thomas Zimmermann wrote:
Am 21.06.23 um 11:12 schrieb Sui Jingfeng:
Hi,
On 2023/6/20 18:33, Thomas Zimmermann wrote:
Dereference struct drm_device.dev_private in the helper function
do_virtio_gpu_device().
Is the word "Dereference" accurate enough ?
It's not real
Hi,
On 2023/6/21 17:39, Lucas Stach wrote:
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
From: Sui Jingfeng
This patch adds PCI driver support on top of what we already have, take
the GC1000 in LS7A1000/LS2K1000 as the first instance which enjoy the PCI
device driver. There
Am 21.06.23 um 13:02 schrieb Greg KH:
On Wed, Jun 21, 2023 at 09:32:04AM +0200, Christian König wrote:
Some Android CTS is testing for that.
Signed-off-by: Christian König
CC: sta...@vger.kernel.org
What commit id does this fix?
Sorry Greg, totally unintentionally send this CC to the stable
On 21/06/2023 12:22, Jason-JH.Lin wrote:
Fixing the coverity issue of:
mtk_drm_cmdq_pkt_destroy frees address of mtk_crtc->cmdq_handle
So remove the free function.
Reviewed-by: Alexandre Mergnat
--
Regards,
Alexandre
On 21/06/2023 12:22, Jason-JH.Lin wrote:
CERT-C Characters and Strings (CERT STR31-C)
all_drm_priv[cnt] evaluates to an address that could be at negative
offset of an array.
In mtk_drm_get_all_drm_priv():
Guarantee that storage for strings has sufficient space for character
data and the null ter
On 21/06/2023 12:02, Dongjin Kim wrote:
> Elida hj080be31ia1 is a 8" MIPI display panel. It utilizes an ILI9881C
> controller chip, so its compatible string should be added to
> ilitek,ili9881c file.
>
> Add the compatible string for it.
>
> Signed-off-by: Dongjin Kim
Acked-by: Krzysztof Kozlo
On Wed, Jun 21, 2023 at 12:04:35PM +0200, Thomas Hellström wrote:
> Add a motivation for and description of asynchronous VM_BIND operation
>
> v2:
> - Fix typos (Nirmoy Das)
> - Improve the description of a memory fence (Oak Zeng)
> - Add a reference to the document in the Xe RFC.
> - Add pointers
Hi,
On 2023/6/21 17:22, Lucas Stach wrote:
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
From: Sui Jingfeng
There are numerous members in the struct etnaviv_drm_private, which are
shared by all GPU core. This patch introduces two dedicated functions for
the construction and
On 21/06/2023 12:22, Jason-JH.Lin wrote:
1. Add casting before assign to avoid the unintentional integer
overflow or unintended sign extension.
2. Add a int varriable for multiplier calculation instead of calculating
different types multiplier with dma_addr_t varriable directly.
Fixes
On Wed, Jun 21, 2023 at 02:05:07PM +0200, Christian König wrote:
> Am 21.06.23 um 13:02 schrieb Greg KH:
> > On Wed, Jun 21, 2023 at 09:32:04AM +0200, Christian König wrote:
> > > Some Android CTS is testing for that.
> > >
> > > Signed-off-by: Christian König
> > > CC: sta...@vger.kernel.org
> >
On 21/06/2023 12:22, Jason-JH.Lin wrote:
Null-checking state suggests that it may be null, but it has already
been dereferenced on drm_atomic_get_new_plane_state(state, plane).
The parameter state will never be NULL currently, so just remove the
state is NULL flow in this function.
Reviewed
From: Robert Foss
On Tue, 20 Jun 2023 08:12:54 +0200, Juerg Haefliger wrote:
> The module loads firmware so add a MODULE_FIRMWARE macro to provide that
> information via modinfo.
>
>
Applied, thanks!
[1/1] drm/bridge: lt9611uxc: Add MODULE_FIRMWARE macro
https://cgit.freedesktop.org/drm
Fix the test for the AST2200 in the DRAM initialization. The value
in ast->chip has to be compared against an enum constant instead of
a numerical value.
This bug got introduced when the driver was first imported into the
kernel.
Signed-off-by: Thomas Zimmermann
Fixes: 312fec1405dd ("drm: Initia
Ast's code for detecting the device type and features is convoluted.
It mixes up several state fields, chip types and sub-models. Rework
the driver into something more understandable.
Patches 1 fixes a long-standing bug. The affected code has never
worked correctly.
Patches 2 to 8 make various ch
According to the chip detection in ast_detect_chip(), AST2300 and
later always have a PCI revision of 0x20 or higher. Therefore the
code in ast_set_def_ext_reg() can not use the else branch when
selecing the EXT register values. Remove the dead branch and the
related values.
Signed-off-by: Thomas
Remove the unused field vga2_clone from struct ast_device. No
functional changes.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sui Jingfeng
Reviewed-by: Jocelyn Falempe
Tested-by: Jocelyn Falempe # AST2600
---
drivers/gpu/drm/ast/ast_drv.h | 1 -
drivers/gpu/drm/ast/ast_main.c | 1 -
2 file
There's way too much going on in ast_detect_chip(). Move the POST
and config code from the top of the function into the caller. No
functional changes.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jocelyn Falempe
Tested-by: Jocelyn Falempe # AST2600
---
drivers/gpu/drm/ast/ast_main.c | 52
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