It is likely that there is a typo in the sanity check for 'v_total'.
If it is 0, then 'pixels_per_frame' will also be 0, and in this case,
we also return 'single_frame_time_multiplier * min_single_frame_time_us'.
So test for !v_total which looks much more logical.
Fixes: 4562236b3bc0 ("drm/amd/d
Thanks to the sanity check a few lines above:
if (!h_total || !v_total || !pix_clk_khz)
and the computation done afterwards on these non 0 values, we know that
'pixels_per_second', 'pixels_per_frame' and 'refresh_rate' are not 0
The code can be simplified accordingly.
Signed-off-by: Christop
Use USEC_PER_SEC instead of defining an equivalent local 'us_in_sec'.
Signed-off-by: Christophe JAILLET
---
NOT compile tested. Because of some BROKEN in KConfig files.
Some header may be missing for USEC_PER_SEC!
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 4 +---
1 file changed, 1
On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
>>
>>
>> On 23.05.2023 03:15, Bjorn Andersson wrote:
>>> From: Bjorn Andersson
>>>
>>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>>> SC8280XP.
>>>
>>> Signed
On 29.05.2023 04:42, Dmitry Baryshkov wrote:
> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote:
>>
>> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
>> another path that needs to be handled to ensure MDSS functions properly,
>> namely the "reg bus", a.k.a the CPU-MDSS int
'rbiter' -> 'arbite'
Signed-off-by: Sui Jingfeng
---
include/drm/i915_drm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7adce327c1c2..3dcb1db519ae 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -4
Il 26/05/23 16:24, Doug Anderson ha scritto:
Hi,
On Fri, May 26, 2023 at 3:09 AM Icenowy Zheng wrote:
Currently a specific panel number is used in the Elm DTSI, which is
corresponded to a 12" panel. However, according to the official Chrome
OS devices document, Elm refers to Acer Chromebook R
Hi Biju,
Thank you for the patch.
On Mon, May 22, 2023 at 11:18:39AM +0100, Biju Das wrote:
> Renesas PMIC RAA215300 exposes two separate i2c devices, one for the main
> device and another for rtc device.
>
> Enhance i2c_new_ancillary_device() to instantiate a real device.
Doesn't it already in
On Mon, 29 May 2023, Sui Jingfeng wrote:
> 'rbiter' -> 'arbite'
Should be arbiter.
>
> Signed-off-by: Sui Jingfeng
> ---
> include/drm/i915_drm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 7adce327c1c2..3dcb
On 5/26/23 18:55, Marek Vasut wrote:
> On 5/25/23 10:14, Raphael Gallais-Pou wrote:
>
> Hi,
Hi Marek,
>
>>> I think if you retain the stm32mp151.dtsi >> <1>;
>>> #size-cells = <0>; }; }; part, then you wouldn't be getting any warnings
>>> regarding LTDC , and you w
Il 28/05/23 16:00, Adrián Larumbe ha scritto:
I agree that the title almost says it all, but please add a commit description.
Regards,
Angelo
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 22 --
1 file changed, 4 insertions(+), 18 deletio
在 2023-05-29星期一的 10:02 +0200，AngeloGioacchino Del Regno写道：
> Il 26/05/23 16:24, Doug Anderson ha scritto:
> > Hi,
> >
> > On Fri, May 26, 2023 at 3:09 AM Icenowy Zheng
> > wrote:
> > >
> > > Currently a specific panel number is used in the Elm DTSI, which
> > > is
> > > corresponded to a 12" pan
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson
> >>>
> >>> Add Adreno
On 29/05/2023 10:42, Konrad Dybcio wrote:
On 29.05.2023 04:42, Dmitry Baryshkov wrote:
On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote:
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "
Hi,
On 2023/5/29 16:06, Jani Nikula wrote:
On Mon, 29 May 2023, Sui Jingfeng wrote:
'rbiter' -> 'arbite'
Should be arbiter.
Yeah, should be arbiter.
arbiter is a noun. Here, this arbiter may referrer to the
drivers/pci/vgaarb.c.
Can you help correct then apply it ? thanks.
Signed
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Mon, May 22, 2023 at 11:18:39AM +0100, Biju Das wrote:
> > Renesas PMIC RAA215300 exposes two separate i2c devices, one for the
> > ma
On 29.05.2023 10:47, Dmitry Baryshkov wrote:
> On 29/05/2023 10:42, Konrad Dybcio wrote:
>>
>>
>> On 29.05.2023 04:42, Dmitry Baryshkov wrote:
>>> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio
>>> wrote:
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another p
This serie aims to reduce the number of device-tree warnings of
following boards :
- STM32F469-DISCO
- STM32MP15*
Those warnings were appearing either during build or when checking
dt-bindings and concern mostly LTDC and DSI IPs. They were due to the
following cases:
- 'panel-dsi@0' instea
"#address-cells" and "#size-cells" are two properties that are not
mandatory. For instance, the DSI could refer to a bridge outside the scope
of the node rather than include a 'panel@0' subnode. By doing so, address
and size fields become then unnecessary, creating a warning at build time.
Signed-
Several warnings appear when building and checking stm32f429 device-tree:
arch/arm/boot/dts/stm32f469-disco.dts:182.28-184.5: Warning
(unit_address_vs_reg): /soc/display-controller@40016800/port/endpoint@0: node
has a unit name, but no reg or ranges property
.../arch/arm/boot/dts/stm32f469-disc
Those concern:
* "#size-cells" and "#address-cells" wrongly used
* residual "reg" property appearing on endpoints where it could be
avoided
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/stm32mp151.dtsi | 5 -
.../boot/dts/stm32mp157a-icore-stm32mp
Fixes DSI related warnings:
* "#size-cells" and "#address-cells" wrongly used
* Changed 'panel-dsi@0' to 'panel@0' according to dsi-controller.yaml
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/stm32mp157.dtsi | 7 ---
.../boot/dts/stm32mp157a-icore-stm
Remove redundant assignment code for ttm->caching
Signed-off-by: Ma Jun
---
drivers/gpu/drm/ttm/ttm_tt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 02b812dacc5d..45a44544b656 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b
Add the compatible for the MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
b/Documentation/devicetree/bindings/displ
Add the required config for the v1.1 MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_
MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
Worth noting that the msm-3.10 downstream kernel also will try other
sequences in case this one doesn't work, but during testing it has shown
that the _m seque
Add the nodes that describe the mdss so that display can work on
MSM8226.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 118
1 file changed, 118 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi
b/arch/arm/boot/dts/qcom-ms
This series adds the required configs for MDP5 and DSI blocks that are
needed for MDSS on MSM8226. Finally we can add the new nodes into the
dts.
Tested on apq8026-lg-lenok and msm8926-htc-memul.
Signed-off-by: Luca Weiss
---
Luca Weiss (7):
dt-bindings: msm: dsi-phy-28nm: Document msm8226
Add the compatible for the DSI found on MSM8226.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Documentation/dev
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
existing bits from other revisions that are identical for v1.0.2.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drive
The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 +
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 +
2 files changed, 2 insertions(+)
diff
On 5/29/23 11:13, Raphael Gallais-Pou wrote:
Fixes DSI related warnings:
* "#size-cells" and "#address-cells" wrongly used
* Changed 'panel-dsi@0' to 'panel@0' according to dsi-controller.yaml
Signed-off-by: Raphael Gallais-Pou
Reviewed-by: Marek Vasut
On 5/29/23 10:07, Raphael Gallais-Pou wrote:
Hi,
I think if you retain the stm32mp151.dtsi ;
#size-cells = <0>; }; }; part, then you wouldn't be getting any warnings
regarding LTDC , and you wouldn't have to remove the unit-address from
endpoint@0 .
btw. I do u
On 5/29/23 11:13, Raphael Gallais-Pou wrote:
Those concern:
* "#size-cells" and "#address-cells" wrongly used
* residual "reg" property appearing on endpoints where it could be
avoided
Signed-off-by: Raphael Gallais-Pou
Reviewed-by: Marek Vasut
On 29/05/2023 12:08, Konrad Dybcio wrote:
On 29.05.2023 10:47, Dmitry Baryshkov wrote:
On 29/05/2023 10:42, Konrad Dybcio wrote:
On 29.05.2023 04:42, Dmitry Baryshkov wrote:
On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote:
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), th
On Mon, 29 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
> Hi,
>
>
> On 2023/5/29 16:06, Jani Nikula wrote:
>> On Mon, 29 May 2023, Sui Jingfeng wrote:
>>> 'rbiter' -> 'arbite'
>> Should be arbiter.
>
> Yeah, should be arbiter.
>
> arbiter is a noun. Here, this arbiter may referrer to the
On 29.05.2023 11:44, Luca Weiss wrote:
> MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
> based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
>
> Worth noting that the msm-3.10 downstream kernel also will try other
> sequences in case this one doesn't wor
On 29/05/2023 08:37, Aradhya Bhatia wrote:
Btw, we seem to be missing get-output-fmt from the mdhp driver.
Yes, we are.
With the drm_bridge_attach call added, the display-connector bridge will
assign MEDIA_BUS_FMT_FIXED as the default output format. And most
bridges support only their primary o
Hi,
I'm just hesitating to so, thank you.
On 2023/5/29 18:06, Jani Nikula wrote:
On Mon, 29 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
Hi,
On 2023/5/29 16:06, Jani Nikula wrote:
On Mon, 29 May 2023, Sui Jingfeng wrote:
'rbiter' -> 'arbite'
Should be arbiter.
Yeah, should be
'rbiter' -> 'arbiter'
Signed-off-by: Sui Jingfeng
---
include/drm/i915_drm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7adce327c1c2..adff68538484 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the required config for the v1.1 MDP5 found on MSM8226.
>
> Signed-off-by: Luca Weiss
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
>
> 1 file changed, 82 insertions(+)
>
> diff --git a/drivers/gpu/drm/ms
On 2023-05-26 09:42:33, Neil Armstrong wrote:
> On 22/05/2023 16:51, Marijn Suijten wrote:
> > On 2023-05-22 11:05:38, Neil Armstrong wrote:
> >> On 21/05/2023 12:30, Marijn Suijten wrote:
> >>> On 2023-05-16 13:20:30, Jessica Zhang wrote:
> Document the 1080x2340 Visionox R66451 AMOLED DSI pa
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
> existing bits from other revisions that are identical for v1.0.2.
>
> Signed-off-by: Luca Weiss
> ---
Reviewed-by: Konrad Dybcio
Konrad
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
> d
On 2023-05-26 09:32:45, Neil Armstrong wrote:
> > +static int visionox_r66451_bl_update_status(struct backlight_device
> > *bl)
> > +{
> > + struct mipi_dsi_device *dsi = bl_get_data(bl);
> > + u16 brightness = backlight_get_brightness(bl);
> > +
> > + return
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the nodes that describe the mdss so that display can work on
> MSM8226.
>
> Signed-off-by: Luca Weiss
> ---
> arch/arm/boot/dts/qcom-msm8226.dtsi | 118
>
> 1 file changed, 118 insertions(+)
>
> diff --git a/a
On 29/05/2023 12:44, Luca Weiss wrote:
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
existing bits from other revisions that are identical for v1.0.2.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files
On 29/05/2023 15:10, Konrad Dybcio wrote:
On 29.05.2023 11:44, Luca Weiss wrote:
Add the nodes that describe the mdss so that display can work on
MSM8226.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 118
1 file changed, 118 inse
On 29.05.2023 14:19, Dmitry Baryshkov wrote:
> On 29/05/2023 15:10, Konrad Dybcio wrote:
>>
>>
>> On 29.05.2023 11:44, Luca Weiss wrote:
>>> Add the nodes that describe the mdss so that display can work on
>>> MSM8226.
>>>
>>> Signed-off-by: Luca Weiss
>>> ---
>>> arch/arm/boot/dts/qcom-msm82
On 29/05/2023 12:44, Luca Weiss wrote:
Add the required config for the v1.1 MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wis
Use struct_size() instead of hand-writing it. It is less verbose, more
robust and more informative.
Signed-off-by: Christophe JAILLET
---
drivers/accel/ivpu/ivpu_job.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/accel/ivpu/ivpu_job.c b/drivers/accel/ivpu/ivpu_j
On 29/05/2023 14:59, Konrad Dybcio wrote:
On 29.05.2023 11:44, Luca Weiss wrote:
Add the required config for the v1.1 MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
diff
Hi Biju,
Thank you for the patch.
On Tue, May 02, 2023 at 11:09:09AM +0100, Biju Das wrote:
> The RZ/G2L LCD controller is composed of Frame Compression Processor
> (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
>
> The DU module supports the following hardware features
> − Displ
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add a compatible string for MediaTek Helio X10 MT6795's display PWM
block: this is the same as MT8173.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks!
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 4
v7 -> v8:
- Fix up resume/suspend (icc now correctly parks to 0, don't abuse
OPP & genpd throughout system-wide suspend)
- Don't handle ebi1_clk separately, the bulk ops handle it just fine
- Rebase on next-20230525 (no meaningful changes)
v7:
https://lore.kernel.org/linux-arm-msm/20230223-topi
As pointed out by Akhil during the review process of GMU wrapper
introduction [1], it makes sense to move this write into the function
that's responsible for forcibly shutting the GMU off.
It is also very convenient to move this to GMU-specific code, so that
it does not have to be guarded by an if
These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 4 ins
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat thes
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat thes
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno
This function is responsible for telling the GPU to halt transactions
on all of its relevant buses, drain them and leave them in a predictable
state, so that the GPU can be e.g. reset cleanly.
Move the function to a6xx_gpu.c, remove the static keyword and add a
prototype in a6xx_gpu.h to accomodat
Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
GPUs and reuse it in a6xx_gmu_force_off().
This helper, contrary to the original usage in GMU code paths, adds
a write memory barrier which together with the necessary delay should
ensure that the reset is never deasserted too qui
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0.
This is typically done automatically on successful GX collapse, but in
case that fails, we should take care of it.
Also, add a memory barrier to ensure it's gone through before jumping
to
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
Reviewed-b
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs
Unify the indentation and explain the cryptic 0xF value.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 6bb4da
A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
a
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset lin
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add the MultiMedia System node, providing clocks for the multimedia
hardware blocks and their IOMMU/SMIs.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 13 +
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add nodes for the multimedia IOMMU and its LARBs: this includes all but
the MJC LARB, which cannot currently be used and will be added later.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediat
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add the pwrap node: this is used to communicate with the PMIC(s).
Signed-off-by: AngeloGioacchino Del Regno
Applied thanks!
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --g
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
MT6331 is the primary PMIC for the MediaTek Helio X10 MT6795 smartphone
platforms: add a devicetree describing its regulators, Real Time Clock
and PMIC-keys.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm6
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
This smartphone uses the Helio X10 standard MT6331+MT6332 combo PMICs:
include the mt6331 devicetree and add the required interrupt.
Note that despite there being two interrupts, one for MT6331 and one
for MT6332, in configurations using
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Configure and enable the MMC0/1/2 controllers, used for the eMMC chip,
MicroSD card slot and SDIO (WiFi) respectively.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
.../dts/mediatek/mt6795-sony-xperia-m5.dts| 9
Hi Laurent,
> Subject: Re: [PATCH v9 RESEND 2/5] dt-bindings: display: Document
> Renesas RZ/G2L DU bindings
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Tue, May 02, 2023 at 11:09:09AM +0100, Biju Das wrote:
> > The RZ/G2L LCD controller is composed of Frame Compression Processor
> > (FCPV
On 14/04/2023 10:22, Krzysztof Kozlowski wrote:
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add a compatible string for MediaTek Helio X10 MT6795: this SoC uses
the same DSI PHY as MT8173.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/phy/medi
Hi Chun-Kuang Hu,
Can you help to merge the missing DT-binding patches in this series?
Thanks a lot,
Matthias
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add a compatible string for the MediaTek Helio X10 MT6795 SoC, using
the same parameters as MT8183.
Signed-off-by: AngeloGioacch
Hi!
I think we have a serious kernel bug that is related to or inside in
drivers/gpu/drm/ttm/ttm_bo.c
The reason for my assumptions lies in one of my recent system freezes
with kernel 6.3.4 that go along with massive kernel error logs in
journalctl. An extract from the logs:
...
May 28 14:
On Fri, May 26, 2023 at 3:04 PM Philippe CORNU
wrote:
>
>
> On 5/19/23 22:05, Alexandru Ardelean wrote:
> > From: Yannick Fertre
> >
> > Add new property to set a brightness by default at probe.
> >
> > Reviewed-by: Philippe CORNU
>
> Hi Alexandru,
>
> Many thanks for your patch.
>
> You have se
On Fri, May 26, 2023 at 1:20 PM Daniel Thompson
wrote:
>
> On Fri, May 19, 2023 at 11:05:20PM +0300, Alexandru Ardelean wrote:
> > From: Yannick Fertre
> >
> > Add documentation for new default-brightness-level property.
> >
> > Reviewed-by: Philippe CORNU
> > Signed-off-by: Yannick Fertre
> >
On Fri, May 26, 2023 at 3:05 PM Philippe CORNU
wrote:
>
>
>
> On 5/19/23 22:05, Alexandru Ardelean wrote:
> > From: Yannick Fertre
> >
> > Add documentation for new default-brightness-level property.
> >
> > Reviewed-by: Philippe CORNU
>
> Hi Alexandru,
> same comments as for the 1/2 patch.
Ack
Hi Biju,
On Thu, May 25, 2023 at 02:30:10PM +, Biju Das wrote:
> Hi DRM maintainers,
>
> Gentle ping.
Sorry, I was on holidays the last two weeks.
> Are we happy with moving all Renesas drm drivers to Renesas specific
> directory or preference is for separate one??
This works for me.
> If
HI Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH v9 RESEND 0/5] Add RZ/{G2L,G2LC} and RZ/V2L Display
> Unit support
>
> Hi Biju,
>
> On Thu, May 25, 2023 at 02:30:10PM +, Biju Das wrote:
> > Hi DRM maintainers,
> >
> > Gentle ping.
>
> Sorry, I was on holidays the last two weeks.
Add support for HDMI Tx on MT8195.
This includes a split of the current "legacy" hdmi driver into a common
library of functions and two dedicated compilation units with specific
code for mt8167 and another for the "v2" mt8195 SoC.
Support for the new mt8195 dpi/drm_drv adjustments to support hdmi
Make cec device optional in order to support newer versions of the
hdmi IP which doesn't require it
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_hdmi.c| 8 +++--
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 52 +++---
2 files changed, 39 inse
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, use a regmap.
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 173 ++--
1 file changed, 65 insertions(+), 108 deletions(-)
diff --git
Add mt8195 SoC bindings for hdmi and hdmi-ddc
On mt8195 the ddc i2c controller is part of the hdmi IP block and thus has no
specific register range, power domain or interrupt, making it simpler
than the legacy "mediatek,hdmi-ddc" binding.
Signed-off-by: Guillaume Ranquet
---
.../bindings/displa
Adds hdmi and hdmi-ddc support for v2 IP.
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/Kconfig|2 +
drivers/gpu/drm/mediatek/Makefile |2 +
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 13 +
drivers/gpu/drm/mediatek/mtk_hdmi_common.h |1 +
d
Add HDMI audio support for v2
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 +
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 198 +
drivers/gpu/drm/mediatek/mtk_hdmi_v2.h | 4 +-
3 files changed, 202 insertions(+), 1 deleti
Add dt-binding documentation of dpi for MediaTek MT8195 SoC.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Guillaume Ranquet
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/med
Create a common "framework" that can be used to add support for
different hdmi IPs within the mediatek range of products.
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_hdmi.c| 596 ++---
driv
Add the DPI1 hdmi path support in mtk dpi driver
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 121 ++--
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 5 ++
2 files changed, 119 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
Hi Biju,
Thank you for the patch.
This is a partial review, because the driver is big, and because some
changes in v10 will (hopefully) simplify the code and make review
easier.
On Tue, May 02, 2023 at 11:09:11AM +0100, Biju Das wrote:
> The LCD controller is composed of Frame Compression Proces
On Mon, May 29, 2023 at 02:22:06PM +, Biju Das wrote:
> HI Laurent,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v9 RESEND 0/5] Add RZ/{G2L,G2LC} and RZ/V2L Display
> > Unit support
> >
> > Hi Biju,
> >
> > On Thu, May 25, 2023 at 02:30:10PM +, Biju Das wrote:
> > > Hi DRM mai
The vga_is_firmware_default() function will work on non-x86 architectures
as long as the arch has UEFI GOP support, which passes the firmware
framebuffer base address and size.
This patch makes the vga_is_firmware_default() function arch-independent.
This could help the VGAARB subsystem make the r
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