Hi Thomas,
Thanks for your review.
On 2023/5/24 下午 06:41, Thomas Zimmermann wrote:
Hi,
sorry that this took so long.
Am 24.05.23 um 04:34 schrieb Jammy Huang:
Hi Thomas,
Could you help review this patch?
This is an issue leading to kernel panic found by Intel. Wendy has
confirmed issue re
On 5/18/2023 3:22 PM, Dmitry Baryshkov wrote:
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Jeykumar Sankaran
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6
On 24.05.2023 10:13, Arseniy Krasnov wrote:
>
>
> On 24.05.2023 09:33, liao jaime wrote:
>> Hi Miquel
>>
>>>
>>> Hi Arseniy,
>>>
>>> avkras...@sberdevices.ru wrote on Mon, 15 May 2023 12:49:50 +0300:
>>>
Hello @Miquel!
Sorry, but who could review this patch? :) IIUC this logic i
On Wed, 24 May 2023, Hamza Mahfooz wrote:
> + Kees
>
> On 5/24/23 15:50, Alex Deucher wrote:
>> On Wed, May 24, 2023 at 3:46 PM Felix Kuehling
>> wrote:
>>>
>>> Sure, I think we tried enabling warnings as errors before and had to
>>> revert it because of weird compiler quirks or the variety of c
Hi,
On 25/05/2023 04:49, Cong Yang wrote:
Compare V2: order of the tables match the order they're
referenced.
Cong Yang (4):
dt-bindings: display: panel: Add compatible for Starry himax83102-j02
drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel
dt-bindings: display: pane
On 24/05/2023 22:46, Dixit, Ashutosh wrote:
On Wed, 24 May 2023 02:12:31 -0700, Andrzej Hajda wrote:
Hi Andrzej,
On 23.05.2023 17:19, Ashutosh Dixit wrote:
pmu_needs_timer() keeps the timer running even when GT is parked,
ostensibly to sample requested/actual frequencies. However
frequen
There are two bugs here.
1) Drop the lock if copy_from_user() fails.
2) If the copy fails then the correct error code is -EFAULT instead of
-EINVAL.
I also broke up the long line and changed "sizeof rd->id" to
"sizeof(rd->id)".
Fixes: 164fb2940933 ("drm/amd/amdgpu: Update debugfs for XCC suppo
On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> ICL doesn't support FEC with a x1 DP link. Make sure
> we don't try to enable FEC in such cases.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 23 ---
> 1
From: Tvrtko Ursulin
Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
thresholds are invariant so lets move their setting to init time.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_rp
From: Tvrtko Ursulin
>From patch 4:
User feedback indicates significant performance gains are possible in
specific games with non default RPS up/down thresholds.
Expose these tunables via sysfs which will allow users to achieve best
performance when running games and best power
From: Tvrtko Ursulin
In preparation for exposing via sysfs add helpers for managing rps
thresholds.
v2:
* Force sw and hw re-programming on threshold change.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_
From: Tvrtko Ursulin
Record the default values as preparation for exposing the sysfs controls.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 2
From: Tvrtko Ursulin
Now that we allow them to be modified, lets include them in the error
state so it is visible when they have been modified in GPU hang triage.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Cc: Andi Shyti
---
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +
drivers/gpu/dr
From: Tvrtko Ursulin
User feedback indicates significant performance gains are possible in
specific games with non default RPS up/down thresholds.
Expose these tunables via sysfs which will allow users to achieve best
performance when running games and best power efficiency elsewhere.
Note this
On 5/18/23 01:33, Marek Vasut wrote:
> On 5/17/23 19:04, Raphael Gallais-Pou wrote:
>> Hi Marek
>
> Hi,
>
>> On 5/17/23 17:41, Marek Vasut wrote:
>>> On 5/17/23 16:35, Raphael Gallais-Pou wrote:
>>>
>>> Hi,
>>>
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
b/arch/arm/boot/dts/stm3
Hi Karolina,
Am 16.05.23 um 16:02 schrieb Karolina Stolarek:
Hi all,
I'm working on KUnit tests for TTM subsystem (nothing RFC-worthy yet),
with an aim to provide better test coverage for the code used by i915
and Xe. Before digging deeper, I wanted to check if the priorities
outlined here
On Tue, 2023-05-02 at 17:38 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On pre-TGL FEC is a port level feature, not a transcoder
> level features, and it's DDI A which doesn't have it, not
> trancodere A.
A couple of typos: "level feature" and "transcoder A".
> Check for the correct
On Tue, 2023-05-02 at 17:38 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The MST codepath is missing FEC readout. Add it.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i9
On 24/05/2023 21:02, fei.y...@intel.com wrote:
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("dr
On 24/05/2023 14:32, Geert Uytterhoeven wrote:
Add support for the Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/panel/panel-simple.c | 33
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/p
On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop dumping state while reading it out. We have a proper
> place for that stuff.
>
> Signed-off-by: Ville Syrjälä
> ---
> .../gpu/drm/i915/display/intel_crtc_state_dump.c| 2 ++
> drivers/gpu/drm/i915/displ
On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Split some overly long lines.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_fdi.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
It doesn't matter much, but it wou
On Wed, 24 May 2023, Simon Ser wrote:
> On Tuesday, May 16th, 2023 at 07:39, Alan Liu wrote:
>
>> To address this problem, since modern display control hardware is able to
>> calculate the CRC checksum of the display content, we are thinking of a
>> feature to let userspace specify a region of in
On Thu, 11 May 2023, Krzysztof Kozlowski wrote:
> Statically allocated array of pointers to hwmon_channel_info can be made
> const for safety.
Btw if you want to further make things const, the compound literals
defined by HWMON_CHANNEL_INFO() still end up mutable, even if they're
only referenced
Copare V3:Resend without Conor's acks on patches 2 and 4.
Cong Yang (4):
dt-bindings: display: panel: Add compatible for Starry himax83102-j02
drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel
dt-bindings: display: panel: Add compatible for Starry ili9882t
drm/panel: Support
The STARRY himax83102-j02 is a 10.51" WUXGA TFT LCD panel,
which fits in nicely with the existing panel-boe-tv101wum-nl6
driver. Hence, we add a new compatible with panel specific config.
Signed-off-by: Cong Yang
Reviewed-by: Douglas Anderson
Acked-by: Conor Dooley
---
.../devicetree/bindings/
The Starry-himax83102-j02 is a 10.51" WUXGA TFT panel. which fits in nicely
with the existing panel-boe-tv101wum-nl6 driver. From the datasheet[1], MIPI
needs to keep the LP11 state before the lcm_reset pin is pulled high, so
increase lp11_before_reset flag.
[1]: https://github.com/HimaxSoftware/D
The STARRY ili9882t is a 10.51" WUXGA TFT LCD panel,
which fits in nicely with the existing panel-boe-tv101wum-nl6
driver. Hence, we add a new compatible with panel specific config.
Signed-off-by: Cong Yang
Reviewed-by: Douglas Anderson
Acked-by: Conor Dooley
---
.../devicetree/bindings/displa
The Starry-ili9882 is a 10.51" WUXGA TFT panel. which fits in nicely with
the existing panel-boe-tv101wum-nl6 driver. From the datasheet,MIPI need
to keep the LP11 state before the lcm_reset pin is pulled high. So add
lp11_before_reset flag.
Signed-off-by: Cong Yang
Reviewed-by: Douglas Anderson
Hello dri maintainers/developers,
This is a 31-day syzbot report for the dri subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/dri
During the period, 0 new issues were detected and 0 were fixed.
In total, 4 issues are still open and 30 have been
On Wed, 2023-05-03 at 14:36 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Track DP enhanced framing properly in the crtc state instead
> of relying just on the cached DPCD everywhere, and hook it
> up into the state check and dump.
>
> v2: Actually set enhanced_framing in .compute_config
On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> encoder->get_config() is not the place where the state
> should be dumped. Get rid of the spam.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 --
> 1 file changed, 2 deleti
On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> There's no need to check for both eDP and fixed_mode when
> deciding whether to do the pfit calculations or not.
>
> Signed-off-by: Ville Syrjälä
> ---
It would be nice to explain _why_ this is not needed. Is it
On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We always check whether combo PHYs need to be re-initialized
> after disabling DC states, which leads to log spam. Switch things
> around so that we only log something when we actually have to
> re-initialized a PHY
If we get signal when waiting for the mmu->lock we do not invalidate
current MMU configuration what might result on undefined behavior.
Additionally there is little or no benefit on break waiting for
ipc->lock. In current code base, we keep this lock for short periods.
Fixes: 263b2ba5fc93 ("accel
From: Andrzej Kacprowski
Turning off the PLL and entering D0i3 will reset the VPU so
an explicit IP reset is redundant.
But if the VPU is active, it may interfere with PLL disabling
and to avoid that, we have to issue an additional IP reset
to silence the VPU before turning off the PLL.
Fixes: a
Hi Christian,
On 25.05.2023 10:30, Christian König wrote:
Hi Karolina,
Am 16.05.23 um 16:02 schrieb Karolina Stolarek:
Hi all,
I'm working on KUnit tests for TTM subsystem (nothing RFC-worthy yet),
with an aim to provide better test coverage for the code used by i915
and Xe. Before digging
Hi,
I notice a regression report on Bugzilla [1]. Quoting from it:
> Original Summary:
> absent both plymouth, and video= on linu lines, vtty[1-6] framebuffers
> produce vast raster right and bottom borders on the larger resolution of two
> displays
>
> To reproduce:
> 1-connect two unequal na
On 5/25/23 17:52, Bagas Sanjaya wrote:
> Hi,
>
> I notice a regression report on Bugzilla [1]. Quoting from it:
>
>> Original Summary:
>> absent both plymouth, and video= on linu lines, vtty[1-6] framebuffers
>> produce vast raster right and bottom borders on the larger resolution of two
>> dis
Hello,
syzbot found the following issue on:
HEAD commit:0dd2a6fb1e34 Merge tag 'tty-6.4-rc3' of git://git.kernel.o..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=12f1564128
kernel config: https://syzkaller.appspot.com/x/.config?x=8944c5b480b57ee6
das
On 25.05.23 12:55, Bagas Sanjaya wrote:
> On 5/25/23 17:52, Bagas Sanjaya wrote:
>>
>> I notice a regression report on Bugzilla [1]. Quoting from it:
>> [...]
>> Anyway, I'm adding it to regzbot:
>>
>> #regzbot introduced: v6.1.12..v6.2.12
>> #regzbot title: vast raster right and bottom borders on
On Sun, 21 May 2023, Uwe Kleine-König wrote:
> After commit b8a1a4cd5a98 ("i2c: Provide a temporary .probe_new()
> call-back type"), all drivers being converted to .probe_new() and then
> 03c835f498b5 ("i2c: Switch .probe() to not take an id parameter") convert
> back to (the new) .probe() to be a
On Tue, 23 May 2023, Geert Uytterhoeven wrote:
> All of gpiod_set_value_cansleep() and gpiod_direction_output() handle
> NULL GPIO pointers just fine, so there is no need to check for that in
> the caller.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> drivers/video/backlight/pwm_bl.c | 9 +++---
On Tue, 23 May 2023, Geert Uytterhoeven wrote:
> make dtbs_check:
>
> arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dtb: backlight:
> 'power-supply' is a required property
> From schema:
> Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml
>
> As that backlight dev
On 5/25/23 17:55, Bagas Sanjaya wrote:
> On 5/25/23 17:52, Bagas Sanjaya wrote:
>> Hi,
>>
>> I notice a regression report on Bugzilla [1]. Quoting from it:
>>
>>> Original Summary:
>>> absent both plymouth, and video= on linu lines, vtty[1-6] framebuffers
>>> produce vast raster right and bottom b
Quoting Jordan Justen (2023-05-21 07:30:52)
> On 2023-05-18 22:11:03, wrote:
> > From: Fei Yang
> >
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out their life cycle, {set, get}_caching ioctl's
> > are no longer supported from MTL onward. With
Instead of registering a struct clk, directly register clk_hw: this
allows us to cleanup a pointer to struct clk from struct mtk_mipi_tx.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 13 ++---
drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 1 -
2 f
This series performs some cleanups to the MediaTek mipi-dsi PHY, used in
various MediaTek SoCs; in particular, it's migrating this driver to
register its clock as clk_hw provider instead and makes use of the devm
function for the same, allowing to remove a pointer to struct clk and
the whole .remov
Switch to devm_of_clk_add_hw_provider() in the probe function: this
also allows to entirely remove the .remove_new() callback, as its
only task was to unregister the clock provider.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 8 +---
1 file change
All of the entries do fit in a maximum of 82 columns, which is
acceptable. While at it, also remove the useless comma on the
last entry and add the usual sentinel comment.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 11 ---
1 file changed, 4 i
Hi Dave & Daniel,
Here goes drm-intel-fixes for v4.6-rc4.
Again just one fix, for pipejoiner config pipe disabling.
Regards, Joonas
***
drm-intel-fixes-2023-05-25:
PIPEDMC disabling fix for bigjoiner config
The following changes since commit 44c026a73be8038f03dbdeef028b642880cf1511:
Linux
On Fri, 2023-05-05 at 16:17 +0200, Thomas Hellström wrote:
> Allow drivers to resolve a WW transaction rollback. This allows for
> 1) Putting a lower-priority transaction to sleep allowing another to
> succeed instead both fighting using trylocks.
> 2) Letting the driver know whether a received -EN
On Thu, 25 May 2023, Joonas Lahtinen wrote:
> Hi Dave & Daniel,
>
> Here goes drm-intel-fixes for v4.6-rc4.
You're seven years late for that one. ;D
J.
>
> Again just one fix, for pipejoiner config pipe disabling.
>
> Regards, Joonas
>
> ***
>
> drm-intel-fixes-2023-05-25:
>
> PIPEDMC disabling
I wouldn't be surprised if 4a16dd9d18a0 is the culprit and that it was
always broken like this with drm fbdev. Anyway, the logs don't indicate we
are actually doing anything wrong, It's just that the tty handling is a
little bonkers as always.
On Thu, May 25, 2023 at 1:37 PM Bagas Sanjaya wrote:
Am 25.05.23 um 14:59 schrieb Thomas Hellström:
On Fri, 2023-05-05 at 16:17 +0200, Thomas Hellström wrote:
Allow drivers to resolve a WW transaction rollback. This allows for
1) Putting a lower-priority transaction to sleep allowing another to
succeed instead both fighting using trylocks.
2) Lett
On Thu, May 25, 2023 at 06:37:05PM +0700, Bagas Sanjaya wrote:
> Oops, again, I messed up the regzbot entry (reporter field still assigned
> to me). Inconclusiving...
>
> #regzbot inconclusive: Wrong reporter assigned (from: doesn't take effect)
>
> Please ignore this thread as I will send a new
On Thu, May 25, 2023 at 01:24:42PM +0200, Thorsten Leemhuis wrote:
> Bagas, thx again for your efforts, much appreciated. But I guess for drm
> drivers that have a line like
>
> B: https://gitlab.freedesktop.org/drm/[...]
>
> in MAINTAINERS (which includes all the popular drm drivers) this just
>
Hi DRM maintainers,
Gentle ping.
Are we happy with moving all Renesas drm drivers to Renesas specific
directory or preference is for separate one??
If it is later, I can send RZ/G2L drm driver separate.
Otherwise, I need to rebase and resend.
Please let me know your preference.
Cheers,
Biju
On Tue, May 23, 2023 at 09:14:46PM -0100, Melissa Wen wrote:
> Place it in drm_property where drm_property_replace_blob and
> drm_property_lookup_blob live. Then we can use the DRM helper for
> driver-specific KMS properties too.
>
> Signed-off-by: Melissa Wen
I know that I've got Cc-ed because
A couple of patches to modify the individualizing somewhat:
The motivation is that we run into trouble with the xe driver doing the
resv individualization in a clean way, having to grab the vm-wide sleeping
lock in a close- or release path which isn't really optimal. While
addressing that, some fl
Clearing the buffer object bulk move is closely tied to individualizing
the resv, since that is when we effectively detach the bo from a vm.
Clearing the bulk move also requires the bo resv, which we have readily
locked at individualizing time without clobbering the much wider vm
lock.
So Clear t
Even if fence copying fails, individualize the resv after the wait.
If fence copying does fail, opportunistically trylock the vm's resv
to attempt to limit the chance of starvation.
Exit individdulizing earlier if the bo type is ttm_bo_type_sg.
Signed-off-by: Thomas Hellström
---
drivers/gpu/d
Rather than coding different delays here and there, use a define for the
resv timeout delay.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/ttm/ttm_bo.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
i
Sounds weird to have a platform restriction on uAPI though. UMD not using this
extension is not a problem, is it?
From: Tvrtko Ursulin
Sent: Thursday, May 25, 2023 1:33 AM
To: Yang, Fei ; intel-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org ; Vivi,
Rodrigo
Subject: Re: [Inte
> On 24/05/2023 21:02, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> This series introduce a new extension for GEM_CREATE,
>> 1. end support for set caching ioctl [PATCH 1/2]
>> 2. add set_pat extension for gem_create [PATCH 2/2]
>>
>> v2: drop one patch that was merged separately
>> comm
Sorry replied on top of wrong thread.
From: Yang, Fei
Sent: Thursday, May 25, 2023 8:12 AM
To: Tvrtko Ursulin ;
intel-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org; Vivi, Rodrigo
Subject: Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at
BO creation
Sounds
On 5/24/23 04:24, Pekka Paalanen wrote:
> On Tue, 23 May 2023 21:14:50 -0100
> Melissa Wen wrote:
>
>> Hook up driver-specific atomic operations for managing AMD color
>> properties and create AMD driver-specific color management properties
>> and attach them according to HW capabilities defin
Hi!
On Wed, May 24, 2023 at 04:27:31PM -0400, Hamza Mahfooz wrote:
> + Kees
>
> On 5/24/23 15:50, Alex Deucher wrote:
> > On Wed, May 24, 2023 at 3:46 PM Felix Kuehling
> > wrote:
> > >
> > > Sure, I think we tried enabling warnings as errors before and had to
> > > revert it because of weird
On 24/05/2023 14:49, Adam Ford wrote:
On Wed, May 24, 2023 at 7:45 AM Fabio Estevam wrote:
Hi Adam,
On Tue, May 23, 2023 at 8:49 PM Adam Ford wrote:
Inki,
I haven't heard back from you on whether or not you want the bindings
patch to be included with me resending the series as V7 or if yo
From: Rob Clark
Fixes undefined symbol when PROC_FS is not enabled.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202305251510.u0r2as7k-...@intel.com/
Fixes: 376c25f8ca47 ("drm/amdgpu: Switch to fdinfo helper")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/amd/a
From: Rob Clark
Some of the fields that are handled by drm_show_fdinfo() crept back in
when rebasing the patch. Remove them again.
Fixes: 376c25f8ca47 ("drm/amdgpu: Switch to fdinfo helper")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 3 ---
1 file changed, 3 del
On Thu, May 25, 2023 at 10:39 AM Neil Armstrong
wrote:
>
> On 24/05/2023 14:49, Adam Ford wrote:
> > On Wed, May 24, 2023 at 7:45 AM Fabio Estevam wrote:
> >>
> >> Hi Adam,
> >>
> >> On Tue, May 23, 2023 at 8:49 PM Adam Ford wrote:
> >>
> >>> Inki,
> >>>
> >>> I haven't heard back from you on wh
On Wed, May 24, 2023 at 04:01:49PM -0700, Justin Chen wrote:
> From: Florian Fainelli
>
> Add a binding document for the Broadcom ASP 2.0 Ethernet
> controller.
>
> Signed-off-by: Florian Fainelli
> Signed-off-by: Justin Chen
> ---
> v5
> - Fix compatible string yaml format to properly c
On 25/05/2023 17:57, Adam Ford wrote:
On Thu, May 25, 2023 at 10:39 AM Neil Armstrong
wrote:
On 24/05/2023 14:49, Adam Ford wrote:
On Wed, May 24, 2023 at 7:45 AM Fabio Estevam wrote:
Hi Adam,
On Tue, May 23, 2023 at 8:49 PM Adam Ford wrote:
Inki,
I haven't heard back from you on whet
Hi,
On Tue, 16 May 2023 09:19:49 +0200, Alexander Stein wrote:
> This map was created from register map from datasheet (section 5.1.2).
> Unused registers are stated by address, so they show up in debugfs as well.
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm
Hi,
On Wed, 03 May 2023 18:33:05 +0200, Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> This patchset contains a proposal to fix the initialization flow for
> the display pipeline used on our i.MX8MM Kontron boards:
>
> i.MX8MM LCDIF -> i.MX8MM DSIM -> TI SN65DSI84 -> 7" LVDS Panel
>
>
On 25/05/2023 18:15, neil.armstr...@linaro.org wrote:
On 25/05/2023 17:57, Adam Ford wrote:
On Thu, May 25, 2023 at 10:39 AM Neil Armstrong
wrote:
On 24/05/2023 14:49, Adam Ford wrote:
On Wed, May 24, 2023 at 7:45 AM Fabio Estevam wrote:
Hi Adam,
On Tue, May 23, 2023 at 8:49 PM Adam Ford
On Thu, May 25, 2023 at 11:19 AM Neil Armstrong
wrote:
>
> On 25/05/2023 18:15, neil.armstr...@linaro.org wrote:
> > On 25/05/2023 17:57, Adam Ford wrote:
> >> On Thu, May 25, 2023 at 10:39 AM Neil Armstrong
> >> wrote:
> >>>
> >>> On 24/05/2023 14:49, Adam Ford wrote:
> On Wed, May 24, 2023
On Thu, May 25, 2023 at 08:37:07AM -0700, Kees Cook wrote:
> Hi!
>
> On Wed, May 24, 2023 at 04:27:31PM -0400, Hamza Mahfooz wrote:
> > + Kees
> >
> > On 5/24/23 15:50, Alex Deucher wrote:
> > > On Wed, May 24, 2023 at 3:46 PM Felix Kuehling
> > > wrote:
> > > >
> > > > Sure, I think we tried
We want to do -Werror builds on our CI. However, non-amdgpu breakages
have prevented us from doing so thus far. Also, there are a number of
additional checks that we should enable, that the community cares about
and are hidden behind -Wextra. So, define DRM_AMDGPU_WERROR to only
enable -Werror for
On Mon, May 22, 2023 at 12:19 PM Biju Das wrote:
> Renesas PMIC RAA215300 exposes two separate i2c devices, one for the main
> device and another for rtc device.
>
> Enhance i2c_new_ancillary_device() to instantiate a real device.
> (eg: Instantiate rtc device from PMIC driver)
>
> Added helper fu
On 5/24/2023 10:14 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
alan: snip
+int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data,
size_t size)
+{
alan:snip
+ /*
+* The GSC binary starts wit
Expose debug capabilities in the KFD topology node's HSA capabilities and
debug properties flags.
Ensure correct capabilities are exposed based on firmware support.
Flag definitions can be referenced in uapi/linux/kfd_sysfs.h.
v2: rebase topology fw check fix with kfd_node struct update
Signed-
The ROCm debugger will attach to a process to debug by PTRACE and will
expect the KFD to prepare a process for the target PID, whether the
target PID has opened the KFD device or not.
This patch is to explicity handle this requirement. Further HW mode
setting and runtime coordination requirements
Introduce the GPU debug operations interface.
For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD GPU
instruction set, provide the necessary interface to allow the debugger
to HW debug-mode set and query exceptions per HSA queue, process or
device.
The runtime_enable interface co
Older HW only supports debugging on a single process because the
SPI debug mode setting registers are device global.
The HWS has supplied a single pinned VMID (0xf) for MAP_PROCESS
for debug purposes. To pin the VMID, the KFD will remove the VMID from
the HWS dynamic VMID allocation via SET_RESOUC
Add missing debug trap registers references and initialize all debug
registers on boot by clearing the hardware exception overrides and the
wave allocation ID index.
The debugger requires that TTMPs 6 & 7 save the dispatch ID to map
waves onto dispatch during compute context inspection.
In order t
Flush delayed restore work in kfd_suspend_all_queues instead of
cancelling. Cancelling the work before it runs results in the queues
becoming permanently disabled. Flushing the work ensures that the
queue suspend/resume state stays balanced.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Introduce the require KGD debug calls that will execute hardware debug
mode setting.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
.../gpu/drm/amd/include/kgd_kfd_interface.h | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd
Add a debug operation that allows the debugger to send an exception
directly to runtime through a payload address.
For memory violations, normal vmfault signals will be applied to
notify runtime instead after passing in the saved exception data
when a memory violation was raised to the debugger.
To enable HW debug mode per process, all devices must be debug enabled
successfully. If a failure occures, rewind the enablement of debug mode
on the enabled devices.
A power management scenario that needs to be considered is HW
debug mode setting during GFXOFF. During GFXOFF, these registers
wi
Implement the per-device calls to enable or disable HW debug mode
for GFX11.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 38 +++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkf
Similar to GFX9 debug devices, set the hardware debug mode by draining
the SPI appropriately prior the mode setting request.
Because GFX10 has waves allocated by the work group boundary and each
SE's SPI instances do not communicate, the SPI drain time is much longer.
This long drain time will be
The HWS schedule allows a grace period for wave completion prior to
preemption for better performance by avoiding CWSR on waves that can
potentially complete quickly. The debugger, on the other hand, will
want to inspect wave status immediately after it actively triggers
preemption (a suspend funct
Implement the per-device calls to enable or disable HW debug mode for
GFX9 prior to GFX9.4.1.
GFX9.4.1 and onward will require their own enable/disable sequence as
follow on patches.
When hardware debug mode setting is requested, waves will inherit
these settings in the Shader Processor Input's (
GFX9.4.2 now supports per-VMID debug mode controls registers
(SPI_GDBG_PER_VMID_CNTL).
Because the KFD lets the HWS handle PASID-VMID mapping, the KFD will
forward all debug mode setting register writes to the HWS scheduler
using a new MAP_PROCESS API, so instead of writing to registers, return
th
Similar to the F32 HWS, the RS64 HWS for GFX11 now supports a multi-process
debug API.
The skip_process_ctx_clear ADD_QUEUE requirement is to prevent the MES
from clearing the process context when the first queue is added to the
scheduler in order to maintain debug mode settings during queue preem
Due to a HW bug, waves in only half the shader arrays can enter trap.
When starting a debug session, relocate all waves to the first shader
array of each shader engine and mask off the 2nd shader array as
unavailable.
When ending a debug session, re-enable the 2nd shader array per
shader engine.
On GFX9.4.1, the implicit wait count instruction on s_barrier is
disabled by default in the driver during normal operation for
performance requirements.
There is a hardware bug in GFX9.4.1 where if the implicit wait count
instruction after an s_barrier instruction is disabled, any wave that
hits a
Allow the debugger to query a single queue, device and process
exception.
The KFD should also return the GPU or Queue id of the exception.
The debugger also has the option of clearing exceptions after
being queried.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd
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