On Mon, May 22, 2023 at 09:06:37PM +0200, Thomas Zimmermann wrote:
> The fbdev framebuffer is I/O memory, so clear it with fb_memset_io().
> Fixes the following sparse warning:
>
> ../drivers/gpu/drm/gma500/fbdev.c:234:20: warning: incorrect type in argument
> 1 (different address spaces)
> ../dr
On Tue, 23 May 2023 at 04:58, Abhinav Kumar wrote:
>
>
>
> On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
> > Rework dpu_encoder initialization code, simplifying calling sequences
> > and separating common init parts.
> >
> > Changes since v1:
> > - Withdrawn two pathes for a later consideration
>
On 23/05/2023 01:22, Abhinav Kumar wrote:
Sorry for the delay, other topics delayed my response on this one.
On 5/18/2023 6:50 PM, Dmitry Baryshkov wrote:
On 19/05/2023 02:46, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to a
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson
>
> Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
>
> Signed-off-by: Bjorn Andersson
> Signed-off-by: Bjorn Andersson
> ---
Reviewed-by: Konrad Dybcio
Konrad
>
> Changes since v1:
> - Moved a690 to a
On 23/05/2023 09:20, Dmitry Baryshkov wrote:
On Tue, 23 May 2023 at 04:58, Abhinav Kumar wrote:
On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
Changes since v1:
- Withdrawn two pathes for
On 21.05.2023 17:44, Dmitry Baryshkov wrote:
> On 19/05/2023 20:04, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
>>
>> {.fl = 0, .lut = 0x0011223344556677 },
>>
>> due to the fact
On 21.05.2023 18:10, Dmitry Baryshkov wrote:
> On 19/05/2023 20:04, Konrad Dybcio wrote:
>> Add basic SM6375 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153
>> +
>>
v4 -> v5:
- Rebase on next-20230522 (drop regdma, drop external dependencies)
- Reuse sdm845_vbif
- Resize non-DSI INTFs to 0x280 (no TE block)
- Fix up 6375 mdss bindings example
- Rewrite reasoning of dropping the QoS LUT entry in
"drm/msm/dpu: Add SM6350 support"
- pick up tags
- add DSC block
Add the DSI host found on SM6350.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docume
Add the DSI host found on SM6375.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docume
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
1 file changed, 216 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
b/Documentation/devicetree/bindings/dis
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the lack of support for selecting between portrait and landscape
LUT settings (for danger and safe LUTs) and no full s
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +
1 file changed, 214 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
b/Documentation/devicetree/bindings/dis
SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with
the main exception being that the last one requires an additional
throttle clock.
It is not well understood yet, but failing to toggle it on makes the
display hardware stall and not output any frames.
Document SM6350 and SM6375
Add support for MDSS on SM6350.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731a
Add basic SM6375 support to the DPU1 driver to enable display output.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 139 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/di
Add support for MDSS on SM6375.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..0564
It got broken at some point, fix it up.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/dr
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson
>
> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> SC8280XP.
>
> Signed-off-by: Bjorn Andersson
> Signed-off-by: Bjorn Andersson
> ---
It does not look like you tested the DTS against bindings. Please ru
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson
>
> Add memory reservation for the zap-shader and enable the Adreno SMMU,
> GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
> Lenovo ThinkPad X13s.
>
> Signed-off-by: Bjorn Andersson
> Signed-off-by:
Hi,
On 2023/5/23 12:26, Sui Jingfeng wrote:
Hi,
On 2023/5/22 19:29, Jani Nikula wrote:
In general, do not use unsigned types in arithmethic to avoid negative
values, because most people will be tripped over by integer promotion
rules, and you'll get negative values anyway.
Here I'm sure abo
On 2023/5/22 16:51, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+
+static void lsdc_crtc0_soft_reset(struct lsdc_crtc *lcrtc)
+{
+ struct lsdc_device *ldev = lcrtc->ldev;
+ u32 val;
+
+ val = lsdc_rreg32(ldev, LSDC_CRTC0_CFG_REG);
+
+ val &= CFG_VALID_BITS_MASK
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
Abhinav Kumar writes:
There is no need to add the 100ms delay back yet.
thanks for posting this but NAK on this patch till we post the fix this
week.
Appreciate a bit of patience till then.
>>>
>>> This regression is already part of the 6.3 stable release series. Will
On 2023/5/22 16:29, Sui Jingfeng wrote:
On 2023/5/22 16:09, WANG Xuerui wrote:
On 2023/5/22 16:02, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
--- /dev/null
+++ b/drivers/gpu/drm/loongson/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config DRM_LOONGSON
+
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
On 2023/5/22 17:25, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+ * LS3A4000/LS3A5000/LS3A6000 CPU, they are equipped with on-board
video RAM
+ * typically. While LS2K0500/LS2K1000/LS2K2000 are low cost SoCs
which share
+ * the system RAM as video RAM, they don't has a dedi
On 2023/5/22 18:17, Sui Jingfeng wrote:
Hi,
On 2023/5/22 18:05, WANG Xuerui wrote:
On 2023/5/22 17:49, Sui Jingfeng wrote:
Hi,
On 2023/5/22 17:28, WANG Xuerui wrote:
On 2023/5/22 17:25, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+ * LS3A4000/LS3A5000/LS3A6000 CPU, they
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
On 5/22/23 21:13, Sui Jingfeng wrote:
Hi,
On 2023/5/22 18:25, WANG Xuerui wrote:
On 2023/5/22 18:17, Sui Jingfeng wrote:
Hi,
On 2023/5/22 18:05, WANG Xuerui wrote:
On 2023/5/22 17:49, Sui Jingfeng wrote:
Hi,
On 2023/5/22 17:28, WANG Xuerui wrote:
On 2023/5/22 17:25, Sui Jingfeng wrote:
H
On 2023/5/22 16:02, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
--- /dev/null
+++ b/drivers/gpu/drm/loongson/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config DRM_LOONGSON
+ tristate "DRM support for Loongson Graphics"
+ depends on DRM && PCI && MMU
On 2023/5/22 17:05, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+++ b/drivers/gpu/drm/loongson/lsdc_debugfs.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+#include
+
+#include "lsdc_benchmar
On Mon, May 22, 2023 at 11:27 AM Conor Dooley wrote:
>
> On Fri, May 19, 2023 at 02:19:40PM -0700, Justin Chen wrote:
> > From: Florian Fainelli
> >
> > Add a binding document for the Broadcom ASP 2.0 Ethernet controller.
> >
> > Signed-off-by: Florian Fainelli
> > Signed-off-by: Justin Ch
On 2023/5/22 16:14, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+
+ If in doubt, say "N".
diff --git a/drivers/gpu/drm/loongson/Makefile
b/drivers/gpu/drm/loongson/Makefile
new file mode 100644
index ..9158816ece8e
--- /dev/null
+++ b/drivers/gpu/drm/loongs
Le sam. 20 mai 2023 à 22:49, Dmitry Baryshkov
a écrit :
>
> On 20/04/2023 20:47, Jeykumar Sankaran wrote:
> >
> >
> > On 4/19/2023 3:23 PM, Dmitry Baryshkov wrote:
> >> On 19/04/2023 17:41, Arnaud Vrac wrote:
> >>> This avoids using two LMs instead of one when the display width is lower
> >>> than
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
On 5/22/23 11:17, Conor Dooley wrote:
On Fri, May 19, 2023 at 02:19:39PM -0700, Justin Chen wrote:
> The ASP 2.0 Ethernet controller uses a brcm unimac.
>
> Signed-off-by: Florian Fainelli
> Signed-off-by: Justin Chen
> ---
> Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml |
On 2023/5/22 17:49, Sui Jingfeng wrote:
Hi,
On 2023/5/22 17:28, WANG Xuerui wrote:
On 2023/5/22 17:25, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+ * LS3A4000/LS3A5000/LS3A6000 CPU, they are equipped with on-board
video RAM
+ * typically. While LS2K0500/LS2K1000/LS2K2000
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
strlcpy() reads the entire source buffer first.
This read may exceed the destination size limit.
This is both inefficient and can lead to linear read
overflows if a source string is not NUL-terminated [1].
In an effort to remove strlcpy() completely [2], replace
strlcpy() here with strscpy().
No re
As the LVDS data-mapping property is required in multiple bindings: move
it to separate file and include instead of duplicating it.
Signed-off-by: Johannes Zink
---
Changes:
v1 -> v2: worked in Rob's review findings (thank you for reviewing my
work): extract common properties to
ml | 26 ++-
drivers/gpu/drm/panel/panel-simple.c | 39 +-
4 files changed, 155 insertions(+), 69 deletions(-)
---
base-commit: 33a86170888b7e4aa0cea94ebb9c67180139cea9
change-id: 20230523-simplepanel_support_nondefault_datamapping-13c3f2ea28f8
Best regards,
--
Johannes Zink
Some panels support multiple LVDS data mapping formats, which can be
used e.g. run displays on jeida-18 format when only 3 LVDS lanes are
available.
Add parsing of an optional data-mapping devicetree property, which also
touches up the bits per color to match the bus format.
Signed-off-by: Johann
Some Displays support more than just a single default lvds data mapping,
which can be used to run displays on only 3 LVDS lanes in the jeida-18
data-mapping mode.
Add an optional data-mapping property to allow overriding the default
data mapping. As it does not generally apply to any display and b
Hello Thomas,
On Mon, May 22, 2023 at 9:17 PM Thomas Zimmermann wrote:
>
> The fbdev framebuffer is in system memory. Store the address in
> the field 'screen_buffer'. Fixes the following sparse warning.
>
> ../drivers/gpu/drm/msm/msm_fbdev.c:124:26: warning: incorrect type in
> assignment (diff
On 23.05.2023 09:59, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
>> From: Bjorn Andersson
>>
>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>> SC8280XP.
>>
>> Signed-off-by: Bjorn Andersson
>> Signed-off-by: Bjorn Andersson
>> ---
> It does no
From: Arnd Bergmann
The .resync_fifo_dccg_dio() callback pointer was added in an #ifdef block,
but is called unconditionally:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2292:31:
error: 'struct hwseq_private_funcs' has no member named 'resync_fifo_dccg_dio'
Add the sa
On Tue, 23 May 2023 09:46:15 +0200, Konrad Dybcio wrote:
> Document the SM6350 MDSS.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214
> +
> 1 file changed, 214 insertions(+)
>
My bot found errors running 'make DT_CHECKER_
On Tue, 23 May 2023 09:46:16 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
> +
> 1 file changed, 216 insertions(+)
>
My bot found errors running 'make DT_CHECKER_
Hi Fei,
finally... pushed in drm-intel-gt-next! :)
Andi
On Thu, May 18, 2023 at 10:11:01PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This series introduce a new extension for GEM_CREATE,
> 1. end support for set caching ioctl [PATCH 1/2]
> 2. add set_pat extension for gem_create [P
From: 15330273...@189.cn <15330273...@189.cn>
> Sent: 23 May 2023 05:27
>
> On 2023/5/22 19:29, Jani Nikula wrote:
> > In general, do not use unsigned types in arithmethic to avoid negative
> > values, because most people will be tripped over by integer promotion
> > rules, and you'll get negative
On Tue, May 16, 2023 at 02:40:27PM +0300, Ville Syrjälä wrote:
> On Tue, May 16, 2023 at 01:43:44PM +0300, Lisovskiy, Stanislav wrote:
> > On Fri, May 12, 2023 at 11:54:16AM +0530, Ankit Nautiyal wrote:
> > > Currently, we take the max lane, rate and pipe bpp, to get the maximum
> > > compressed bp
On 23/05/2023 00:09, Andi Shyti wrote:
Hi Tvrtko,
On Mon, May 22, 2023 at 12:59:27PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
In preparation for exposing via sysfs add helpers for managing rps
thresholds.
v2:
* Force sw and hw re-programming on threshold change.
Signed-off-by:
On Mon, May 22, 2023 at 10:18 PM Karol Herbst wrote:
>
> This fixes a NULL pointer access inside nvkm_acr_oneinit in case necessary
> firmware files couldn't be loaded.
>
> Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/212
> Fixes: 4b569ded09fd ("drm/nouveau/acr/ga102: initial suppor
On Wed, 17 May 2023, Jani Nikula wrote:
> On Wed, 17 May 2023, Krzysztof Kozlowski
> wrote:
>> On 17/05/2023 11:28, Jani Nikula wrote:
>>> On Thu, 11 May 2023, Krzysztof Kozlowski
>>> wrote:
Statically allocated array of pointers to hwmon_channel_info can be made
const for safety.
>>
On 22/05/2023 12:18, Biju Das wrote:
> Renesas PMIC RAA215300 exposes two separate i2c devices, one for the main
> device and another for rtc device.
>
> Enhance i2c_new_ancillary_device() to instantiate a real device.
> (eg: Instantiate rtc device from PMIC driver)
>
> Added helper function __i2
Hi,
On 2023/5/23 16:50, David Laight wrote:
From: 15330273...@189.cn <15330273...@189.cn>
Sent: 23 May 2023 05:27
On 2023/5/22 19:29, Jani Nikula wrote:
In general, do not use unsigned types in arithmethic to avoid negative
values, because most people will be tripped over by integer promotion
From: Sui Jingfeng
Both mode->crtc_htotal and mode->crtc_vtotal are u16 type, using a u32 is
to store the result instead of int.
Signed-off-by: Sui Jingfeng
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
https://bugzilla.kernel.org/show_bug.cgi?id=201957
Stuart Foster (smf-li...@virginmedia.com) changed:
What|Removed |Added
CC||smf-li...@virg
Due to the initial confusion about MIPI_DSI_MODE_EOT_PACKET, properly
renamed to MIPI_DSI_MODE_NO_EOT_PACKET, reflecting its actual meaning,
both the DSI_TXRX_CON register setting for bit (HSTX_)DIS_EOT and the
later calculation for horizontal sync-active (HSA), back (HBP) and
front (HFP) porches g
On Mon, May 22, 2023 at 10:47:50AM +0200, Marijn Suijten wrote:
> On 2023-05-22 10:48:01, Dan Carpenter wrote:
> > The "vsync_hz" variable is used to store negative error codes so it
> > needs to be signed for the error checking to work correctly.
>
> Nicely spotted, but it it looks like we have m
Hi
Am 23.05.23 um 09:00 schrieb Patrik Jakobsson:
On Mon, May 22, 2023 at 09:06:37PM +0200, Thomas Zimmermann wrote:
The fbdev framebuffer is I/O memory, so clear it with fb_memset_io().
Fixes the following sparse warning:
../drivers/gpu/drm/gma500/fbdev.c:234:20: warning: incorrect type in ar
Hi Tvrtko,
> > > + /* Force reset. */
> > > + rps->last_freq = -1;
> > > + mutex_lock(&rps->power.mutex);
> > > + rps->power.mode = -1;
> > > + mutex_unlock(&rps->power.mutex);
> > > +
> > > + intel_rps_set(rps, clamp(rps->cur_freq,
> > > + rps->min_freq_softlimit,
> > > +
On Tue, May 23, 2023 at 1:29 PM Thomas Zimmermann wrote:
>
> Hi
>
> Am 23.05.23 um 09:00 schrieb Patrik Jakobsson:
> > On Mon, May 22, 2023 at 09:06:37PM +0200, Thomas Zimmermann wrote:
> >> The fbdev framebuffer is I/O memory, so clear it with fb_memset_io().
> >> Fixes the following sparse warni
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1069:43: error:
‘res_create_maximus_funcs’ defined but not used
[-Werror=unused-const-variable=]
1069 | static const struct resource_create_funcs res_create_maximus_funcs = {
|
On Tue, 23 May 2023 10:54:11 +0100
Catalin Marinas wrote:
> On Wed, May 17, 2023 at 01:27:48PM +0200, Petr Tesařík wrote:
> > On Wed, 17 May 2023 08:35:10 +0200
> > Petr Tesařík wrote:
> > > Anyway, my greatest objection to allocating additional swiotlb chunks is
> > > that _all_ of them must
From: Sandor Yu
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor
Port the HDMI PHY driver for Qualcomm MSM8974 / APQ8074 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig | 11 +
drivers/phy/qualcomm/Makefile| 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-msm8974.c | 531 +++
3 files chang
Port the HDMI PHY driver for Qualcomm MSM8260 / MSM8660 / APQ8060 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig | 11 +
drivers/phy/qualcomm/Makefile| 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-msm8x60.c | 353 +++
3 f
Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
generic part and the msm8996 part. When adding support for msm8992/4 and
msm8998 (which also employ QMP for HDMI PHY), one will have to provide
the PLL programming part only.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualco
The MSM HDMI PHYs have been using the ad-hoc approach / API instead of
using the generic API framework. Move all the PHYs to
drivers/phy/qualcomm and rework them to use generic PHY framework. This
way all the QMP-related code is kept close. Also in future this will
allow us to use a common set of f
The "uni" PLL is shared between several PHYS: APQ8064's SATA,
MSM8974/APQ8084 HDMI, MSM8916 DSI, MSM8974/APQ8084 DSI.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 23 +-
drivers/phy/qualcomm/phy-qcom-uniphy.h | 32
2 fi
Port the HDMI PHY driver for Qualcomm MSM8960 / APQ8064 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig | 11 +
drivers/phy/qualcomm/Makefile| 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-msm8960.c | 744 +++
3 files chang
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
In consequent modeset calls, the atomic_pre_enable() will be called
several times without calling atomic_post_disable() inbetween. Thus
iframes will not be updated for the next mode. Fix this by setting the
iframe outside of the !power_on check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/dr
Import register definitions from 28nm DSI and HDMI PHYs, adding more UNI
PHY registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-uniphy.h | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.h
b/drivers/phy
Change the MSM HDMI driver to use generic PHY subsystem. Moving PHY
drivers allows better code sharing with the rest of the PHY system.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 6 ---
drivers/gpu/drm/msm/hdmi/hdmi.c| 58 +++--
drivers/
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 62ce1455f974..fbcf4dd91cd9 100644
--- a/drivers/gpu/dr
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 217 ---
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 51 --
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 765 ---
drivers/gpu/drm/msm/
In preparation to converting MSM HDMI driver to use PHY framework, which
requires phy_power_on() calls to be paired with phy_power_off(), add a
conditional call to msm_hdmi_phy_powerdown() before the call to
msm_hdmi_phy_powerup().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdm
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24 ---
drivers/gpu/drm/msm/hdmi/hdmi.h| 6 +
drivers/gpu/drm/msm/hdmi/hdmi_
On Tue, May 23, 2023 at 10:04:40AM +0200, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Add memory reservation for the zap-shader and enable the Adreno SMMU,
> > GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
>
On Mon, May 22, 2023 at 04:02:45PM -0700, Kuogee Hsieh wrote:
> The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
> false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
> case. HDP related interrupts can not be enabled until internal_hpd is set
> to tr
Currently, it is possible for the composer to be set as enabled and then
as disabled without a proper call for the vkms_vblank_simulate(). This
is problematic, because the driver would skip one CRC output, causing CRC
tests to fail. Therefore, we need to make sure that, for each time the
composer i
On 23/05/2023 15:35, Bjorn Andersson wrote:
On Mon, May 22, 2023 at 04:02:45PM -0700, Kuogee Hsieh wrote:
The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
case. HDP related interrupts can not be
On 23/05/2023 15:14, Dmitry Baryshkov wrote:
The MSM HDMI PHYs have been using the ad-hoc approach / API instead of
using the generic API framework. Move all the PHYs to
drivers/phy/qualcomm and rework them to use generic PHY framework. This
way all the QMP-related code is kept close. Also in fut
clang with W=1 reports
drivers/gpu/drm/i915/display/intel_display.c:6012:3: error: unannotated
fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
case I915_FORMAT_MOD_X_TILED:
^
Only one case and the default does anything in this switch, so it sho
On 23.05.2023 14:28, Bjorn Andersson wrote:
> On Tue, May 23, 2023 at 10:04:40AM +0200, Konrad Dybcio wrote:
>>
>>
>> On 23.05.2023 03:15, Bjorn Andersson wrote:
>>> From: Bjorn Andersson
>>>
>>> Add memory reservation for the zap-shader and enable the Adreno SMMU,
>>> GPU clock controller, GMU
Hello,
pon, 22. svi 2023. u 10:55 napisao je:
>
> On 19/05/2023 16:24, Paulo Pavacic wrote:
> > Fannal C3004 is a 2 lane MIPI DSI 480x800 panel which requires
> > initialization with DSI DCS commands. After some commands delay is required.
>
> By curiosity, on which board is this panel used ?
>
On Tue, 23 May 2023, Tom Rix wrote:
> clang with W=1 reports
> drivers/gpu/drm/i915/display/intel_display.c:6012:3: error: unannotated
> fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
> case I915_FORMAT_MOD_X_TILED:
> ^
>
> Only one case and t
On Mon, Apr 10, 2023 at 09:52:26PM +0300, Dmitry Baryshkov wrote:
> If the Adreno SMMU is dma-coherent, allocation will fail unless we
> disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
> coherent SMMUs (like we have on sm8350 platform).
>
> Fixes: 54af0ceb7595 ("arm64: dts
On 22/05/2023 23:17, Ashutosh Dixit wrote:
Clearing out report id and timestamp as means to detect unlanded reports
only works if report size is power of 2. That is, only when report size is
a sub-multiple of the OA buffer size can we be certain that reports will
land at the same place each time
On 23/05/2023 10:31, Neil Armstrong wrote:
On 23/05/2023 09:20, Dmitry Baryshkov wrote:
On Tue, 23 May 2023 at 04:58, Abhinav Kumar
wrote:
On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
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