> So, the driver has to be panel-fannal-c3004.c and binding to be
> fannal,c3004.yaml.
I believe I have covered this and all the other problems in following
patch which I will submit as a V3 of the conversation in a patchset
together with a driver:
Add dt-bindings documentation for panel-mipi-ds
The previous patch is not based on drm-misc-next, resend this series.
Support Starry-himax83102-j02 and Starry-ili9882t TDDI MIPI-DSI panel,
set the default high for RST at boe_panel_add and add lp11_before_reset flag.
Cong Yang (2):
drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI pan
The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
it seems that the touch can communicate successfully only when the RST
signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
let's set the default high for RST at boe_panel_add. Also MIPI needs to
keep the LP11 st
On 18/05/2023 15:44, Tetsuo Handa wrote:
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says, flush_scheduled_work() is dangerous and will be forbidden.
i915 became the last flush_scheduled_work() user, but developers cannot
find time for auditing which work i
The Starry-ili9882 panel also is a TDDI IC. From the datasheet,panel
need the RST signal is high when touch communicate and also MIPI needs
to keep the LP11 state before the lcm_reset pin is pulled high. So add
enable_gpio_init_value and lp11_before_reset flag.
Signed-off-by: Cong Yang
---
.../g
drmm_mutex_init() needs to be defined as a macro if we want
lockdep to classify locks properly. If we don't do that, all locks
will be considered as belonging to the same lock class, leading to
false positive deadlock reports.
Signed-off-by: Boris Brezillon
Reported-by: Sarah Walker
---
drivers
On Fri, 19 May 2023 at 09:55, Boris Brezillon
wrote:
>
> drmm_mutex_init() needs to be defined as a macro if we want
> lockdep to classify locks properly. If we don't do that, all locks
> will be considered as belonging to the same lock class, leading to
> false positive deadlock reports.
>
> Sign
In mutex_init() lockdep identifies a lock by defining a special static
key for each lock class. However if we wrap the macro in a function,
like in drmm_mutex_init(), we end up generating:
int drmm_mutex_init(struct drm_device *dev, struct mutex *lock)
{
static struct lock_class_key __key;
Hi
On Fri, May 19, 2023 at 10:55:25AM +0200, Boris Brezillon wrote:
> drmm_mutex_init() needs to be defined as a macro if we want
> lockdep to classify locks properly. If we don't do that, all locks
> will be considered as belonging to the same lock class, leading to
> false positive deadlock repo
On Fri, 19 May 2023 10:07:33 +0100
Matthew Auld wrote:
> In mutex_init() lockdep identifies a lock by defining a special static
> key for each lock class. However if we wrap the macro in a function,
> like in drmm_mutex_init(), we end up generating:
>
> int drmm_mutex_init(struct drm_device *dev
On Fri, 19 May 2023 10:05:27 +0100
Matthew Auld wrote:
> On Fri, 19 May 2023 at 09:55, Boris Brezillon
> wrote:
> >
> > drmm_mutex_init() needs to be defined as a macro if we want
> > lockdep to classify locks properly. If we don't do that, all locks
> > will be considered as belonging to the sa
Hi Inki,
> > > @@ -469,8 +469,6 @@ static int vidi_remove(struct platform_device *pdev)
> > > if (ctx->raw_edid != (struct edid *)fake_edid_info) {
> > > kfree(ctx->raw_edid);
> > > ctx->raw_edid = NULL;
> > > -
> > > - return -EINVAL;
> >
> > It doesn't look right t
On Fri, May 19, 2023 at 10:07:33AM +0100, Matthew Auld wrote:
> In mutex_init() lockdep identifies a lock by defining a special static
> key for each lock class. However if we wrap the macro in a function,
> like in drmm_mutex_init(), we end up generating:
>
> int drmm_mutex_init(struct drm_device
On 5/18/23 22:35, Alan Stern wrote:
On Thu, May 18, 2023 at 09:06:12PM +0200, Helge Deller wrote:
* Alan Stern :
On Thu, May 18, 2023 at 04:16:33PM +0200, Helge Deller wrote:
On 5/18/23 15:54, Alan Stern wrote:
In this case it looks like dlfb_usb_probe() or one of the routines it
calls is wro
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, May 17, 2023 3:58 PM
> To: David Airlie ; Daniel Vetter ; Jani
> Nikula ; Kandpal, Suraj
> ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Rob Clark
> ; Abhinav Kumar ;
> Sean Paul ; Marijn Suijten
>
> Cc: Ville
On 2023-05-19 01:40:19, Dmitry Baryshkov wrote:
>
> On 19/05/2023 01:09, Kuogee Hsieh wrote:
> >
> > On 5/17/2023 3:31 PM, Marijn Suijten wrote:
> >>
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> >>> @@ -139,6 +139,11 @@ static inl
On 2023-05-19 00:40:03, Dmitry Baryshkov wrote:
>
> On 19/05/2023 00:39, Marijn Suijten wrote:
> > On 2023-05-19 00:06:15, Dmitry Baryshkov wrote:
> >> On 18/05/2023 22:14, Marijn Suijten wrote:
> >>> On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
> The src_blk declares a lame copy of main S
Hi Biju,
On Thu, May 18, 2023 at 1:37 PM Biju Das wrote:
> Renesas PMIC RAA215300 exposes two separate i2c devices, one for the main
> device and another for rtc device.
>
> Enhance i2c_new_ancillary_device() to instantiate a real device.
> (eg: Instantiate rtc device from PMIC driver)
>
> Added
This series brings some niceties in preparation for A7xx introduction.
It should be fully independent of the GMU wrapper series.
Signed-off-by: Konrad Dybcio
---
Changes in v2:
- Drop switching to using the GMU_AO counter in timestamp
- Add a definition for REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, may
Some specific SKUs leave certain protection range registers empty.
Allow for that behavior.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/m
Add a definition of the REG_A6XX_GMU_AHB_FENCE_STATUS_CLR register.
This may be substituted with a mesa header sync after MR22901 is merged.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno
Change the order of region allocations to make the addresses match
downstream. This shouldn't matter very much, but helps eliminate one
more difference when comparing register accesses.
Also, make the log region 16K long. That's what it is, unconditionally
on A6xx and A7xx.
Signed-off-by: Konrad
We have the necessary information, so explain which bit does what.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
inde
The GMU force shutdown sequence involves some additional register cleanup
which was not implemented previously. Do so.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/driver
While it's not very well understood, there is some sort of a fault
handler implemented in the GMU firmware which triggers when a certain
bit is set, resulting in the M3 core not booting up the way we expect
it to.
Write a magic value to a magic register to hopefully prevent that
from happening.
S
Thanks!
Reviewed-by: Luben Tuikov
Applied to drm-misc-fixes.
Regards,
Luben
On 2023-05-17 08:52, Vladislav Efanov wrote:
> The rq pointer points inside the drm_gpu_scheduler structure. Thus
> it can't be NULL.
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Fixes: c
On Thu, May 18, 2023 at 8:06 PM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the amdgpu tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c: In function 'amdgpu_ctx_init':
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c:348:26: er
Series is:
Reviewed-by: Alex Deucher
On Thu, May 18, 2023 at 9:03 AM Luben Tuikov wrote:
>
> On 2023-05-17 19:35, Luben Tuikov wrote:
> > Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
> > is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
>
On 19/05/2023 00:29, Marijn Suijten wrote:
According to various downstream sources the PCC sub-block inside DSPP is
version 4.0 since DPU 4.0 and higher, including SC7[12]80 at DPU version
6.2 and 7.2 respectively. After correcting the version this struct
becomes identical to sm8150_dspp_sblk wh
On 5/17/23 10:46, Jani Nikula wrote:
On Tue, 16 May 2023, Arnd Bergmann wrote:
From: Arnd Bergmann
Building with W=1 shows that a header needs to be included to
make the prototypes visible:
drivers/video/fbdev/i810/i810_dvt.c:194:6: error: no previous prototype for
'round_off_xres' [-Werror
* Geert Uytterhoeven :
> Hi Arnd,
>
> On Tue, May 16, 2023 at 10:23 PM Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > There is a global function with this name on sparc, but no
> > global declaration:
> >
> > drivers/video/fbdev/core/fbmem.c:1469:15: error: no previous prototype for
> > 'g
Hi Helge,
On Fri, May 19, 2023 at 4:37 PM Helge Deller wrote:
> * Geert Uytterhoeven :
> > On Tue, May 16, 2023 at 10:23 PM Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > There is a global function with this name on sparc, but no
> > > global declaration:
> > >
> > > drivers/video/f
On 5/16/23 14:24, Ville Syrjälä wrote:
On Tue, May 16, 2023 at 01:00:33PM +0200, Niklas Schnelle wrote:
Just below the removed lines par->clk_wr_offset is hard coded to 3 so
there is no use in determining a different clock just to then ignore it
anyway. This also removes the only I/O port use re
On 5/19/23 16:44, Geert Uytterhoeven wrote:
Hi Helge,
On Fri, May 19, 2023 at 4:37 PM Helge Deller wrote:
* Geert Uytterhoeven :
On Tue, May 16, 2023 at 10:23 PM Arnd Bergmann wrote:
From: Arnd Bergmann
There is a global function with this name on sparc, but no
global declaration:
driver
The array of CRTC in the struct msm_drm_private duplicates a list of
CRTCs in the drm_device. Drop it and use the existing list for CRTC
enumeration.
Signed-off-by: Dmitry Baryshkov
---
This was a part of https://patchwork.freedesktop.org/series/105302/
Changes since v6:
- Dropped applied patche
On Fri, May 19, 2023 at 10:07:33AM +0100, Matthew Auld wrote:
In mutex_init() lockdep identifies a lock by defining a special static
key for each lock class. However if we wrap the macro in a function,
like in drmm_mutex_init(), we end up generating:
int drmm_mutex_init(struct drm_device *dev, s
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v4 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> Hi Biju,
>
> On Thu, May 18, 2023 at 1:37 PM Biju Das
> wrote:
> > Renesas PMIC RAA215300 exposes two separate i2c devices, one for the
> > main device and another for rtc device.
>
Function rv740_get_decoded_reference_divider() may return 0 due to
unpredictable reference divider value calculated in
radeon_atom_get_clock_dividers(). This will lead to
division-by-zero error once that value is used as a divider
in calculating 'clk_s'.
While unlikely, this issue should nonetheles
On Fri, May 19, 2023 at 12:38:15PM +0200, Helge Deller wrote:
> Patch looks good and survived the test.
>
> Will you send a proper patch to the fbdev mailing list, so that I can
> include it?
Will do.
While you're working on this driver, here's a suggestion for another
improvement you can make.
In preparation of moving resource allocation to the probe time, allow
MSM KMS drivers to pass struct msm_kms pointer via msm_drv_probe().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers
This patchset was left untouched for almost a year. Let's reiterate it
in attempt to solve the long-standing issue.
As discussed several times on IRC, move display subdriver resource
allocation from kms_init to probe time to let it bail early.
Changes since v1:
- Dropped the applied patch
- Picke
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 100 ++-
1 file chan
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers
In preparation of moving resource allocation to the probe time, allow
MSM KMS drivers to pass struct msm_kms pointer via msm_drv_probe().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp
On 14/01/2023 02:49, Abhinav Kumar wrote:
On 1/2/2023 7:47 AM, Dmitry Baryshkov wrote:
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dp
With the QAIC driver in -next, I'd like to suggest some MHI changes that
specific to AIC100 devices, but perhaps provide a framework for other
device oddities.
AIC100 devices technically violate the MHI spec in two ways. Sadly, these
issues comes from the device hardware, so host SW needs to work
AIC100 does not initialize the SOC_HW_VERSION MHI register as expected.
Some instances of AIC100 are observed to have 0x in this register
which makes the controller think that the link is down and return an error
up to MHI. This results in a failed initialization.
Allow these cards to init
Some devices might require special handling due to flawed implementations
or other reasons. Implement a quirk framework to handle these situations.
Implement the first quirk in this framework -
MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE
The MHI spec indicates that the MHI device must initialize the
SOC_
Hey Paulo,
On Fri, May 19, 2023 at 04:24:55PM +0200, Paulo Pavacic wrote:
>
> Added fannal to vendor-prefixes and dt bindings for Fannal C3004.
> Fannal C3004 is a 480x800 MIPI DSI Panel which requires
> DCS initialization sequences with certain delays between certain
> commands.
>
> Signed-off-
On 03/04/2023 19:11, Dmitry Baryshkov wrote:
On Mon, 3 Apr 2023 at 15:01, Vinod Polimera wrote:
On Fri, 31 Mar 2023 at 16:59, Vinod Polimera
wrote:
In certain CPU stress conditions, there can be a delay in scheduling commit
work and it was observed that PSR commit from a different work que
On 19/04/2023 18:43, Mark Yacoub wrote:
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change in v10 is handling the kernel test bot warnings.
Patches 1-4 focus on moving the common HDCP helpers to comm
Applied. Thanks!
On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote:
>
> amdgpu does not need swiotlb.h, so stop including it.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/a
Applied. Thanks!
On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote:
>
> radeon does not need swiotlb.h, so stop including it.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/gpu/drm/radeon/radeon_ttm.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/ra
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Restored dpu_msm8998_cfg.perf, incorrectly removed previously (Marijn)
- Also dropped reg_dma
This patchset adds initial support for Samsung S6D7AA0-based panels.
Currently, the following panels are supported:
- S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0)
- S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015)
- S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015)
Changed in v2:
- Added
Add bindings for the S6D7AA0 LCD panel controller, including the
S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family
of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels
used in the Samsung Galaxy Tab A 8.0 and 9.7 2015.
Signed-off-by: Artur Weber
---
Changed in v
Initial driver for S6D7AA0-controlled panels. Currently, the following
panels are supported:
- S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0)
- S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015)
- S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015)
It should be possible to extend this driver to
Add myself as maintainer of the Samsung S6D7AA0 panel driver.
Signed-off-by: Artur Weber
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 402e26d0cdbc..7cc2bfa4af6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6663,6 +6663,12 @@ S:
v3 -> v4:
- Drop adding new QoS LUT entries
- Add safe_lut_tbl for both SoCs
Depends on:
-
https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-0-27ce1a5ab...@somainline.org/
v3:
https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v3-0-9837d6b35...@linaro.org
v2 -> v3:
- Don't
Add the DSI host found on SM6350.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docume
SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with
the main exception being that the last one requires an additional
throttle clock.
It is not well understood yet, but failing to toggle it on makes the
display hardware stall and not output any frames.
Document SM6350 and SM6375
Add the DSI host found on SM6375.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docume
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +
1 file changed, 214 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
b/Documentation/devicetree/bindings/dis
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the fact that newer SoCs dropped the .fl (fill level)-based
logic and don't provide real values, resulting in all entr
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
1 file changed, 216 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
b/Documentation/devicetree/bindings/dis
Add support for MDSS on SM6350.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731a
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index ae09c627bc84.
Add support for MDSS on SM6375.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..0564
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/dr
On 19/05/2023 20:03, Dmitry Baryshkov wrote:
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Restored dpu_msm8998_cfg.perf, incorrectly remo
In practice this should never happen. Applied with some minor coding
style fixes.
Alex
On Fri, May 19, 2023 at 11:33 AM Nikita Zhandarovich
wrote:
>
> Function rv740_get_decoded_reference_divider() may return 0 due to
> unpredictable reference divider value calculated in
> radeon_atom_get_clock
Hi,
On Fri, May 19, 2023 at 1:02 AM Cong Yang
wrote:
>
> The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
> it seems that the touch can communicate successfully only when the RST
> signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
> let's set the default h
On Tue, Apr 11, 2023 at 3:46 PM Dmitry Baryshkov
wrote:
>
> On 12/04/2023 01:43, Marijn Suijten wrote:
> > As I get more and more active in the drm/msm space, yet sometimes miss
> > out on patches (where I was involved in previous discussions), add
> > myself as reviewer to make this involvement c
I test this on my 3A5000 + 7A1000 and 3A5000 + 7A2000 desktop,
and this works well, so:
Tested-by: Liu Peibao
Br,
Peibao
On 5/15/23 11:57 PM, Sui Jingfeng wrote:
> Loongson display controller IP has been integrated in both Loongson north
> bridge chipset(ls7a1000/ls7a2000) and Loongson SoCs(ls2
Fannal C3004 is a 480x800 display made by fannal that requires
DCS initialization sequences.
Signed-off-by: Paulo Pavacic
---
v2 changelog:
- renamed from panel-mipi-dsi-bringup
- only one MAINTAINER e-mail
---
MAINTAINERS| 1 +
drivers/gpu/drm/panel/Kconfig
Added fannal to vendor-prefixes and dt bindings for Fannal C3004.
Fannal C3004 is a 480x800 MIPI DSI Panel which requires
DCS initialization sequences with certain delays between certain
commands.
Signed-off-by: Paulo Pavacic
---
v3 changelog:
- renamed yml file
- refactored yml file to des
Fannal C3004 is a 2 lane MIPI DSI 480x800 panel which requires initialization
with DSI DCS commands. After some commands delay is required.
In previous discussions for device tree [1] [2] and device driver [3] were
named mipi-dsi-bringup.
[1]
https://patchwork.ozlabs.org/project/devicetree-bin
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabl
Convert TI LP855X backlight controller bindings from TXT to YAML and,
while we're at it, rework some of the code related to PWM handling.
Also correct existing DTS files to avoid introducing new dtb_check
errors.
Signed-off-by: Artur Weber
Changed in v2:
- Added additionalProperties to ROM patt
Notable changes:
- ROM child nodes use dashes instead of underscores; the driver
reads all child nodes regardless of their names, so this doesn't
break ABI.
- pwm-period argument is deprecated, as it effectively duplicates
the period value provided in pwms. The driver continues to accept
th
Change underscores in ROM node names to dashes, and remove deprecated
pwm-period property.
Signed-off-by: Artur Weber
---
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dt
Also deprecate the pwm-period DT property, as it is now redundant
(pwms property already contains period value).
Signed-off-by: Artur Weber
---
drivers/video/backlight/lp855x_bl.c | 48 -
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/video/ba
On 2023-05-19 19:04:21, Konrad Dybcio wrote:
> v3 -> v4:
> - Drop adding new QoS LUT entries
> - Add safe_lut_tbl for both SoCs
I may not have pinged you correctly with this message [1], but can you
add the DSC configuration for both SoCs?
[1]:
https://lore.kernel.org/linux-arm-msm/u47xthqfjxpbb
On Fri, May 19, 2023 at 07:03:52PM +0200, Artur Weber wrote:
> Add bindings for the S6D7AA0 LCD panel controller, including the
> S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family
> of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels
> used in the Samsung Galaxy
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc Intel GPU test that verifies data coherency
of DRM frame buffer objects using hardware CRC checksums calculated by
display
On some devices the 5V pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. The dp-connector
for such usecases provides dp-pwr supply support. Follow this example
and make hdmi-connector support the hdmi-pwr supply.
Changes since v1:
- Changed the pin de
In preparation to adding support for the hdmi_pwr supply, rename dp_pwr
structure field to the generic connector_pwr.
Reviewed-by: Laurent Pinchart
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/display-connector.c | 18 +-
1 file changed, 9 insertions(+), 9 deletion
Follow the dp-connector example and add hdmi-pwr supply to drive the 5V
pin of the HDMI connector (together with some simple glue logic possibly
attached to the connector).
Reviewed-by: Laurent Pinchart
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/d
On some devices the +5V Power pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. Instead of
declaring this regulator as always-on, make hdmi-connector support the
additional hdmi-pwr supply.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/
On 5/19/23 17:42, Alan Stern wrote:
On Fri, May 19, 2023 at 12:38:15PM +0200, Helge Deller wrote:
Patch looks good and survived the test.
Will you send a proper patch to the fbdev mailing list, so that I can
include it?
Will do.
Great! Thanks!
While you're working on this driver,
I'm no
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticat
DPU5 and newer targets enable this unconditionally. Move it from the
SC7280 mask to the SC7180 one.
Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
Depends on:
https://lor
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2 hosts.
Also, while we
On 5/8/2023 2:56 PM, Marijn Suijten wrote:
On 2023-05-05 14:49:08, Jessica Zhang wrote:
On 5/5/2023 2:23 PM, Jessica Zhang wrote:
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Changes in v2:
- Adjusted pclk_rate math to divide only the hdisplay value
On Fri, 19 May 2023 19:04:26 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
> +
> 1 file changed, 216 insertions(+)
>
My bot found errors running 'make DT_CHECKER_
On 19.05.2023 21:05, Rob Herring wrote:
>
> On Fri, 19 May 2023 19:04:26 +0200, Konrad Dybcio wrote:
>> Document the SM6375 MDSS.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
>> +
>> 1 file changed, 216 insertions(
1 - 100 of 147 matches
Mail list logo
