Re: [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set cache at BO creation

On 2023-04-05 13:26:43, Jordan Justen wrote: > On 2023-04-05 00:45:24, Lionel Landwerlin wrote: > > On 04/04/2023 19:04, Yang, Fei wrote: > > >> Subject: Re: [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set cache > > >> at BO creation > > >> > > >> Just like the protected content uAPI, there is

Re: [PATCH v2 9/9] drm/i915: Use kmap_local_page() in gem/i915_gem_execbuffer.c

Thanks all for your review! On Fri, Mar 31, 2023 at 05:32:17PM +0200, Fabio M. De Francesco wrote: > Date: Fri, 31 Mar 2023 17:32:17 +0200 > From: "Fabio M. De Francesco" > Subject: Re: [PATCH v2 9/9] drm/i915: Use kmap_local_page() in > gem/i915_gem_execbuffer.c > > On venerd? 31 marzo 2023 13

Re: [PATCH 3/5] drm: shmobile: Switch to drm_crtc_init_with_planes()

Hi Laurent, Thanks for your comments! On Wed, Apr 5, 2023 at 5:59 AM Laurent Pinchart wrote: > On Fri, Mar 31, 2023 at 04:48:09PM +0200, Geert Uytterhoeven wrote: > > The SH-Mobile DRM driver uses the legacy drm_crtc_init(), which > > advertizes only the formats in safe_modeset_formats[] (XR24 a

Re: [PATCH 5/5] drm: shmobile: Make DRM_SHMOBILE visible on Renesas SoC platforms

Hi Laurent, On Wed, Apr 5, 2023 at 6:02 AM Laurent Pinchart wrote: > On Fri, Mar 31, 2023 at 04:48:11PM +0200, Geert Uytterhoeven wrote: > > The LCD Controller supported by the drm-shmob driver is not only present > > on SuperH SH-Mobile SoCs, but also on Renesas ARM SH/R-Mobile SoCs. > > Make it

Re: [PATCH 30/68] hwmon: lochnagar: constify pointers to hwmon_channel_info

On Thu, Apr 06, 2023 at 10:30:25PM +0200, Krzysztof Kozlowski wrote: > Statically allocated array of pointed to hwmon_channel_info can be made > const for safety. > > Signed-off-by: Krzysztof Kozlowski > --- Acked-by: Charles Keepax Thanks, Charles

Re: [PATCH 3/5] drm: shmobile: Switch to drm_crtc_init_with_planes()

Hi Geert, On Mon, Apr 10, 2023 at 11:35:56AM +0200, Geert Uytterhoeven wrote: > On Wed, Apr 5, 2023 at 5:59 AM Laurent Pinchart wrote: > > On Fri, Mar 31, 2023 at 04:48:09PM +0200, Geert Uytterhoeven wrote: > > > The SH-Mobile DRM driver uses the legacy drm_crtc_init(), which > > > advertizes only

[git pull] habanalabs for drm-next-6.4

Hi Dave, Daniel. An additional pull request for 6.4. Mostly bug fixes and cleanups. Full details are in the signed tag. Thanks, Oded The following changes since commit 4d877b1a6e855d1c8685fa0e27ad7a521b31b6ca: Merge tag 'drm-intel-next-2023-04-06' of git://anongit.freedesktop.org/drm/drm-i

[PATCH v2] drm/vkms: add module parameter to set background color

After commit 8ba1648567e2 ("drm: vkms: Refactor the plane composer to accept new formats") the composition is no longer performed on top of the primary plane, but instead on top of the CRTC, which means that now we have a background. This opens to the possibility of coloring the background with a

Re: [PATCH] drm/amd/display: remove unused matching_stream_ptrs variable

On 3/25/23 09:45, Tom Rix wrote: clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_enc_cfg.c:625:6: error: variable 'matching_stream_ptrs' set but not used [-Werror,-Wunused-but-set-variable] int matching_stream_ptrs = 0; ^ This variable is not

Re: [PATCH] drm/amd/display: set variable dcn3_14_soc storage-class-specifier to static

On 4/6/23 14:44, Tom Rix wrote: smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.c:100:37: warning: symbol 'dcn3_14_soc' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by: Tom Rix Applied, thanks!

Re: [PATCH] drm/amd/display: set variables aperture_default_system and context0_default_system storage-class-specifier to static

On 4/6/23 15:58, Tom Rix wrote: smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:758:10: warning: symbol 'aperture_default_system' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:759:10: warning: symbol 'context0

Re: [PATCH] drm/amd/display: set variables dml*_funcs storage-class-specifier to static

On 4/8/23 09:43, Tom Rix wrote: smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:44:24: warning: symbol 'dml20_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:51:24: warning: symbol 'dml20v2_funcs'

[pull] drm/msm: drm-msm-next-2023-04-10 for v6.4

Hi Dave, This is the main pull for v6.4, see below for description. A bit big this time because of (1) generated header updates and (2) dpu hw catelog rework which split the increasingly unwieldy big-giant-file-of-tables into per-SoC files. But those are mainly mechanical churn. The following c

Re: [PATCH v7 3/8] drm/i915/pxp: Add MTL helpers to submit Heci-Cmd-Packet to GSC

On 4/6/2023 10:44 AM, Alan Previn wrote: Add helper functions into a new file for heci-packet-submission. The helpers will handle generating the MTL GSC-CS Memory-Header and submission of the Heci-Cmd-Packet instructions to the engine. NOTE1: These common functions for heci-packet-submission

RE: [PATCH 1/2] dt-bindings: drm: bridge: adi,adv7533: Document adi,disable-lanes-override property

Hi All, I would like to drop this patch as[1] and [2] fixes the issue [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/gpu/drm/bridge/adv7511/adv7533.c?h=next-20230406&id=9a0cdcd6649b76f0b7ceec0e55b0a718321e34d3 [2] https://git.kernel.org/pub/scm/linux/ker

Re: [PATCH 1/2] drm: sun4i/dsi: factor out DSI PHY poweron and poweroff

'--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Brandon-Cheo-Fusi/drm-sun4i-dsi-factor-out-DSI-PHY-poweron-and-poweroff/20230410-165257 base: https://git.kernel.org/pub/scm/linux/kernel

RE: [PATCH 2/2] drm/bridge: adv7533: Add option to disable lane switching

Hi All, I would like to drop this patch as [1] and [2] fixes the issue. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/gpu/drm/bridge/adv7511/adv7533.c?h=next-20230406&id=9a0cdcd6649b76f0b7ceec0e55b0a718321e34d3 [2] https://git.kernel.org/pub/scm/linux/k

Re: [PATCH v7 4/8] drm/i915/pxp: Add GSC-CS backend to send GSC fw messages

On 4/6/2023 10:44 AM, Alan Previn wrote: Add GSC engine based method for sending PXP firmware packets to the GSC firmware for MTL (and future) products. Use the newly added helpers to populate the GSC-CS memory header and send the message packet to the FW by dispatching the GSC_HECI_CMD_PKT i

Re: [Intel-gfx] [PATCH 1/8] drm/i915/mtl: Define MOCS and PAT tables for MTL

On Fri, Apr 07, 2023 at 12:12:29AM -0700, fei.y...@intel.com wrote: > From: Fei Yang > > On MTL, GT can no longer allocate on LLC - only the CPU can. > This, along with addition of support for ADM/L4 cache calls a > MOCS/PAT table update. Also defines PTE encode functions for > MTL as it has diff

Re: [PATCH v2] drm/vkms: add module parameter to set background color

I think this should be a KMS property instead of a module parameter. Is there a reason why this patch uses a module parameter? It breaks user-space expectations.

[PATCH] drm/msm/a6xx: initialize GMU mutex earlier

Move GMU mutex initialization earlier to make sure that it is always initialized. a6xx_destroy can be called from ther failure path before GMU initialization. This fixes the following backtrace: [ cut here ] DEBUG_LOCKS_WARN_ON(lock->magic != lock) WARNING: CPU: 0 PID: 58

Re: [PATCH v7 5/8] drm/i915/pxp: Add ARB session creation and cleanup

On 4/6/2023 10:44 AM, Alan Previn wrote: Add MTL's function for ARB session creation using PXP firmware version 4.3 ABI structure format. Also add MTL's function for ARB session invalidation but this reuses PXP firmware version 4.2 ABI structure format. For both cases, in the back-end gsccs

Re: [PATCH v7 6/8] drm/i915/uapi/pxp: Fix UAPI spec comments and add GET_PARAM for PXP

On 4/6/2023 10:44 AM, Alan Previn wrote: 1. UAPI update: Without actually changing backward compatible behavior, update i915's drm-uapi comments that describe the possible error values when creating a context with I915_CONTEXT_PARAM_PROTECTED_CONTENT. Since the first merge of PXP support on AD

Re: [PATCH v2] drm/vkms: add module parameter to set background color

On 04/10, Simon Ser wrote: > I think this should be a KMS property instead of a module parameter. > Is there a reason why this patch uses a module parameter? It breaks > user-space expectations. Hi Simon, a KMS property is what we have on vkms TODO [1] and the module parameter was Maíra's first s

Re: [PATCH 1/2] drm: sun4i/dsi: factor out DSI PHY poweron and poweroff

'--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Brandon-Cheo-Fusi/drm-sun4i-dsi-factor-out-DSI-PHY-poweron-and-poweroff/20230410-165257 base: https://git.kernel.org/pub/scm/linux/kernel

[PATCH] drm/pl111: fix drm and dev leak when irq request failed.

From: Gan Gecen Smatch reports: pl111_amba_probe() warn: missing unwind goto? Code segment for dev_put is: dev_put: drm_dev_put(drm); of_reserved_mem_device_release(dev); When err happened, jumping to dev_put will release drm and dev resources all

Re: [PATCH 2/2] vkms: Add support for multiple connectors

On 04/06, Marius Vlad wrote: > Hi Thomas, > > Thanks for the clarifications! Made a couple of remarks in-line. > > On 4/6/23 14:29, Thomas Zimmermann wrote: > > Hi > > > > Am 06.04.23 um 11:17 schrieb Marius Vlad: > > > Hi Maira, > > > > > > Thanks a lot for taking a look. Yeah, indeed, this cr

[PATCH] drm/msm/a6xx: don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU

If the Adreno SMMU is dma-coherent, allocation will fail unless we disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the coherent SMMUs (like we have on sm8350 platform). Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes") Reported-by: David He

Re: [RFC 1/2] drm: Add fdinfo memory stats

On Sat, Apr 8, 2023 at 5:20 AM Emil Velikov wrote: > > Hey Rob, > > On Thu, 6 Apr 2023 at 22:59, Rob Clark wrote: > > > +- drm-purgeable-memory: [KiB|MiB] > > + > > +The total size of buffers that are purgable. > > s/purgable/purgeable/ > > > > +static void print_size(struct drm_printer *p, cons

Re: [PATCH] drm/msm/adreno: fix sparse warnings in a6xx code

Quoting Dmitry Baryshkov (2023-04-06 18:07:41) > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index 0bc3eb443fec..84d345af126f 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -51,8 +51,8 @@ st

[PATCH 0/2] Add support for dumping error captures via kernel logging

From: John Harrison Sometimes, the only effective way to debug an issue is to dump all the interesting information at the point of failure. So add support for doing that. Signed-off-by: John Harrison John Harrison (2): drm/i915: Dump error capture to kernel log drm/i915/guc: Dump error ca

[PATCH 2/2] drm/i915/guc: Dump error capture to dmesg on CTB error

From: John Harrison In the past, There have been sporadic CTB failures which proved hard to reproduce manually. The most effective solution was to dump the GuC log at the point of failure and let the CI system do the repro. It is preferable not to dump the GuC log via dmesg for all issues as it i

[PATCH 1/2] drm/i915: Dump error capture to kernel log

From: John Harrison This is useful for getting debug information out in certain situations, such as failing kernel selftests and CI runs that don't log error captures. It is especially useful for things like retrieving GuC logs as GuC operation can't be tracked by adding printk or ftrace entries.

Re: [RFC PATCH] drm/msm/a5xx: really check for A510 in a5xx_gpu_init

Quoting Dmitry Baryshkov (2023-04-08 18:13:29) > The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno > 510") added special handling for a510 (this SKU doesn't seem to support > preemption, so the driver should clamp nr_rings to 1). However the > gpu->revn is not yet set (it is

Re: [RFC PATCH] drm/msm/a5xx: really check for A510 in a5xx_gpu_init

On Mon, 10 Apr 2023 at 22:28, Stephen Boyd wrote: > > Quoting Dmitry Baryshkov (2023-04-08 18:13:29) > > The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno > > 510") added special handling for a510 (this SKU doesn't seem to support > > preemption, so the driver should clamp n

Re: [PATCH] drm/msm/a6xx: don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU

Thank you! Tested-by: David Heidelberg On 10/04/2023 20:52, Dmitry Baryshkov wrote: If the Adreno SMMU is dma-coherent, allocation will fail unless we disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the coherent SMMUs (like we have on sm8350 platform). Fixes: 54af0ceb7595

[PATCH v2 1/2] drm: Add fdinfo memory stats

From: Rob Clark Add a helper to dump memory stats to fdinfo. For the things the drm core isn't aware of, use a callback. v2: Fix typos, change size units to match docs, use div_u64 Signed-off-by: Rob Clark Reviewed-by: Emil Velikov --- Documentation/gpu/drm-usage-stats.rst | 21 +++ dri

[PATCH v2 0/2] drm: fdinfo memory stats

From: Rob Clark Similar motivation to other similar recent attempt[1]. But with an attempt to have some shared code for this. As well as documentation. It is probably a bit UMA-centric, I guess devices with VRAM might want some placement stats as well. But this seems like a reasonable start.

[PATCH v2 2/2] drm/msm: Add memory stats to fdinfo

From: Rob Clark Use the new helper to export stats about memory usage. v2: Drop unintended hunk Signed-off-by: Rob Clark Reviewed-by: Emil Velikov --- drivers/gpu/drm/msm/msm_drv.c | 25 - drivers/gpu/drm/msm/msm_gpu.c | 2 -- 2 files changed, 24 insertions(+), 3 del

Re: [PATCH] drm/nouveau/fb: add missing sysmen flush callbacks

On Wed, 5 Apr 2023 at 21:05, Karol Herbst wrote: > > Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/203 > Fixes: 5728d064190e1 ("drm/nouveau/fb: handle sysmem flush page from common > code") > Signed-off-by: Karol Herbst Oops, that must've gotten lost in a rebase somehow. Reviewed-

[PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware

On dGfx, the PL1 power limit being enabled and set to a low value results in a low GPU operating freq. It also negates the freq raise operation which is done before GuC firmware load. As a result GuC firmware load can time out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power

[PATCH 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware

Updates to Patch 2/3 and Patch 3/3 in this version. Ashutosh Dixit (3): drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write drm/i915/guc: Disable PL1 power limit when loading GuC firmware drm/i915/hwmon: Block waiting for GuC reset to complete drivers/gpu/drm/i915/gt/uc/

[PATCH 1/3] drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write

In preparation for follow-on patches, refactor hwm_power_max_write to take hwmon_lock and runtime pm wakeref at start of the function and release them at the end, therefore acquiring these just once each. Signed-off-by: Ashutosh Dixit Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_hwmo

[PATCH 3/3] drm/i915/hwmon: Block waiting for GuC reset to complete

Instead of erroring out when GuC reset is in progress, block waiting for GuC reset to complete which is a more reasonable uapi behavior. v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo) Signed-off-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_hwmon.c | 38 +

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware

On Fri, 07 Apr 2023 04:08:31 -0700, Rodrigo Vivi wrote: > Hi Rodrigo, > On Wed, Apr 05, 2023 at 09:45:21PM -0700, Ashutosh Dixit wrote: > > On dGfx, the PL1 power limit being enabled and set to a low value results > > in a low GPU operating freq. It also negates the freq raise operation which > >

[PATCH] drm/msm/adreno: warn if chip revn is verified before being set

The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno 510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE to prevent such bugs from happening again. A separate helper is necessary so that the warning is displayed really just once instead of being displayed for

[PATCH v2] drm/msm/adreno: fix sparse warnings in a6xx code

Sparse reports plenty of warnings against the a6xx code because of a6xx_gmu::mmio and a6xx_gmu::rscc members. For some reason they were defined as __iomem pointers rather than pointers to __iomem memory. Correct the __iomem attribute. Fixes: 02ef80c54e7c ("drm/msm/a6xx: update pdc/rscc GMU registe

Re: [Intel-gfx] [PATCH 3/3] drm/i915/hwmon: Block waiting for GuC reset to complete

On Fri, 07 Apr 2023 04:04:06 -0700, Rodrigo Vivi wrote: > Hi Rodrigo, > On Wed, Apr 05, 2023 at 09:45:22PM -0700, Ashutosh Dixit wrote: > > Instead of erroring out when GuC reset is in progress, block waiting for > > GuC reset to complete which is a more reasonable uapi behavior. > > > > Signed-o

[PATCH] drm: etnaviv: Replace of_platform.h with explicit includes

Etnaviv doesn't use anything from of_platform.h, but depends on of.h, of_device.h, and platform_device.h which are all implicitly included, but that is going to be removed soon. Signed-off-by: Rob Herring --- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 dele

[GIT PULL] mediatek drm next for 6.4

Hi, Dave & Daniel: This includes: 1. Add support for 10-bit overlays 2. Add MediaTek SoC DRM (vdosys1) support for mt8195 3. Change mmsys compatible for mt8195 mediatek-drm 4. Only trigger DRM HPD events if bridge is attached 5. Change the aux retries times when receiving AUX_DEFER Regards, Chun

Re: [PATCH] drm/msm/adreno: warn if chip revn is verified before being set

Quoting Dmitry Baryshkov (2023-04-10 15:38:36) > The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno > 510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE > to prevent such bugs from happening again. A separate helper is > necessary so that the warning is di

Re: [PATCH v5 1/4] drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xp

On 4/7/2023 5:27 PM, Dmitry Baryshkov wrote: Theoretically, since sm8150 we should be using a single CTL for the split panel case, but since we do not support it for now, fallback to DPU_CTL_SPLIT_DISPLAY. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar

Re: [PATCH v5 2/4] drm/msm/dpu: enable DSPP_2/3 for LM_2/3 on sm8450

On 4/7/2023 5:27 PM, Dmitry Baryshkov wrote: Mark DSPP_2 and DSPP_3 as used for LM_2 and LM_3 Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Signed-off-by: Dmitry Baryshkov --- Reviewed-by: Abhinav Kumar

Re: [PATCH v5 3/4] drm/msm/dpu: enable DSPP and DSC on sc8180x

On 4/7/2023 5:27 PM, Dmitry Baryshkov wrote: Enable DSPP and DSC hardware blocks on sc8180x platform. Signed-off-by: Dmitry Baryshkov --- Reviewed-by: Abhinav Kumar

Re: [PATCH v5 4/4] drm/msm/dpu: use CTL_SC7280_MASK for sm8450's ctl_0

On 4/7/2023 5:27 PM, Dmitry Baryshkov wrote: On sm8450 platform the CTL_0 doesn't differ from the rest of CTL blocks, so switch it to CTL_SC7280_MASK too. Some background: original commit 100d7ef6995d ("drm/msm/dpu: add support for SM8450") had all (relevant at that time) bit spelled individu

linux-next: manual merge of the drm tree with the mm-stable tree

Hi all, Today's linux-next merge of the drm tree got a conflict in: drivers/gpu/drm/ttm/ttm_pool.c between commit: 23baf831a32c ("mm, treewide: redefine MAX_ORDER sanely") from the mm-stable tree and commit: 322458c2bb1a ("drm/ttm: Reduce the number of used allocation orders for TTM pa

Re: [PATCH v10 2/2] drm: add kms driver for loongson display controller

Hi, On 2023/4/4 22:10, Emil Velikov wrote: --- /dev/null +++ b/drivers/gpu/drm/loongson/lsdc_debugfs.c +void lsdc_debugfs_init(struct drm_minor *minor) +{ +#ifdef CONFIG_DEBUG_FS + drm_debugfs_create_files(lsdc_debugfs_list, +ARRAY_SIZE(lsdc_debugfs_list), +

RE: [Intel-gfx] [PATCH 1/8] drm/i915/mtl: Define MOCS and PAT tables for MTL

>Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/mtl: Define MOCS and PAT tables >for MTL > > On Fri, Apr 07, 2023 at 12:12:29AM -0700, > fei.y...@intel.com wrote: >> From: Fei Yang fei.y...@intel.com >> >> On MTL, GT can no longer allocate on L

linux-next: manual merge of the tip tree with the drm tree

Hi all, Today's linux-next merge of the tip tree got a conflict in: drivers/gpu/drm/i915/gt/intel_rc6.c between commit: 3735040978a4 ("drm/i915/mtl: Synchronize i915/BIOS on C6 enabling") from the drm tree and commit: f7faedffa92c ("drm/i915/gt: use __xchg instead of internal helper")

[PATCH 6/9] drm/i915: preparation for using PAT index

From: Fei Yang This patch is a preparation for replacing enum i915_cache_level with PAT index. Caching policy for buffer objects is set through the PAT index in PTE, the old i915_cache_level is not sufficient to represent all caching modes supported by the hardware. Preparing the transition by a

[PATCH 1/9] drm/i915/mtl: Set has_llc=0

From: Fei Yang On MTL, GT is no longer allocated on LLC, set has_llc=0. Signed-off-by: Fei Yang --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index cddb6e197972..025d32c0b161 100644 ---

[PATCH 8/9] drm/i915: making mtl pte encode generic for gen12

From: Fei Yang PTE encode is platform dependent. After replacing cache_level with pat_index, the newly introduced mtl_pte_encode is actually generic for all gen12 platforms, thus rename it to gen12_pte_encode and apply it to all gen12 platforms. Cc: Chris Wilson Cc: Matt Roper Cc: Andi Shyti

[PATCH 4/9] drm/i915/mtl: workaround coherency issue for Media

From: Fei Yang This patch implements Wa_22016122933. In MTL, memory writes initiated by Media tile update the whole cache line even for partial writes. This creates a coherency problem for cacheable memory if both CPU and GPU are writing data to different locations within a single cache line. CT

[PATCH 2/9] drm/i915/mtl: Define MOCS and PAT tables for MTL

From: Fei Yang On MTL, GT can no longer allocate on LLC - only the CPU can. This, along with addition of support for ADM/L4 cache calls a MOCS/PAT table update. BSpec: 44509, 45101, 44235 Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: Aravi

[PATCH 9/9] drm/i915: Allow user to set cache at BO creation

From: Fei Yang To comply with the design that buffer objects shall have immutable cache setting through out its life cycle, {set, get}_caching ioctl's are no longer supported from MTL onward. With that change caching policy can only be set at object creation time. The current code applies a defau

[PATCH 3/9] drm/i915/mtl: Add PTE encode function

From: Fei Yang PTE encode functions are platform dependent. This patch implements PTE functions for MTL, and ensures the correct PTE encode function is used by calling pte_encode function pointer instead of the hardcoded gen8 version of PTE encode. Signed-off-by: Fei Yang --- drivers/gpu/drm/i

[PATCH 0/9] drm/i915/mtl: Define MOCS and PAT tables for MTL

From: Fei Yang The series includes patches needed to enable MTL. Also add new extension for GEM_CREATE uAPI to let user space set cache policy for buffer objects. Fei Yang (9): drm/i915/mtl: Set has_llc=0 drm/i915/mtl: Define MOCS and PAT tables for MTL drm/i915/mtl: Add PTE encode functio

[PATCH 5/9] drm/i915/mtl: end support for set caching ioctl

From: Fei Yang The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU

[PATCH 7/9] drm/i915: use pat_index instead of cache_level

From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent, ha

linux-next: build failure after merge of the driver-core tree

Hi all, After merging the driver-core tree, today's linux-next build (x86_64 allmodconfig) failed like this: In file included from include/linux/linkage.h:7, from include/linux/kernel.h:17, from drivers/accel/qaic/mhi_qaic_ctrl.c:4: drivers/accel/qaic/mhi_qaic_ct

Re: [PATCH v10 2/2] drm: add kms driver for loongson display controller

Hi, On 2023/4/4 22:10, Emil Velikov wrote: +static void lsdc_crtc_reset(struct drm_crtc *crtc) +{ + struct lsdc_display_pipe *dispipe = crtc_to_display_pipe(crtc); + struct drm_device *ddev = crtc->dev; + struct lsdc_device *ldev = to_lsdc(ddev); + struct lsdc_crtc_state

linux-next: build warning after merge of the drm tree

Hi all, After merging the drm tree, today's linux-next build (htmldocs) produced this warning: drivers/gpu/drm/i915/i915_perf.c:5307: warning: Function parameter or member 'i915' not described in 'i915_perf_ioctl_version' Introduced by commit 94d82e95219a ("drm/i915/perf: Pass i915 object to

linux-next: build warning after merge of the drm tree

Hi all, After merging the drm tree, today's linux-next build (htmldocs) produced this warning: drivers/gpu/drm/i915/gt/uc/intel_guc.h:274: warning: Function parameter or member 'dbgfs_node' not described in 'intel_guc' Introduced by commit 70b5ffb393f3 ("drm/i915/gt: Create per-gt debugfs fi

Re: [PATCH v2 1/2] dt-bindings: drm/bridge: Add no-hpd property

On 05/04/2023 16:24, Jayesh Choudhary wrote: > From: Rahul T R > > The mhdp bridge can work without its HPD pin hooked up to the connector, > but the current bridge driver throws an error when hpd line is not > connected to the connector. For such cases, we need an indication for > no-hpd, using

Re: [PATCH v4 2/5] drm/i915/gt: Add intel_context_timeline_is_locked helper

On 3/8/2023 10:41 AM, Andi Shyti wrote: We have: - intel_context_timeline_lock() - intel_context_timeline_unlock() In the next patches we will also need: - intel_context_timeline_is_locked() Add it. Signed-off-by: Andi Shyti Cc: sta...@vger.kernel.org Reviewed-by: Nirmoy Das -

Re: [PATCH v4 3/5] drm/i915: Create the locked version of the request create

On 3/8/2023 10:41 AM, Andi Shyti wrote: Make version of the request creation that doesn't hold any lock. Signed-off-by: Andi Shyti Cc: sta...@vger.kernel.org Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/i915_request.c | 43 +++-- drivers/gpu/drm/i915/i915_r

Re: [PATCH v4 5/5] drm/i915/gt: Make sure that errors are propagated through request chains

On 3/8/2023 10:41 AM, Andi Shyti wrote: Currently, when we perform operations such as clearing or copying large blocks of memory, we generate multiple requests that are executed in a chain. However, if one of these requests fails, we may not realize it unless it happens to be the last request

linux-next: build failure after merge of the drm tree

Hi all, After merging the drm tree, today's linux-next build (powerpc allyesconfig) failed like this: drivers/gpu/drm/ttm/ttm_pool.c:73:29: error: variably modified 'global_write_combined' at file scope 73 | static struct ttm_pool_type global_write_combined[TTM_DIM_ORDER]; |