Hi,
On Tue, 24 Jan 2023 12:45:47 +0200, Dmitry Baryshkov wrote:
> Extract drm_kms_helper_enable_hpd() and drm_kms_helper_disable_hpd(),
> two helpers that enable and disable HPD handling on all device's
> connectors.
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(
Hi,
On Tue, 24 Jan 2023 15:34:42 -0800, Randy Dunlap wrote:
> Correct a spelling mistake (reported by codespell).
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next)
[1/1] drm/bridge: Kconfig: fix a spelling mistake
https://cgit.freedesktop.org/d
Hi Dave and Daniel,
after the PR earlier this week, here's drm-misc-next's final PR
before -rc6. The committed TTM changes all seem to be reverted.
Best regards
Thomas
drm-misc-next-2023-01-26:
drm-misc-next for v6.3:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
* fbdev-helper: Stre
Hi Sanan,
On Thu, Jan 26, 2023 at 12:58 AM Sanan Hasanov
wrote:
> We found a bug using a modified kernel configuration file used by syzbot.
>
> We enhanced the coverage of the configuration file using our tool, klocalizer.
>
> Kernel Branch: 6.2.0-rc5-next-20230124
> Kernel config:
> https://dri
On 26. 01. 23, 1:49, Samuel Thibault wrote:
blit_x and blit_y are uint32_t, so fbcon currently cannot support fonts
larger than 32x32.
The 32x32 case also needs shifting an unsigned int, to properly set bit
31, otherwise we get "UBSAN: shift-out-of-bounds in fbcon_set_font",
as reported on
http
On 26/01/2023 00:54, john.c.harri...@intel.com wrote:
From: John Harrison
When GuC support was added to error capture, the locking around the
request object was broken. Fix it up.
The context based search manages the spinlocking around the search
internally. So it needs to grab the reference
On 26. 01. 23, 8:43, Greg KH wrote:
--- linux-6.0.orig/drivers/video/fbdev/core/fbcon.c
+++ linux-6.0/drivers/video/fbdev/core/fbcon.c
@@ -2489,9 +2489,12 @@ static int fbcon_set_font(struct vc_data
h > FBCON_SWAP(info->var.rotate, info->var.yres, info->var.xres))
retu
The devm_memremap() function doesn't return NULL, it returns error
pointers.
Fixes: 9a10c7e6519b ("drm/simpledrm: Add support for system memory
framebuffers")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/tiny/simpledrm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi,
Thanks for your review
On Wed, Jan 11, 2023 at 03:11:51PM +0100, Thomas Zimmermann wrote:
> Am 07.12.22 um 17:07 schrieb Maxime Ripard:
> > From: Dave Stevenson
> >
> > Copy Intel's "Broadcast RGB" property semantics to add manual override
> > of the HDMI pixel range for monitors that don't
On Mon, Jan 23, 2023 at 04:36:25AM +, Matthew Wilcox wrote:
> On Sat, Jan 21, 2023 at 11:03:05AM -0400, Jason Gunthorpe wrote:
> > I would like to have a session at LSF to talk about Matthew's
> > physr discussion starter:
> >
> > https://lore.kernel.org/linux-mm/ydykweu0htv8m...@casper.infra
This updates the panel timings to achieve a clean 60Hz refresh rate.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/panel/panel-khadas-ts050.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-khadas-ts050.c
b/drivers/gpu/drm/p
[AMD Official Use Only - General]
Hi Thomas,
I have checked what you mentioned.
When loading amdgpu we call drm_client_init() during fbdev setup [1], the
refcnt for drm_kms_helper increases from 3 -> 4.
When we unbind vtcon, refcnt for drm_kms_helper drops 4 -> 3, but the
drm_client_release()
Am 25.01.23 um 16:20 schrieb Somalapuram Amaranath:
To support GTT manager amdgpu_res_first, amdgpu_res_next
from pages to bytes and clean up PAGE_SHIFT operation.
Change the GTT manager init and allocate from pages to bytes
v1 -> v2: reorder patch sequence
v3 -> v4: reorder patch sequence
That
We reference dump buffers both by their handle as well as their
object. The problem is now that when anybody iterates over the DRM
framebuffers and exports the underlying GEM objects through DMA-buf
we run into a circular reference count situation.
The result is that the fbdev handling holds the G
Not used by any driver any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_dumb_buffers.c | 5 +
drivers/gpu/drm/drm_gem.c | 7 ---
drivers/gpu/drm/drm_internal.h | 3 ---
include/drm/drm_drv.h | 19 ---
4 files changed, 1 inserti
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2023-01-26:
A fix and a preliminary patch to fix a memory leak in i915, and a use
after free fix for fbdev deferred io
The following changes since commit 2293a73ad4f3b6c37c06713ff1b67659d92ef43d:
drm/i915: Remove unused
On Wed, 25 Jan 2023, Jani Nikula wrote:
> Here are the drm/i915 patches from [1], re-submitted to CI now that the
> drm/edid dependencies from that series have been merged to
> drm-misc-next, merged to drm-next, and backmerged to drm-misc-next.
>
> Fingers crossed. This has been a long journey.
A
On 25/01/2023 19:04, Matt Roper wrote:
On Wed, Jan 25, 2023 at 10:51:53AM +, Tvrtko Ursulin wrote:
On 24/01/2023 20:54, john.c.harri...@intel.com wrote:
From: John Harrison
Uncore is really part of the GT. So use the GT specific debug/error
That's not really true; uncore should be ou
On 19/01/2023 14:22, Dmitry Baryshkov wrote:
> Add pxo clock to the 8960 bindings (used by the HDMI PLL)
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../bindings/phy/qcom,hdmi-phy-other.yaml | 23 ---
> 1 file changed, 20 insertions(+), 3 deletions(-)
>
Reviewed-by: Krzysz
On Thu, 19 Jan 2023 10:02:19 +0100, Hans Verkuil wrote:
> The bcm2711 has two HDMI outputs, each with their own CEC adapter.
> The CEC adapter name has to be unique, but it is currently
> hardcoded to "vc4" for both outputs. Change this to use the card_name
> from the variant information in order t
[+cc folks from 145eed48de27 and framebuffer folks, regression list]
On Thu, Jan 12, 2023 at 02:08:19PM -0600, Bjorn Helgaas wrote:
> On Wed, Dec 28, 2022 at 06:02:48AM -0600, Bjorn Helgaas wrote:
> > On Wed, Dec 28, 2022 at 08:37:52AM +, bugzilla-dae...@kernel.org wrote:
> > > https://bugzill
Hi,
On Mon, Jan 23, 2023 at 08:41:56PM +0530, Jagan Teki wrote:
> Add devm OF helper to return the next DSI bridge in the chain.
>
> Unlike general bridge return helper devm_drm_of_get_bridge, this
> helper uses the dsi specific panel_or_bridge helper to find the
> next DSI device in the pipeline
On Mon, Jan 09, 2023 at 12:04:39AM +0300, Dmitry Osipenko wrote:
> f a multi-GPU system by using drm_WARN_*() and
> drm_dbg_kms() helpers that print out DRM device name corresponding
> to shmem GEM.
That commit message looks truncated ...
take care,
Gerd
On Mon, Jan 09, 2023 at 12:04:40AM +0300, Dmitry Osipenko wrote:
> its own refcounting of vmaps, use it instead of drm-shmem
> counting. This change prepares drm-shmem for addition of memory shrinker
> support where drm-shmem will use a single dma-buf reservation lock for
> all operations performe
Am 26.01.23 um 10:49 schrieb Slivka, Danijel:
[AMD Official Use Only - General]
Hi Thomas,
I have checked what you mentioned.
When loading amdgpu we call drm_client_init() during fbdev setup [1], the refcnt
for drm_kms_helper increases from 3 -> 4.
When we unbind vtcon, refcnt for drm_kms_hel
On 1/26/23 15:17, Gerd Hoffmann wrote:
> On Mon, Jan 09, 2023 at 12:04:40AM +0300, Dmitry Osipenko wrote:
>> its own refcounting of vmaps, use it instead of drm-shmem
>> counting. This change prepares drm-shmem for addition of memory shrinker
>> support where drm-shmem will use a single dma-buf re
On 1/9/23 00:13, Dmitry Osipenko wrote:
> drm_gem_shmem_mmap() doesn't own reference in error code path, resulting
> in the dma-buf shmem GEM object getting prematurely freed leading to a
> later use-after-free.
>
> Fixes: f49a51bfdc8e ("drm/shme-helpers: Fix dma_buf_mmap forwarding bug")
> Cc: st
Hi
Am 26.01.23 um 10:49 schrieb Slivka, Danijel:
[AMD Official Use Only - General]
Hi Thomas,
I have checked what you mentioned.
When loading amdgpu we call drm_client_init() during fbdev setup [1], the refcnt
for drm_kms_helper increases from 3 -> 4.
When we unbind vtcon, refcnt for drm_kms
Am 26.01.23 um 13:40 schrieb Thomas Zimmermann:
Hi
Am 26.01.23 um 10:49 schrieb Slivka, Danijel:
[AMD Official Use Only - General]
Hi Thomas,
I have checked what you mentioned.
When loading amdgpu we call drm_client_init() during fbdev setup
[1], the refcnt for drm_kms_helper increases from
Am 26.01.23 um 10:28 schrieb Dan Carpenter:
The devm_memremap() function doesn't return NULL, it returns error
pointers.
Fixes: 9a10c7e6519b ("drm/simpledrm: Add support for system memory
framebuffers")
Signed-off-by: Dan Carpenter
Reviewed-by: Thomas Zimmermann
---
drivers/gpu/drm/ti
Hi
Am 26.01.23 um 13:45 schrieb Christian König:
Am 26.01.23 um 13:40 schrieb Thomas Zimmermann:
Hi
Am 26.01.23 um 10:49 schrieb Slivka, Danijel:
[AMD Official Use Only - General]
Hi Thomas,
I have checked what you mentioned.
When loading amdgpu we call drm_client_init() during fbdev setup
On Wed, Jan 25, 2023 at 06:11:35PM +, Tvrtko Ursulin
wrote:
> I don't immediately see how you envisage the half-userspace implementation
> would look like in terms of what functionality/new APIs would be provided by
> the kernel?
Output:
drm.stat (with consumed time(s))
Input:
Hi,
I just want to comment that the code in this patch is fine, but I'm not
going to merge it until the other discussion about using the panel's DT
nodes has been resolved. IMHO, the panel-based solution seems preferable
to the new properties.
Best regards
Thomas
Am 21.01.23 um 16:35 schrie
On Wed, Jan 25, 2023 at 03:41:57PM -0800, Matt Roper wrote:
> Register reset characteristics (i.e., whether the register maintains or
> loses its value on engine reset) is an important factor that determines
> which wa_list we want to add workarounds to. We recently found out that
> the bspec docu
On Wed, Jan 25, 2023 at 03:43:26PM -0800, Matt Roper wrote:
> On Wed, Jan 25, 2023 at 03:41:58PM -0800, Matt Roper wrote:
> > Workaround Wa_18018781329 has applied to several recent Xe_HP-based
> > platforms. However there are some extra gotchas to implementing this
> > properly for MTL that we ne
Hi,
On Wed, Jan 11, 2023 at 05:00:41PM +, Dave Stevenson wrote:
> Hi Thomas
>
> Thanks for the review
>
> On Wed, 11 Jan 2023 at 15:03, Thomas Zimmermann wrote:
> >
> > Hi
> >
> > Am 07.12.22 um 17:07 schrieb Maxime Ripard:
> > > From: Dave Stevenson
> > >
> > > The CSC matrices were store
On Tue, 24 Jan 2023, наб wrote:
> Booted with both, hibernated, resumed; full dmesg below.
Unfortunately, this is probably hitting a regression with drm debug
logging, and we don't get proper debug logging for i915. :(
Please use DRM_USE_DYNAMIC_DEBUG=n with v6.1. I don't know if the proper
fixe
[AMD Official Use Only - General]
Hi Christian,
I have tested the proposed patch, the issue is not reproducible and everything
else seems to work fine.
BR,
Danijel
>-Original Message-
>From: Christian König
>Sent: Thursday, January 26, 2023 1:20 PM
>To: Slivka, Danijel ; Thomas Zimmer
Hi,
Here's a collection of patches that have been in the downstream tree for a
while to add a bunch of new features to the HDMI controller.
Let me know what you think,
Maxime
To: Emma Anholt
To: Maxime Ripard
To: David Airlie
To: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
Cc: linux-ke
From: Dave Stevenson
Copy Intel's "Broadcast RGB" property semantics to add manual override
of the HDMI pixel range for monitors that don't abide by the content
of the AVI Infoframe.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 97 +++
container_of_const() allows to preserve the pointer constness and is
thus more flexible than inline functions.
Let's switch all our instances of container_of() to
container_of_const().
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/tests/vc4_mock.h| 3 ++
drivers/gpu/drm/vc4/test
From: Dave Stevenson
The VC4 HDMI driver has a helper function to figure out whether full
range or limited range RGB is being used called
vc4_hdmi_is_full_range_rgb().
We'll need it to support other colorspaces, so let's rename it to
vc4_hdmi_is_full_range().
Signed-off-by: Dave Stevenson
Revi
On VC4, the TV margins on the HDMI connector are implemented by scaling
the planes.
However, if only the TV margins or the connector are changed by a new
state, the planes ending up on that connector won't be. Thus, they won't
be updated properly and we'll effectively ignore that change until the
From: Dave Stevenson
Even though we report that we support the BT.2020 Colorspace, we were
always using the BT.709 conversion matrices. Let's add the BT.2020 ones.
Signed-off-by: Dave Stevenson
Reviewed-by: Thomas Zimmermann
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 3
From: Dave Stevenson
The CSC matrices were stored as separate matrix for each colorspace, and
if we wanted a limited or full RGB output.
This created some gaps in our support and we would not always pick the
relevant matrix.
Let's rework our data structure to store one per colorspace, and then
From: Dave Stevenson
The CSC matrix to use depends on the output format, its range and the
colorspace.
Since we're going to add more colorspaces, let's move the CSC matrix
retrieval to a function.
Signed-off-by: Dave Stevenson
Reviewed-by: Thomas Zimmermann
Signed-off-by: Maxime Ripard
---
From: Dave Stevenson
YUV444 and YUV422 actually require the same matrix, but programmed
differently.
We've dealt with it in the past by having two matrices, with the one
for YUV444 reordered to accomodate the hardware.
This gets in the way of subsequent reworks so let's define a function
that w
From: Dave Stevenson
Even though we report that we support the BT601 Colorspace, we were
always using the BT.709 conversion matrices. Let's add the BT601 ones.
Signed-off-by: Dave Stevenson
Reviewed-by: Thomas Zimmermann
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 38 ++
Hi Danijel,
can you also double check that GDM/X is still capable of acquiring a
DMA-buf file descriptor for the buffer (e.g. that we have a DMA-buf
handle for it while they are started).
And that handover from fbdev to GDM/X is flicker free?
Thanks,
Christian.
Am 26.01.23 um 14:44 schrieb
[AMD Official Use Only - General]
I would also highly recommend this to be tested with another compositor (Like
Weston/Sway etc)
Regards
Shashank
-Original Message-
From: Christian König
Sent: 26 January 2023 15:12
To: Slivka, Danijel ; Thomas Zimmermann
Cc: Deucher, Alexander ; dri-
Oh, yeah. Very good point as well.
Christian.
Am 26.01.23 um 15:13 schrieb Sharma, Shashank:
[AMD Official Use Only - General]
I would also highly recommend this to be tested with another compositor (Like
Weston/Sway etc)
Regards
Shashank
-Original Message-
From: Christian König
Sen
On Sat, 07 Jan 2023, Sam Ravnborg via B4 Submission Endpoint wrote:
> From: Sam Ravnborg
>
> With all users gone remove the deprecated fb_blank member in
> backlight_properties.
>
> Signed-off-by: Sam Ravnborg
> Cc: Lee Jones
> Cc: Daniel Thompson
> Cc: Jingoo Han
> ---
> drivers/video/bac
Hi
Am 26.01.23 um 11:28 schrieb Christian König:
We reference dump buffers both by their handle as well as their
object. The problem is now that when anybody iterates over the DRM
framebuffers and exports the underlying GEM objects through DMA-buf
we run into a circular reference count situation
Am 26.01.23 um 11:28 schrieb Christian König:
Not used by any driver any more.
Signed-off-by: Christian König
Same comments as for patch 1.
Reviewed-by: Thomas Zimmermann
Tested-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_dumb_buffers.c | 5 +
drivers/gpu/drm/drm_gem.c
On Fri, 20 Jan 2023, Jianhua Lu wrote:
> Add Kinetic KTZ8866 backlight binding documentation.
>
> Signed-off-by: Jianhua Lu
> Reviewed-by: Krzysztof Kozlowski
> ---
> Changes in v2:
> - Remove "items" between "compatible" and "const: kinetic,ktz8866".
> - Change "additionalProperties" to "u
On Fri, 20 Jan 2023, Jianhua Lu wrote:
> Add support for Kinetic KTZ8866 backlight, which is used in
> Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
> downstream implementation [1].
> [1]
> https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/elish-r-oss/drivers/video/backlight/
From: Thierry Reding
On Thu, 19 Jan 2023 15:38:58 +0200, Mikko Perttunen wrote:
> From: Mikko Perttunen
>
> Ensure appropriate configuration is done to make the host1x device
> and context devices DMA coherent by adding the dma-coherent flag.
>
>
Applied, thanks!
[1/4] arm64: tegra: Mark ho
From: Thierry Reding
On Thu, 19 Jan 2023 15:09:18 +0200, Mikko Perttunen wrote:
> From: Mikko Perttunen
>
> In anticipation of removal of the intr API, move host1x_syncpt_wait
> to use DMA fences instead. As of this patch, this means that waits
> have a 30 second maximum timeout because of the
This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.
The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
Patch 0005 - 0006: optional PHY, PMS_P offset
Patch 0007 :
Devices can also be child nodes when we also control that device
through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
Unlike the drm_of_find_panel_or_bridge helper it requires a special
case to lookup a child node of the given parent that isn't either
port or ports.
Lookup for a chil
Add devm OF helper to return the next DSI bridge in the chain.
Unlike general bridge return helper devm_drm_of_get_bridge, this
helper uses the dsi specific panel_or_bridge helper to find the
next DSI device in the pipeline.
Helper lookup a given child DSI node or a DT node's port and
endpoint nu
Exynos DSI already converted into a bridge driver, so bridge
detach will suppose happened during bridge chain removal done
by the bridge core.
Drop the explicit call chain to detach the bridge.
Signed-off-by: Jagan Teki
---
Changes for v12, v11:
- none
Changes for v10:
- new patch
drivers/gpu/
devm_drm_of_dsi_get_bridge is capable of looking up the downstream
DSI bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_dsi_get_bridge.
Signed-off-by: Jagan Teki
---
Changes for v12, v11:
- none
Changes for v10:
- new patch
The same Samsung MIPI DSIM master can also be used in NXP's
i.MX8M Mini/Nano/Plus SoC.
In i.MX8M Mini/Nano/Plus SoC the DSI Phy requires a MIPI DPHY
bit to reset in order to activate the PHY and that can be done
via upstream i.MX8M blk-ctrl driver.
So, mark the phy get as optional.
Reviewed-by:
Look like PLL PMS_P offset value varies between platforms that have
Samsung DSIM IP.
However, there is no clear evidence for it as both Exynos and i.MX
8M Mini Application Processor Reference Manual is still referring
the PMS_P offset as 13.
The offset 13 is not working for i.MX8M Mini SoCs but t
Samsung MIPI DSIM controller is common DSI IP that can be used
in various SoCs like Exynos, i.MX8M Mini/Nano/Plus.
Add hw_type enum via platform_data so that accessing the different
controller data between various platforms becomes easy and meaningful.
Reviewed-by: Marek Vasut
Reviewed-by: Fried
From: Marek Szyprowski
Host transfer() in the DSI master will invoke only when the DSI commands
are sent from DSI devices like DSI Panel or DSI bridges and this host
the transfer wouldn't invoke for I2C-based-DSI bridge drivers.
Handling DSI host initialization in transfer calls misses the contr
Look like an explicit fixing up of mode_flags is required for DSIM IP
present in i.MX8M Mini/Nano SoCs.
At least the LCDIF + DSIM needs active low sync polarities in order
to correlate the correct sync flags of the surrounding components in
the chain to make sure the whole pipeline can work proper
LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting
the i.MX8M Mini/Nano DSI host to add additional Data Enable signal
active low (DE_LOW). This makes the valid data transfer on each
horizontal line.
So, add additional bus flags DE_LOW setting via input_bus_flags
for i.MX8M Mini/Nano
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
proper input format from list of supported output formats.
This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the
DSI host registration, attach and detach operations are quite
different for the component and bridge-based DRM drivers.
Supporting generic bridge driver to use both component and bridge
based DRM drivers can be tricky and would require additional host
related operation hooks.
Add host operation
IRQ handler for te-gpio seems to be common across DSIM host.
However, Exynos is handling this via CRTC drivers but there is no clear
evidence on how the same has been handled in i.MX8MM. Keeping the handler
as-it-is can be a viable option but adding DSIM bridge core in upcoming
patches is not poss
On Thu, Jan 26, 2023 at 08:14:11PM +0530, Jagan Teki wrote:
> Add devm OF helper to return the next DSI bridge in the chain.
>
> Unlike general bridge return helper devm_drm_of_get_bridge, this
> helper uses the dsi specific panel_or_bridge helper to find the
> next DSI device in the pipeline.
>
Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.
In order to access this DSI controller between various platform SoCs,
the ideal way to incorporate this in the drm stack is via the drm bridge
driver.
We already have a consolidated code
Samsung MIPI DSIM bridge can also be found in i.MX8M Mini/Nano SoC.
Add dt-bingings for it.
Reviewed-by: Marek Vasut
Acked-by: Rob Herring
Signed-off-by: Jagan Teki
---
Changes for v12:
- collect RB from Marek
Changes for v11, v10, v9:
- none
Changes for v8:
- add comment to include i.MX8M Nan
Samsung MIPI DSIM master can also be found in i.MX8M Mini/Nano SoC.
Add compatible and associated driver_data for it.
Reviewed-by: Marek Vasut
Reviewed-by: Frieder Schrempf
Acked-by: Robert Foss
Reviewed-by: Laurent Pinchart
Signed-off-by: Marek Szyprowski
Signed-off-by: Jagan Teki
---
Chan
Samsung MIPI DSIM bridge can also be found in i.MX8M Plus SoC.
Add dt-bingings for it.
Reviewed-by: Marek Vasut
Acked-by: Rob Herring
Signed-off-by: Jagan Teki
---
Changes for v12:
- collect RB from Marek
Changes for v11:
- collect ACK from Rob
Changes for v10, v9:
- none
Documentation/devic
From: Marek Vasut
Add extras to support i.MX8M Plus. The main change is the removal of
HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise
the implementation of this IP in i.MX8M Plus is very much compatible
with the i.MX8M Mini/Nano one.
Reviewed-by: Marek Vasut
Reviewed-by: Fr
On Thu, Jan 26, 2023 at 8:17 PM Maxime Ripard wrote:
>
> On Thu, Jan 26, 2023 at 08:14:11PM +0530, Jagan Teki wrote:
> > Add devm OF helper to return the next DSI bridge in the chain.
> >
> > Unlike general bridge return helper devm_drm_of_get_bridge, this
> > helper uses the dsi specific panel_or
On Fri, 20 Jan 2023, Arun R Murthy wrote:
> Enable SDP error detection configuration, this will set CRC16 in
> 128b/132b link layer.
> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
> added to enable/disable SDP CRC applicable for DP2.0 only, but the
> default value of this b
These two will be reused by at least A619_holi in the non-gmu
paths. De-staticize them to make it possible.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git
Port setting min_access_length, ubwc_mode and upper_bit from downstream.
Values were validated using downstream device trees for SM8[123]50 and
left default (as per downstream) elsewhere.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 26 ++
1 fi
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno
These SKUs don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adr
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is
done in a6xx_bus_clear_pending_transactions(), but for the GMU-less
ones we have to do it *somewhere*. Unhalting both side by side sounds
like a good plan and
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adr
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset lin
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 37 ++
One of the protected ranges was too small (compared to the data we
have downstream). Fix it.
Fixes: 408434036958 ("drm/msm/a6xx: update/fix CP_PROTECT initialization")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Currently we only utilize the OPP table connected to the GPU for
getting (available) frequencies. We do however need to scale the
voltage rail(s) accordingly to ensure that we aren't trying to
run the GPU at 1GHz with a VDD_LOW vote, as that would result in
an otherwise inexplainable hang.
Tell th
On GMU-equipped GPUs, the GMU requests appropriate bandwidth votes
for us. This is however not the case for the other GPUs. Add the
dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle
bus voting as part of power level setting.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/g
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Signed-o
On Thu, Jan 26, 2023 at 5:42 PM Maxime Ripard wrote:
>
> Hi,
>
> On Mon, Jan 23, 2023 at 08:41:56PM +0530, Jagan Teki wrote:
> > Add devm OF helper to return the next DSI bridge in the chain.
> >
> > Unlike general bridge return helper devm_drm_of_get_bridge, this
> > helper uses the dsi specific
On 25/01/2023 22:09, Jonathan Cormier wrote:
> Add a i2c example with HDMI connector
Why? It's the same - but more on this below.
>
> Signed-off-by: Jonathan Cormier
You need to test the bindings before sending and fix the errors.
> ---
> .../bindings/display/bridge/ti,tfp410.yaml |
On 25/01/2023 22:09, Jonathan Cormier wrote:
> From: Michael Williamson
>
> The TFP410 driver does not support I2C. As such, the device remains in
> Power Down if the I2C is enabled by the bootstrap pins.
>
> Add basic support for the I2C interface, and provide support to take
> the device out
On Thu, Jan 26, 2023 at 10:46:01AM +, Tvrtko Ursulin wrote:
>
> On 25/01/2023 19:04, Matt Roper wrote:
> > On Wed, Jan 25, 2023 at 10:51:53AM +, Tvrtko Ursulin wrote:
> > >
> > > On 24/01/2023 20:54, john.c.harri...@intel.com wrote:
> > > > From: John Harrison
> > > >
> > > > Uncore is
On 1/26/23 15:44, Jagan Teki wrote:
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
proper input format from list of supported output formats.
This format can be used in pipeline for negotiating bus format betwe
Hi Lee,
On Thu, Jan 26, 2023 at 02:27:26PM +, Lee Jones wrote:
> On Sat, 07 Jan 2023, Sam Ravnborg via B4 Submission Endpoint wrote:
>
> > From: Sam Ravnborg
> >
> > With all users gone remove the deprecated fb_blank member in
> > backlight_properties.
> >
> > Signed-off-by: Sam Ravnborg
>
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