Samsung MIPI DSIM controller is common DSI IP that can be used
in various SoCs like Exynos, i.MX8M Mini/Nano/Plus.
Add hw_type enum via platform_data so that accessing the different
controller data between various platforms becomes easy and meaningful.
Reviewed-by: Frieder Schrempf
Suggested-by:
From: Marek Szyprowski
Host transfer() in the DSI master will invoke only when the DSI commands
are sent from DSI devices like DSI Panel or DSI bridges and this host
the transfer wouldn't invoke for I2C-based-DSI bridge drivers.
Handling DSI host initialization in transfer calls misses the contr
Look like an explicit fixing up of mode_flags is required for DSIM IP
present in i.MX8M Mini/Nano SoCs.
At least the LCDIF + DSIM needs active low sync polarities in order
to correlate the correct sync flags of the surrounding components in
the chain to make sure the whole pipeline can work proper
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
proper input format from list of supported output formats.
This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the
LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting
the i.MX8M Mini/Nano DSI host to add additional Data Enable signal
active low (DE_LOW). This makes the valid data transfer on each
horizontal line.
So, add additional bus flags DE_LOW setting via input_bus_flags
for i.MX8M Mini/Nano
DSI host registration, attach and detach operations are quite
different for the component and bridge-based DRM drivers.
Supporting generic bridge driver to use both component and bridge
based DRM drivers can be tricky and would require additional host
related operation hooks.
Add host operation
Enable and disable of te_gpio's are Exynos platform specific
irq handling, so add the exynos based irq operations and hook
them for exynos plat_data.
Signed-off-by: Jagan Teki
---
Changes for v11:
- none
Changes for v10:
- split from previous series patch
"drm: bridge: Generalize Exynos-DSI drive
Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.
In order to access this DSI controller between various platform SoCs,
the ideal way to incorporate this in the drm stack is via the drm bridge
driver.
We already have a consolidated code
Samsung MIPI DSIM bridge can also be found in i.MX8M Mini/Nano SoC.
Add dt-bingings for it.
Acked-by: Rob Herring
Signed-off-by: Jagan Teki
---
Changes for v11, v10, v9:
- none
Changes for v8:
- add comment to include i.MX8M Nano.
Changes for v7, v6, v5, v4:
- none
Changes for v3:
- collect Rob
Samsung MIPI DSIM master can also be found in i.MX8M Mini/Nano SoC.
Add compatible and associated driver_data for it.
Reviewed-by: Frieder Schrempf
Acked-by: Robert Foss
Reviewed-by: Laurent Pinchart
Signed-off-by: Marek Szyprowski
Signed-off-by: Jagan Teki
---
Changes for v11:
- collect RB
Samsung MIPI DSIM bridge can also be found in i.MX8M Plus SoC.
Add dt-bingings for it.
Acked-by: Rob Herring
Signed-off-by: Jagan Teki
---
Changes for v11:
- collect ACK from Rob
Changes for v10, v9:
- none
Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 +
1 file changed
From: Marek Vasut
Add extras to support i.MX8M Plus. The main change is the removal of
HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise
the implementation of this IP in i.MX8M Plus is very much compatible
with the i.MX8M Mini/Nano one.
Reviewed-by: Frieder Schrempf
Acked-by:
On Mon, Jan 23, 2023 at 10:16:55AM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 20.01.23 um 18:31 schrieb Thierry Reding:
> > From: Thierry Reding
> >
> > Add XB24 and AB24 to the list of supported formats. The format helpers
> > support conversion to these formats and they are documented in the
Hi Thomas!
On 1/23/23 16:13, Thomas Zimmermann wrote:
Driver Changes:
* Remove obsolete drivers for userspace modesetting i810, mga, r128,
savage, sis, tdfx, via
Is the Rage 128 GPU still supported via the generic modesetting driver?
I'm asking because, we're still supporting PowerMacs i
From: Chris Morgan
Add the NewVision NV3051D panel as found on the second revision of the
RG353V. The underlying LCD panel itself is unknown (ST7703 is the
controller IC).
Changes from V1:
- Split redefinition of CMD_UNKNOWN_C6 into separate patch.
Chris Morgan (3):
dt-bindings: panel: Add c
From: Chris Morgan
The Anbernic RG353V-V2 panel is a 5 inch 640x480 MIPI-DSI LCD panel.
It's based on the ST7703 LCD controller just like rocktech,jh057n00900.
It's used in a 2nd revision of the Anbernic RG353V handheld gaming
device. Like the first revision of the RG353V the control chip is know
From: Chris Morgan
The Anbernic RG353V-V2 is a 5 inch panel used in a new revision of the
Anbernic RG353V handheld gaming device. Add support for it.
Unfortunately it appears this controller is not able to support 120hz
or 100hz mode like the first revision panel.
Signed-off-by: Chris Morgan
R
From: Chris Morgan
A later revision of the datasheet for the ST7703 refers to this command
as "SETECO".
Signed-off-by: Chris Morgan
Reviewed-by: Guido Günther
---
drivers/gpu/drm/panel/panel-sitronix-st7703.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
Hi
Am 23.01.23 um 16:23 schrieb John Paul Adrian Glaubitz:
Hi Thomas!
On 1/23/23 16:13, Thomas Zimmermann wrote:
Driver Changes:
* Remove obsolete drivers for userspace modesetting i810, mga, r128,
savage, sis, tdfx, via
Is the Rage 128 GPU still supported via the generic modesetting dr
From: Rob Clark
The existing no-op shims for when PM_DEVFREQ (or an individual governor)
only do half the job. The governor specific config/tuning structs need
to be available to avoid compile errors in drivers using devfreq.
Fixes: 6563f60f14cb ("drm/msm/gpu: Add devfreq tuning debugfs")
Signe
On Mon, Jan 23, 2023 at 4:38 AM Krzysztof Kozlowski wrote:
>
> On 11/01/2023 00:14, Rob Clark wrote:
> > From: Rob Clark
> >
> > Make the handful of tuning knobs available visible via debugfs.
> >
> > v2: select DEVFREQ_GOV_SIMPLE_ONDEMAND because for some reason
> > struct devfreq_simple_ond
Hello Tvrtko.
Interesting work.
On Thu, Jan 12, 2023 at 04:55:57PM +, Tvrtko Ursulin
wrote:
> Because of the heterogenous hardware and driver DRM capabilities, soft limits
> are implemented as a loose co-operative (bi-directional) interface between the
> controller and DRM core.
IIUC, this
From: Chris Morgan
Add the Magnachip D53E6EA8966 panel IC controller for display panels
such as the Samsung AMS495QA01 panel as found on the Anbernic RG503.
This panel uses DSI to receive video signals, but 3-wire SPI to receive
command signals using DBI.
Changes since V11:
- Added a "Co-develo
From: Chris Morgan
Add helper function to find DSI host for devices where DSI panel is not
a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
official Raspberry Pi touchscreen display).
Co-developed-by: Maya Matuszczyk
Signed-off-by: Maya Matuszczyk
Signed-off-by: Chris Morgan
From: Chris Morgan
Support Magnachip D53E6EA8966 based panels such as the Samsung
AMS495QA01 panel as found on the Anbernic RG503. Note this driver
supports only the AMS495QA01 today which receives video signals via DSI,
however it receives commands via 3-wire SPI using DBI.
Co-developed-by: May
From: Chris Morgan
Add documentation for Samsung AMS495QA01 panel (with Magnachip
D53E6EA8966 controller IC).
Co-developed-by: Maya Matuszczyk
Signed-off-by: Maya Matuszczyk
Signed-off-by: Chris Morgan
Reviewed-by: Rob Herring
---
.../display/panel/samsung,ams495qa01.yaml | 57 +
From: Chris Morgan
Add Samsung AMS495QA01 panel to RG503.
Co-developed-by: Maya Matuszczyk
Signed-off-by: Maya Matuszczyk
Signed-off-by: Chris Morgan
---
.../dts/rockchip/rk3566-anbernic-rg503.dts| 55 +++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts
From: Rob Clark
Once we create the handle, the handle owns the reference. Currently
nothing was doing anything with the shmem ptr after the handle was
created, but let's change drm_gem_shmem_create_with_handle() to not
return the pointer, so-as to not encourage problematic use of this
function i
Hi Marek,
On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki
> >> wrote:
> >>
> >>> There are
Hi Thomas!
On 1/23/23 16:35, Thomas Zimmermann wrote:
The only thing that is not supported any longer is hardware-accelerated 3d
rendering.
However, this has not worked anyway, as Mesa has dropped support for those
chips a long
time ago.
Correct me if I'm wrong, but I thought that's what Mes
CC'ing the linux-media mailing list.
On Mon, Jan 23, 2023 at 02:10:58PM +, Simon Ser wrote:
> Hi all,
>
> In the last few days I've been working on a small new project, pixfmtdb [1].
> It's a Web database of pixel format guides, it can be useful to understand
> how pixels are laid out in memo
On 1/23/23 08:23, Liu Ying wrote:
There is one LCDIF embedded in i.MX93 SoC to connect with
MIPI DSI controller through LCDIF cross line pattern(controlled
by mediamix blk-ctrl) or connect with LVDS display bridge(LDB)
directly or connect with a parallel display through parallel
display format(al
On 1/23/23 08:23, Liu Ying wrote:
The LCDIF embedded in i.MX93 SoC is essentially the same to those
in i.MX8mp SoC. However, i.MX93 LCDIF may connect with MIPI DSI
controller through LCDIF cross line pattern(controlled by mediamix
blk-ctrl) or connect with LVDS display bridge(LDB) directly or a
On Tue, Jan 17, 2023 at 09:04:39AM +0100, Johan Hovold wrote:
> On Mon, Jan 16, 2023 at 08:51:22PM -0600, Bjorn Andersson wrote:
> > On Fri, Jan 13, 2023 at 10:57:18AM +0200, Dmitry Baryshkov wrote:
> > > On 13/01/2023 06:23, Dmitry Baryshkov wrote:
> > > > On 13/01/2023 06:10, Bjorn Andersson wrot
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother intro
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother intro
The RCAR DSI driver uses reset controller, so we should select it in the
Kconfig.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
On Sun, 22 Jan 2023 at 01:56:07 +0530, Siddh Raman Pant wrote:
> Hello,
>
> I want to participate in X.Org EVoC as I am looking to learn and
> contribute more to the Linux kernel.
>
> I have made a draft proposal at
> https://gitlab.freedesktop.org/-/snippets/7366.
Seems like my gitlab.fd.o acc
From: Koji Matsuoka
According to hardware manual, LVDCR0 register must be cleared bit by bit
when disabling LVDS.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother intro
On H3 ES1.x two bits in DPLLCR are used to select the DU input dot clock
source. These are bits 20 and 21 for DU2, and bits 22 and 23 for DU1. On
non-ES1.x, only the higher bits are used (bits 21 and 23), and the lower
bits are reserved and should be set to 0.
The current code always sets the lowe
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 873ff2cf72c9..b7a9ec550ba1 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -296,7 +296,7 @@ static const struct aspeed_spi_data ast2400_spi_
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Each flash that is connected in stacked mode should have a separate
parameter structure. So, the flash parameter member(*params) of the spi_nor
structure is changed to an array (*params[2]). The array is used to store
the parameters of each flash c
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother intro
rcar_du_crtc.c does a soc_device_match() in
rcar_du_crtc_set_display_timing() to find out if the SoC is H3 ES1.x, and
if so, apply a workaround.
We will need another H3 ES1.x check in the following patch, so rather than
adding more soc_device_match() calls, let's add a rcar_du_device_info
entry fo
From: Tomi Valkeinen
Hi,
Diff to v2:
- Depend on PM in Kconfig to ensure runtime PM works
- Fix access to DEFR7 in "drm: rcar-du: Stop accessing non-existant
registers on gen4"
- Use pm_runtime_put_sync() instead of pm_runtime_put()
- Add missing line feed
- Fix lvsd typo in commit message
T
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother intro
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi core and spi controller drivers would require
the chip_select & cs_gpiod members of struct spi_device to be an array.
But changing the type of these members to array would break the spi driver
functionality. To make the t
On Sunday, 22 January 2023 20:49:22 CET Christophe JAILLET wrote:
> Le 22/01/2023 à 19:16, Diederik de Haas a écrit :
> > Signed-off-by: Diederik de Haas
> > ---
> >
> > drivers/char/agp/amd64-agp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/char/ag
Add simple runtime PM suspend and resume functionality.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
drivers/gpu/drm/rcar-du/rcar_lvds.c | 43 +
2 files changed, 38 insertions(+), 6 deletions(-)
diff --g
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF7Rm, DEF8Rm, ESCRn, OTARn.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 24 ++
On 1/19/23 19:53, Amit Kumar Mahapatra wrote:
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother intro
Reset LVDS using the reset control as CPG reset/release is required in
the hardware manual sequence.
Based on a BSP patch from Koji Matsuoka .
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
drivers/gpu/drm/rcar-du/rcar_lvds.c | 20 ++
Hi John,
On Mon, Jan 23, 2023 at 12:16:45PM +, John Keeping wrote:
> On Sun, Jan 22, 2023 at 05:01:27PM +0200, Laurent Pinchart wrote:
> > On Sat, Jan 21, 2023 at 05:58:11PM +, John Keeping wrote:
> > > On Sat, Jan 21, 2023 at 09:57:18AM +0100, Sam Ravnborg wrote:
> > > > On Fri, Jan 20, 2
Hi Thomas,
Am 23.01.23 um 15:59 schrieb Thomas Hellström:
On 1/4/23 11:31, Christian König wrote:
Am 30.12.22 um 12:11 schrieb Thomas Hellström:
Hi, Christian, others.
I'm starting to take a look at the TTM shrinker again. We'll
probably be
needing it at least for supporting integrated hard
On 23/01/2023 15:48, Rob Clark wrote:
> From: Rob Clark
>
> Once we create the handle, the handle owns the reference. Currently
> nothing was doing anything with the shmem ptr after the handle was
> created, but let's change drm_gem_shmem_create_with_handle() to not
> return the pointer, so-as t
Hi Naresh,
On Mon, Jan 23, 2023 at 07:28:10PM +0530, Naresh Kamboju wrote:
> FYI,
> [ please provide comments, feedback and improvements on build/ ltp smoke
> tests ]
>
> LKFT test farm have fetched your patch series [1]
> [PATCH v2 00/14] Remove clang's -Qunused-arguments from KBUILD_CPPFLAGS
>
Hi, Christian,
On 1/23/23 17:07, Christian König wrote:
Hi Thomas,
Am 23.01.23 um 15:59 schrieb Thomas Hellström:
On 1/4/23 11:31, Christian König wrote:
Am 30.12.22 um 12:11 schrieb Thomas Hellström:
Hi, Christian, others.
I'm starting to take a look at the TTM shrinker again. We'll
prob
> -Original Message-
> From: Jani Nikula
> Sent: Monday, January 23, 2023 3:01 AM
> To: De Marchi, Lucas ; Srivatsa, Anusha
>
> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
>
> On Sat,
Am 23.01.23 um 14:55 schrieb Laurent Pinchart:
Hi Christian,
CC'ing James as I think this is related to his work on the unix device
memory allocator ([1]).
[1]
https://lore.kernel.org/dri-devel/8b555674-1c5b-c791-4547-2ea7c16ae...@nvidia.com/
On Mon, Jan 23, 2023 at 01:37:54PM +0100, Christia
The initial datasheet claimed that chouzhong designed this 10"
DSI panel on top of JD9365DA IC, but later Radxa mentioned that
chouzhong is the manufacturer.
So the actual design of the panel, gsensor, and customized FPC
is done by Radxa. The panel model named is Radxa Display 10HD
with AD001 is t
This reverts commit 90f86d0c617d9461cb00f4d8e861eda28011d46e.
[why]
The initial datasheet claimed that chouzhong designed the 10" DSI
panel on top of JD9365DA IC, but later Radxa mentioned that chouzhong
is the manufacturer. This concludes that the actual design of the
panel, gsensor, and customiz
Radxa Display 8HD is a family of DSI panels from Radxa that
uses jd9365da-h3 IC.
Add compatible string for it.
Signed-off-by: Jagan Teki
---
.../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/di
Radxa Display 8HD is a family of DSI panels from Radxa that
uses jd9365da-h3 IC.
Add support for it.
Co-developed-by: Stephen Chen
Signed-off-by: Stephen Chen
Signed-off-by: Jagan Teki
---
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 200 ++
1 file changed, 200 insertions(+
On Mon, Jan 23, 2023 at 08:15:16AM -0800, Anusha Srivatsa wrote:
-Original Message-
From: Jani Nikula
Sent: Monday, January 23, 2023 3:01 AM
To: De Marchi, Lucas ; Srivatsa, Anusha
Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2
+ some more people based on e1a7ab4fca0c
On 19/01/2023 17:32, Rob Clark wrote:
From: Rob Clark
Adding the vm to the vm_xa table makes it visible to userspace, which
could try to race with us to close the vm. So we need to take our extra
reference before putting it in the table.
Signed-off-
Hi Christian,
On Mon, Jan 23, 2023 at 05:29:18PM +0100, Christian König wrote:
> Am 23.01.23 um 14:55 schrieb Laurent Pinchart:
> > Hi Christian,
> >
> > CC'ing James as I think this is related to his work on the unix device
> > memory allocator ([1]).
> >
> > [1]
> > https://lore.kernel.org/dri-
On 1/20/23 18:15, Lyude Paul wrote:
> For the whole series:
>
> Reviewed-by: Lyude Paul
Thanks, series is merged to amd-staging-drm-next.
Harry
>
> So glad to have this fixed finally ♥
>
> On Thu, 2023-01-19 at 18:51 -0500, Harry Wentland wrote:
>> MST has been broken on amdgpu after a refac
On 1/22/23 14:12, Didier 'OdyX' Raboud wrote:
> For the whole series, as rebased on v6.1.7. Tested on this Thinkpad X13 AMD
> Gen2:
>
> Tested-By: Didier Raboud
Thanks.
Harry
>
> Le vendredi, 20 janvier 2023, 00.51:53 h CET Harry Wentland a écrit :
>> MST has been broken on amdgpu after a
On Mon, Jan 23, 2023 at 05:01:45PM +0100, Johan Hovold wrote:
> On Tue, Jan 17, 2023 at 09:04:39AM +0100, Johan Hovold wrote:
> > On Mon, Jan 16, 2023 at 08:51:22PM -0600, Bjorn Andersson wrote:
> > > On Fri, Jan 13, 2023 at 10:57:18AM +0200, Dmitry Baryshkov wrote:
> > > > On 13/01/2023 06:23, Dmi
It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged
due to some reasons like:
1) It increases the code size since the array is declared
in e
On 23/01/2023 17:40, Jagan Teki wrote:
> This reverts commit 90f86d0c617d9461cb00f4d8e861eda28011d46e.
>
> [why]
> The initial datasheet claimed that chouzhong designed the 10" DSI
> panel on top of JD9365DA IC, but later Radxa mentioned that chouzhong
> is the manufacturer. This concludes that th
On 23/01/2023 17:40, Jagan Teki wrote:
> Radxa Display 8HD is a family of DSI panels from Radxa that
> uses jd9365da-h3 IC.
>
> Add compatible string for it.
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 23/01/2023 17:40, Jagan Teki wrote:
> The initial datasheet claimed that chouzhong designed this 10"
> DSI panel on top of JD9365DA IC, but later Radxa mentioned that
> chouzhong is the manufacturer.
>
> So the actual design of the panel, gsensor, and customized FPC
> is done by Radxa. The pane
On Mon, 23 Jan 2023 at 22:52, Krzysztof Kozlowski
wrote:
>
> On 23/01/2023 17:40, Jagan Teki wrote:
> > The initial datasheet claimed that chouzhong designed this 10"
> > DSI panel on top of JD9365DA IC, but later Radxa mentioned that
> > chouzhong is the manufacturer.
> >
> > So the actual design
> -Original Message-
> From: De Marchi, Lucas
> Sent: Monday, January 23, 2023 9:16 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Jani Nikula
> ; De Marchi, Lucas
> Subject: [PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()
>
> It's a
On 20/01/2023 23:28, john.c.harri...@intel.com wrote:
From: John Harrison
When GuC support was added to error capture, the locking around the
request object was broken. Fix it up.
The context based search manages the spinlocking around the search
internally. So it needs to grab the reference
On Sun, Jan 22, 2023 at 05:25:38PM +, Rayyan Ansari wrote:
> On 22/01/2023 15:36, Rob Herring wrote:
> > On Sat, Jan 21, 2023 at 9:36 AM Rayyan Ansari wrote:
> > >
> >
> > Why do you need this change?
> >
> > The 'simple-framebuffer' contains data on how the bootloader
> > configured the di
On 23/01/2023 18:45, Jagan Teki wrote:
> On Mon, 23 Jan 2023 at 22:52, Krzysztof Kozlowski
> wrote:
>>
>> On 23/01/2023 17:40, Jagan Teki wrote:
>>> The initial datasheet claimed that chouzhong designed this 10"
>>> DSI panel on top of JD9365DA IC, but later Radxa mentioned that
>>> chouzhong is t
On Mon, Jan 23, 2023 at 12:15:04PM +0200, Jani Nikula wrote:
> On Fri, 20 Jan 2023, Ville Syrjälä wrote:
> > On Thu, Jan 19, 2023 at 06:18:58PM +0200, Jani Nikula wrote:
> >> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> >> b/drivers/gpu/drm/i915/display/intel_lvds.c
> >> index aecec99
This patch add DSC related supporting functions into to both dp controller and
dpu enccoder
Kuogee Hsieh (14):
drm/msm/dp: add dpcd read of both dsc and fec capability
drm/msm/dp: add dsc factor into calculation of supported bpp
drm/msm/dp: add configure mainlink_levels base on lane number
FEC is pre-requirement of DSC. Therefore FEC has to be enabled
before DSC enabled. This patch add functions to read sink's DSC
and FEC related DPCD and decode them and set enable flags
accordingly.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.c | 91 +++
When FEC enabled, it introduces 2.5% overhead into link capacity.
This factor have to be considered into calculation supported bpp.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.c | 45 +--
1 file changed, 38 insertions(+), 7 deletions(-)
di
Mainlink_levels determined when two actions to take place by hardware,
a new BS sequence due to start of video and a static HW MVID is sent
to panel. This patch add function to configure mainlink level properly
base on lane number.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_catalo
At display port, the pixel data is packed into TU (transfer units)
which is used to carry main video stream data during its horizontal active
period. TUs are mapping into the main-Link to facilitate the support of
various lane counts regardless of the pixel bit depth and colorimetry
format. Stuffin
Add display compression related struct to support variant compression
mechanism. However, DSC is the only one supported at this moment.
VDC may be added later.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.h | 42 ++
drivers/gpu/drm/msm/msm_drv.h | 89 ++
Add DSC related supporting functions to calculate DSC related parameters.
In addition, DSC hardware encoder customized configuration parameters are
also included. Algorithms used to perform calculation are derived from
system engineer spreadsheet.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/
MSA MISC0 bit 1 to 7 contains Colorimetry Indicator Field. At current
implementation, Colorimetry Indicator Field of MISC0 is not configured
correctly. This patch add support of RGB formats Colorimetry.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 5 +++--
drivers/gpu/drm
This patch provides DSC required functions at DP controller to
complete DSC feature. those functions include enable fec, configure
dsc, configure dto, transmit pps and finally flush hardware registers.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 139 -
drivers/g
Current implementation timing engine programming does not consider
compression factors. This patch add consideration of DSC factors
while programming timing engine.
Signed-off-by: Kuogee Hsieh
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ca
DSC V1.2 encoder engine is newly added hardware module. This patch
add support functions to configure and enable DSC V1.2 encoder engine.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 2 +-
drivers/gpu/d
struct msm_compression_info is used to support several different
compression mechanisms. It also contains customized info required
to configure DSC encoder engine. This patch also make changes DSI
module to have DSI exports struct msm_compreion_info to dpu encoder
instead of struct drm_dsc_config.
This patch add DSC block and sub block to support new DSC v1.2 hardware
encoder. Also sc7280 DSC related hardware information are added to allow
sc7280 DSC feature be enabled at sc7280 platform.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 50 +
A new flushing mechanism is introduced to decouple peripheral metadata
flushing from timing engine related flush. This patch add peripheral
flushing functions.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 24 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_
Since display Port is an external peripheral, runtime compression
detection is added to handle plug in and unplugged events. Currently
only DSC compression supported. Once DSC compression detected, topology
is static added and used to allocate system resources to accommodate
DSC requirement. DSC re
Radxa Display 10HD is a family of DSI panels from Radxa that
uses jd9365da-h3 IC.
Add compatible string for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
.../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Docume
Radxa Display 10HD is a family of DSI panels from Radxa that
uses jd9365da-h3 IC.
Add panel support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/dri
Radxa Display 8HD is a family of DSI panels from Radxa that
uses jd9365da-h3 IC.
Add compatible string for it.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Krzysztof ACK
.../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml| 1 +
1 file cha
Radxa Display 8HD is a family of DSI panels from Radxa that
uses jd9365da-h3 IC.
Add support for it.
Co-developed-by: Stephen Chen
Signed-off-by: Stephen Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 200 ++
1 f
DisplayPort is a name, and I think you should spell it as such in both
the cover letter title and individual patch descriptions (capital D and
P, no space in between).
On 2023-01-23 10:24:20, Kuogee Hsieh wrote:
> This patch add DSC related supporting functions into to both dp controller
> and dp
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