Hi
Am 18.01.23 um 20:21 schrieb Rodrigo Vivi:
On Thu, Jan 12, 2023 at 09:11:55PM +0100, Thomas Zimmermann wrote:
Set the framebuffer info for drivers that support VGA switcheroo. Only
affects the amdgpu and nouveau drivers, which use VGA switcheroo and
generic fbdev emulation. For other drivers
* Laurent Pinchart [230114 15:37]:
> Tony, could you take this patch in your tree for v6.3 ? The two patches
> that it depends on have both been merged in v6.2.
OK applying into omap-for-v6.3/dt.
Thanks,
Tony
Hi,
On Wed, Jan 18, 2023 at 05:31:32PM -0600, Chris Morgan wrote:
> From: Chris Morgan
>
> Add helper function to find DSI host for devices where DSI panel is not
> a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
> official Raspberry Pi touchscreen display).
>
> Signed-off-by:
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Thanks!
Maxime
drm-misc-fixes-2023-01-19:
A fix for vc4 to address a memory leak when allocating a buffer, a
Kconfig fix for panfrost and two fixes for i915 and fb-helper to
address some bugs with vga-switcheroo.
The following changes since com
On Wed, Jan 18, 2023 at 02:39:15PM +0100, Krzysztof Kozlowski wrote:
> On 18/01/2023 14:10, Jianhua Lu wrote:
> > Add support for Kinetic KTZ8866 backlight, which is used in
> > Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
> > downstream implementation [1].
> > [1]
> > https://gith
Add support for Kinetic KTZ8866 backlight, which is used in
Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
downstream implementation [1].
[1]
https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/elish-r-oss/drivers/video/backlight/ktz8866.c
Signed-off-by: Jianhua Lu
---
Changes
On Wed, Jan 18, 2023 at 02:40:00PM +0100, Krzysztof Kozlowski wrote:
> On 18/01/2023 14:10, Jianhua Lu wrote:
> > Add Kinetic KTZ8866 backlight binding documentation.
> >
> > Signed-off-by: Jianhua Lu
> > ---
> > Changes in v2:
> > - Remove "items" between "compatible" and "const: kinetic,ktz88
On Wed, Jan 18, 2023 at 12:08:01PM +, Daniel Thompson wrote:
> On Tue, Jan 17, 2023 at 11:44:08PM +0800, Jianhua Lu wrote:
> > Add support for Kinetic KTZ8866 backlight, which is used in
> > Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
> > downstream implementation [1].
> > [1]
Add Kinetic KTZ8866 backlight binding documentation.
Signed-off-by: Jianhua Lu
---
Changes in v2:
- Remove "items" between "compatible" and "const: kinetic,ktz8866"
- Change "additionalProperties" to "unevaluatedProperties"
Changes in v3:
- Add Krzysztof's R-b
Changes in v4:
- Drop Krzy
On Wed, 18 Jan 2023 at 21:30, Mark Yacoub wrote:
>
> From: Sean Paul
>
> This patch adds the bindings for the MSM DisplayPort HDCP registers
> which are required to write the HDCP key into the display controller as
> well as the registers to enable HDCP authentication/key
> exchange/encryption.
>
On Wed, 18 Jan 2023 at 21:30, Mark Yacoub wrote:
>
> From: Sean Paul
>
> This patch adds the register ranges required for HDCP key injection and
> HDCP TrustZone interaction as described in the dt-bindings for the
> sc7180 dp controller. Now that these are supported, change the
> compatible strin
Hi Dave and Daniel,
this is the weekly PR for drm-misc-next. This big change is that the
old drivers for userspace modesetting have been removed. Nouveau has
also lost support for these old ioctls and is therefore now requiring
libdrm 2.4.33.
Best regards
Thomas
drm-misc-next-2023-01-19:
drm-mis
The bcm2711 has two HDMI outputs, each with their own CEC adapter.
The CEC adapter name has to be unique, but it is currently
hardcoded to "vc4" for both outputs. Change this to use the card_name
from the variant information in order to make the adapter name unique.
Signed-off-by: Hans Verkuil
--
Thomas wrote:
> On Tue, Jan 17 2023 at 10:18, Boqun Feng wrote:
> > On Mon, Jan 16, 2023 at 10:00:52AM -0800, Linus Torvalds wrote:
> > > I also recall this giving a fair amount of false positives, are they all
> > > fixed?
> >
> > From the following part in the cover letter, I guess the answer is
On Tue, Jan 10, 2023 at 09:34:00PM +0200, Oded Gabbay wrote:
> On Mon, Jan 9, 2023 at 2:23 PM Jacek Lawrynowicz
> wrote:
> >
> > Hi,
> >
> > This patchset contains a new Linux* Kernel Driver for Intel® VPUs.
> >
> > VPU stands for Versatile Processing Unit and it is an AI inference
> > accelerato
Hi Tomi,
On Thu, Jan 19, 2023 at 11:17:58AM +0200, Tomi Valkeinen wrote:
> On 18/01/2023 23:38, Laurent Pinchart wrote:
> > On Tue, Jan 17, 2023 at 03:51:53PM +0200, Tomi Valkeinen wrote:
> >> On H3 ES1 two bits in DPLLCR are used to select the DU input dot clock
> >
> > s/ES1/ES1.x/
> >
> > Sam
Hi Dan,
On 1/3/23 09:07, Dan Carpenter wrote:
> Hi Michael,
>
> url:
> https://github.com/intel-lab-lkp/linux/commits/Michael-Riesch/drm-rockchip-vop2-add-support-for-the-rgb-output-block/20221130-220346
> base: b7b275e60bcd5f89771e865a8239325f86d9927d
> patch link:
> https://lore.kerne
On Wed, 18 Jan 2023, Ville Syrjälä wrote:
> On Wed, Jan 04, 2023 at 12:05:25PM +0200, Jani Nikula wrote:
>> Add a helper for skipping the HDMI VSDB audio latency fields.
>>
>> There's a functional change for HDMI VSDB blocks that do not respect the
>> spec: "I_Latency_Fields_Present shall be zero
Hi,
Just a reflexion I have after an intensive (and intense) debugging
session.
I had the following code:
int my_dma_resv_lock(struct dma_buf *dmabuf)
{
struct ww_acquire_ctx ctx;
int ret;
ww_acquire_init(&ctx, &reservation_ww_class);
ret = dma_resv_lock_interr
On Thu, Jan 12, 2023 at 05:45:42PM +0100, Greg KH wrote:
> On Thu, Jan 12, 2023 at 04:26:45PM +0100, Daniel Vetter wrote:
> > On Thu, 12 Jan 2023 at 13:47, Greg KH wrote:
> > > On Wed, Jan 04, 2023 at 07:56:33PM +0200, Dragos-Marian Panait wrote:
> > > > From: Jiasheng Jiang
> > > >
> > > > [ Ups
On 18/01/2023 20:30, Mark Yacoub wrote:
> From: Sean Paul
>
> This patch adds the register ranges required for HDCP key injection and
Do not use "This commit/patch".
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
This applies to all your patches
On 2023-01-19 11:24, Paul Cercueil wrote:
Hi,
Just a reflexion I have after an intensive (and intense) debugging
session.
I had the following code:
int my_dma_resv_lock(struct dma_buf *dmabuf)
{
struct ww_acquire_ctx ctx;
int ret;
ww_acquire_init(&ctx, &reservation_
On 18/01/2023 20:30, Mark Yacoub wrote:
> From: Sean Paul
>
> This patch moves the hdcp atomic check from i915 to drm_hdcp so other
> drivers can use it. No functional changes, just cleaned up some of the
> code when moving it over.
>
> Acked-by: Jani Nikula
> Acked-by: Jani Nikula
> Reviewed-
(cc: devicet...@vger.kernel.org, as...@lists.linux.dev)
Hi,
thanks for the patch. I already wondered if the DPI value should be
configurable in some way.
Am 18.01.23 um 19:48 schrieb Rayyan Ansari:
Hello,
The following draft patch adds support for configuring the
height-mm and width-mm DRM p
Hi Tomi,
On Thu, Jan 19, 2023 at 10:49:28AM +0200, Tomi Valkeinen wrote:
> On 18/01/2023 23:12, Laurent Pinchart wrote:
> > On Tue, Jan 17, 2023 at 03:51:51PM +0200, Tomi Valkeinen wrote:
> >> From: Koji Matsuoka
> >>
> >> According to H/W manual, LVDCR0 register must be cleared bit by bit when
>
On Mon, Jan 09, 2023 at 08:26:44PM +0100, Neil Armstrong wrote:
> On 09/01/2023 19:32, Sam Ravnborg wrote:
> > Hi Neil,
> >
> > On Mon, Jan 09, 2023 at 09:49:30AM +0100, Neil Armstrong wrote:
> > > Add support for the 1080x2400 Visionox VTDR6130 AMOLED DSI panel
> > > found on the Qualcomm SM8550
On Tue, Jan 17, 2023 at 10:27:16AM +0100, Jacek Lawrynowicz wrote:
> Hi,
>
> This patchset contains a new Linux* Kernel Driver for Intel® VPUs.
>
> VPU stands for Versatile Processing Unit and it is an AI inference accelerator
> integrated with Intel non-server CPUs starting from 14th generation.
On Thu, Jan 19, 2023 at 11:37:39AM +0100, Maarten Lankhorst wrote:
>
> On 2023-01-19 11:24, Paul Cercueil wrote:
> > Hi,
> >
> > Just a reflexion I have after an intensive (and intense) debugging
> > session.
> >
> > I had the following code:
> >
> >
> > int my_dma_resv_lock(struct dma_buf *dm
Am 19.01.23 um 06:23 schrieb Matthew Brost:
[SNIP]
Userspace (generally Vulkan, some compute) has interfaces that pretty
much dictate a lot of how VMA tracking works, esp around lifetimes,
sparse mappings and splitting/merging underlying page tables, I'd
really like this to be more consistent ac
On 18/01/2023 21:30, Mark Yacoub wrote:
From: Sean Paul
This patch adds HDCP 1.x support to msm DP connectors using the new HDCP
helpers.
Cc: Stephen Boyd
Cc: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
Link:
https://patchwork.freedesktop.o
On 18/01/2023 21:30, Mark Yacoub wrote:
From: Sean Paul
This patch moves the hdcp atomic check from i915 to drm_hdcp so other
drivers can use it. No functional changes, just cleaned up some of the
code when moving it over.
Acked-by: Jani Nikula
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Am 19.01.23 um 12:12 schrieb Daniel Vetter:
On Thu, Jan 19, 2023 at 11:37:39AM +0100, Maarten Lankhorst wrote:
On 2023-01-19 11:24, Paul Cercueil wrote:
Hi,
Just a reflexion I have after an intensive (and intense) debugging
session.
I had the following code:
int my_dma_resv_lock(struct dma_
On 18/01/2023 21:30, Mark Yacoub wrote:
From: Sean Paul
Instead of forcing a modeset in the hdcp atomic check, simply return
true if the content protection value is changing and let the driver
decide whether a modeset is required or not.
I don't think this is a good idea. All foo_atomic_check
On 2023/1/19 2:00, Jason Gunthorpe wrote:
This is eventually called by iommufd through intel_iommu_map_pages() and
it should not be forced to atomic. Push the GFP_ATOMIC to all callers.
Signed-off-by: Jason Gunthorpe
Reviewed-by: Lu Baolu
Best regards,
baolu
Am 19.01.23 um 11:26 schrieb Daniel Vetter:
[SNIP]
I guess next step is that people will use chatgpt to write the patches for
these bugs.
To be honest I think that would result in quite some improvement in the
average patch quality.
That guessing this AI does has at least a statistically pro
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display
On 2023/1/19 2:00, Jason Gunthorpe wrote:
Flow it down to alloc_pgtable_page() via pfn_to_dma_pte() and
__domain_mapping().
Signed-off-by: Jason Gunthorpe
Irrelevant to this patch, GFP_ATOMIC could be changed to GFP_KERNEL in
some places. I will follow up further to clean it up.
For this patc
Hi,
On 19.01.2023 12:11, Daniel Vetter wrote:
> On Tue, Jan 17, 2023 at 10:27:16AM +0100, Jacek Lawrynowicz wrote:
>> Hi,
>>
>> This patchset contains a new Linux* Kernel Driver for Intel® VPUs.
>>
>> VPU stands for Versatile Processing Unit and it is an AI inference
>> accelerator
>> integrated
On 2023/1/19 19:57, Baolu Lu wrote:
On 2023/1/19 2:00, Jason Gunthorpe wrote:
Flow it down to alloc_pgtable_page() via pfn_to_dma_pte() and
__domain_mapping().
Signed-off-by: Jason Gunthorpe
Irrelevant to this patch, GFP_ATOMIC could be changed to GFP_KERNEL in
some places. I will follow up f
On 2023/1/19 2:00, Jason Gunthorpe wrote:
These contexts are sleepable, so use the proper annotation. The GFP_ATOMIC
was added mechanically in the prior patches.
Signed-off-by: Jason Gunthorpe
Reviewed-by: Lu Baolu
Best regards,
baolu
Hi Heiko,
On 11/30/22 15:02, Michael Riesch wrote:
> The rk3568-pinctrl.dtsi only defines the 24-bit RGB interface. Add separate
> nodes for the 16-bit and 18-bit version, respectively. While at it, split
> off the clock/sync signals from the data signals.
>
> The exact mapping of the data pins w
/20230119/202301191956.s3acgxpu-...@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add drm-misc git
[AMD Official Use Only - General]
Hi,
With Kernel v5.15 -> v6.1 upgradation, I have noticed that, now consecutive
Plane IDs values are incremented by 2 each time. i.e. 34,36,38. In kernel
v5.15, it was incremented by 1. i.e. 34,35,36...
I attached modetest log with kernel v6.1.
Is this change
On Wed, 18 Jan 2023, Ville Syrjälä wrote:
> On Wed, Jan 04, 2023 at 12:05:30PM +0200, Jani Nikula wrote:
>> The BPC quirks are closer to home in update_display_info().
>>
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Ville Syrjälä
Thanks, also pushed patches 12-15 becaus
On Wed, Jan 04, 2023 at 12:05:31PM +0200, Jani Nikula wrote:
> By moving update_display_info() out of _drm_edid_connector_update() we
> make the function purely about adding modes. Rename accordingly.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drive
On Wed, Jan 04, 2023 at 12:05:32PM +0200, Jani Nikula wrote:
> The original goal with drm_edid_connector_update() was to have a single
> call for updating the connector and adding probed modes, in this order,
> but that turned out to be problematic. Drivers that need to update the
> connector in th
On Wed, Jan 04, 2023 at 12:05:33PM +0200, Jani Nikula wrote:
> Realize that drm_edid_connector_update() and
> _drm_connector_update_edid_property() are now the same thing. Drop the
> latter.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm
On Tue, Jan 17, 2023 at 4:05 PM Dan Carpenter wrote:
>
> Hello Oded Gabbay,
>
> The patch c216477363a3: "habanalabs: add debugfs support" from Feb
> 16, 2019, leads to the following Smatch static checker warning:
>
> drivers/accel/habanalabs/common/debugfs.c:272 vm_show()
> warn: s
On 18/01/2023 21:30, Mark Yacoub wrote:
From: Sean Paul
This patch expands upon the HDCP helper library to manage HDCP
enable, disable, and check.
Previous to this patch, the majority of the state management and sink
interaction is tucked inside the Intel driver with the understanding
that onc
Hi Sascha,
Thanks for your comments!
On 12/7/22 07:45, Sascha Hauer wrote:
> On Wed, Nov 30, 2022 at 03:02:13PM +0100, Michael Riesch wrote:
>> Commit 540b8f271e53 ("drm/rockchip: Embed drm_encoder into
>> rockchip_decoder") provides the means to pass the endpoint ID to the
>> VOP2 driver, which
From: Mikko Perttunen
In anticipation of removal of the intr API, move host1x_syncpt_wait
to use DMA fences instead. As of this patch, this means that waits
have a 30 second maximum timeout because of the implicit timeout
we have with fences, but that will be lifted in a follow-up patch.
Signed-
From: Mikko Perttunen
Move from the old, complex intr handling code to a new implementation
based on dma_fences. While there is a fair bit of churn to get there,
the new implementation is much simpler and likely faster as well due
to allowing signaling directly from interrupt context.
Signed-off
From: Mikko Perttunen
Currently all fences have a 30 second timeout to ensure they are
cleaned up if the fence never completes otherwise. However, this
one size fits all solution doesn't actually fit in every case,
such as syncpoint waiting where we want to be able to have timeouts
longer than 30
From: Mikko Perttunen
In anticipation of removal of the intr API, implement job tracking
using DMA fences instead. The main two things about this are
making cdma_update schedule the work since fence completion can
now be called from interrupt context, and some complication in
ensuring the callbac
The type for operating-points-v2 property is coming from dtschema
(/schemas/opp/opp.yaml), so individual bindings can just use simple
"true".
Signed-off-by: Krzysztof Kozlowski
---
This depends on my pull request, at least logically:
https://github.com/devicetree-org/dt-schema/pull/95
Patch co
Make msm8960's HDMI PHY accept clocks from DT and also register it as a
DT clock provider.
Dmitry Baryshkov (6):
dt-bindings: phy: qcom,hdmi-phy-other: use pxo clock
dt-bindings: phy: qcom,hdmi-phy-other: mark it as clock provider
drm/msm/hdmi: switch hdmi_pll_8960 to use parent_data
drm/m
Add pxo clock to the 8960 bindings (used by the HDMI PLL)
Signed-off-by: Dmitry Baryshkov
---
.../bindings/phy/qcom,hdmi-phy-other.yaml | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
b/D
Replace parent_names usage with parent_data. Note, that this makes the
PLL default to board's `pxo_board' clock rather than just `pxo' clock,
as we are on a way to deprecate the global cxo/pxo clocks.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 6 +++---
1 file
Eventually all HDMI PHYs are going to provide the HDMI PLL clock to the
MMCC. Add #clock-cells property required to provide the HDMI PLL clock to
other devices.
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/phy/qcom,hdmi-phy-other.yaml | 4
1 file changed, 4 insertion
Add #clock-cells property to the HDMI PHY device node to let other nodes
resolve the hdmipll clock.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dt
Link hdmi_phy as a clock provider of "hdmipll" clock to the MMCC.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 82c795beb
On MSM8960 the HDMI PHY provides the PLL clock to the MMCC. As we are
preparing to convert the MSM8960 to use DT clocks properties (rather
than global clock names), register the OF clock provider.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 15 ++-
On Tue, 17 Jan 2023 18:52:35 +0100, Nirmoy Das wrote:
> Currently there is no easy way for a drm driver to safely check and allow
> drm_vma_offset_node for a drm file just once. Allow drm drivers to call
> non-refcounted version of drm_vma_node_allow() so that a driver doesn't
> need to keep track
On 1/19/2023 2:25 PM, Maxime Ripard wrote:
On Tue, 17 Jan 2023 18:52:35 +0100, Nirmoy Das wrote:
Currently there is no easy way for a drm driver to safely check and allow
drm_vma_offset_node for a drm file just once. Allow drm drivers to call
non-refcounted version of drm_vma_node_allow() so t
From: Mikko Perttunen
On Tegra186+, the syncpoint ID has 10 bits of space. To allow
using more than 256 syncpoints, fix the mask.
Fixes: 9abdd497cd0a ("gpu: host1x: Tegra234 device data and headers")
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 2 +-
drivers/
From: Mikko Perttunen
Ensure appropriate configuration is done to make the host1x device
and context devices DMA coherent by adding the dma-coherent flag.
Fixes: b35f5b53a87b ("arm64: tegra: Add context isolation domains on Tegra234")
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvid
From: Mikko Perttunen
In the IMM opcode check, don't call is_addr_reg if it's not set.
Fixes: 8cc95f3fd35e ("drm/tegra: Add job firewall")
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/firewall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/tegra/firewall.c
From: Mikko Perttunen
The code to write the syncpoint channel assignment register
incorrectly skips the write if hypervisor registers are not available.
The register, however, is within the guest aperture so remove the
check and assign syncpoints properly even on virtualized systems.
Fixes: c3f
On Thu, Jan 19, 2023 at 03:23:08PM +0900, Byungchul Park wrote:
> Boqun wrote:
> > * Looks like the DEPT dependency graph doesn't handle the
> > fair/unfair readers as lockdep current does. Which bring the
> > next question.
>
> No. DEPT works better for unfair read. It works based on wa
On 19.01.2023 14:22, Dmitry Baryshkov wrote:
> Replace parent_names usage with parent_data. Note, that this makes the
> PLL default to board's `pxo_board' clock rather than just `pxo' clock,
> as we are on a way to deprecate the global cxo/pxo clocks.
>
> Signed-off-by: Dmitry Baryshkov
> ---
On 19.01.2023 14:22, Dmitry Baryshkov wrote:
> On MSM8960 the HDMI PHY provides the PLL clock to the MMCC. As we are
> preparing to convert the MSM8960 to use DT clocks properties (rather
> than global clock names), register the OF clock provider.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Revi
ps = {
---
base-commit: 43bde505d66a41c2ad706d603e97b2c8aa2fbe4a
change-id: 20230119-topic-sm8550-vtdr6130-fixup-fb25f686ba59
Best regards,
--
Neil Armstrong
ghtness);
> - if (ret < 0)
> - return ret;
> -
> - return 0;
> + return mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
> }
>
> static const struct backlight_ops visionox_vtdr6130_bl_ops = {
>
> ---
> base-commit: 43bde505d66a41c2ad706d603e97b2c8aa2fbe4a
> change-id: 20230119-topic-sm8550-vtdr6130-fixup-fb25f686ba59
>
> Best regards,
> --
> Neil Armstrong
On 19.01.2023 14:22, Dmitry Baryshkov wrote:
> Link hdmi_phy as a clock provider of "hdmipll" clock to the MMCC.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> dif
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Chang
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/drm_atomic.c | 60 ++
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Ba
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_brid
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/panel.c | 20 +++
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/bridge
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++-
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dis
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
---
.../gpu/drm/msm/disp/dpu1/dpu_e
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 +
1 file change
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/di
Clear interface active register from the datapath for a clean shutdown of
the datapath.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/
[adding various lists and the two other nouveau maintainers to the list
of recipients]
For the rest of this mail:
[TLDR: I'm adding this report to the list of tracked Linux kernel
regressions; the text you find below is based on a few templates
paragraphs you might have encountered already in sim
Hi,
On Thu, 19 Jan 2023 15:04:12 +0100, Neil Armstrong wrote:
> Fix the following warning:
> panel-visionox-vtdr6130.c:249:12: warning: 'ret' is used uninitialized
> [-Wuninitialized]
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next)
[1/1] drm/panel:
Hi all,
This series adds support for the RGB output block that can be found in the
Rockchip Video Output Processor (VOP) 2. Version 2 of this series incorporates
the feedback by Dan Carpenter and Sascha Hauer. Thanks for your comments!
Patches 1-4 clean up the code and make it more general.
Patc
The VOP2 driver has more than one video port, hence the hard-coded
port id will not work anymore. Add an extra parameter for the video
port id to the rockchip_rgb_init function.
Signed-off-by: Michael Riesch
---
v2:
- no changes
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
drivers/gpu/d
The rk3568-pinctrl.dtsi only defines the 24-bit RGB interface. Add separate
nodes for the 16-bit and 18-bit version, respectively. While at it, split
off the clock/sync signals from the data signals.
The exact mapping of the data pins was discussed here:
https://lore.kernel.org/linux-rockchip/f33a
The variable possible_crtcs is only initialized for primary and
overlay planes. Since the VOP2 driver only supports these plane
types at the moment, the current code is safe. However, in order
to provide a future-proof solution, fix the initialization of
the variable.
Reported-by: kernel test robo
Let the function name vop2_create_crtcs reflect that the function creates
multiple CRTCS. Also, use a symmetric function pair to create and destroy
the CRTCs and the corresponding planes.
Signed-off-by: Michael Riesch
---
v2:
- no changes
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 31 +
The Rockchip VOP2 features an internal RGB output block, which can be
attached to the video port 2 of the VOP2. Add support for this output
block.
Signed-off-by: Michael Riesch
---
v2:
- move away from wrong assumption that the RGB block is always
connected to video port 2 -> check devicetree
Commit 540b8f271e53 ("drm/rockchip: Embed drm_encoder into
rockchip_decoder") provides the means to pass the endpoint ID to the
VOP2 driver, which sets the interface MUX accordingly. However, this
step has not yet been carried out for the RGB output block. Embed the
drm_encoder structure into the r
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