A series of patches to fix mode programming for the Lontium lt9611
DSI-to-HDMI bridge (found e.g. on the Thundercomm RB3/Dragonboard845c
platform).
Changes since v2:
- Rewrote mode_valid callback to be more explicit.
Changes since v1:
- Fixed the double-DSI check to look for the lt9611->dsi1_no
Fix programming of hsync and vsync polarities
Fixes: 23278bf54afe ("drm/bridge: Introduce LT9611 DSI to HDMI bridge")
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
The mode_set callback is deprectated for drm_bridges in favour of using
atomic_enable callback. Move corresponding code into the function
lt9611_bridge_atomic_enable() and turn lt9611_bridge_pre_enable() into
the proper atomic_pre_enable callback.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry
On atomic_post_disable the bridge goes to the low power state. However
the code disables too much of the chip, so the HPD event is not being
detected and delivered to the host. Reduce the power saving in order to
get the HPD event.
Fixes: 23278bf54afe ("drm/bridge: Introduce LT9611 DSI to HDMI bri
The bindings require that there is a next bridge after the lt9611. If
nothing else it can be the hdmi-connector (as used on the RB3 platform,
see sdm845-db845c.dts).
Bring in the next bridge into the drm bridges chain and attach to it.
Since lt9611 is not anymore the last bridge in the chain, thi
The driver will reset the bridge in the atomic_pre_enable(). However
this will also drop the HPD interrupt state. Instead of resetting the
bridge, properly wake it up. This fixes the HPD interrupt delivery after
the disable/enable cycle.
Fixes: 23278bf54afe ("drm/bridge: Introduce LT9611 DSI to HD
Pass a pointer to the OF node while registering lt9611 MIPI device.
Fixes: 23278bf54afe ("drm/bridge: Introduce LT9611 DSI to HDMI bridge")
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Program the upper part of the hfront_porch into the proper register.
Fixes: 23278bf54afe ("drm/bridge: Introduce LT9611 DSI to HDMI bridge")
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 3 ++-
1 file changed, 2 insertions(+), 1 deleti
Attaching DVI sink to the lt9611 requires different setup. Fix the
register write to make the DVI displays sync onto the correct sync
pulse.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 9 ++---
1 file changed, 6 insertions(+), 3
Rework handling infoframes:
- Write full HDMI AVI infoframe instead of just fixing the VIC value
- Also send the HDMI Vendor Specific infoframe, as recommended by the
HDMI spec.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 57 ++
Inline calculated values to simplify the calculation in
lt9611_mipi_video_setup().
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/lontium-lt961
The lt9611 bridge can support different modes, it makes no sense to list
them in the table. Drop the table and check the number of interfaces
using the fixed value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 49 ++---
1 file changed, 12 inse
If the bridge is connected using both DSI ports, the driver should use
both of them all the time. Correct programming sequence to always use
dual-port mode if both dsi0 and dsi1 are connected.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.
Instead of having several fixed values for the pcr register, calculate
it before programming. This allows the bridge to support most of the
display modes.
Fixes: 23278bf54afe ("drm/bridge: Introduce LT9611 DSI to HDMI bridge")
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
driv
On Tue, Jan 17, 2023 at 01:36:26PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When GuC support was added to error capture, the locking around the
> request object was broken. Fix it up.
>
> The context based search manages the spinlocking around the search
> internally. So
On 18/01/2023 09:16, Dmitry Baryshkov wrote:
The lt9611 bridge can support different modes, it makes no sense to list
them in the table. Drop the table and check the number of interfaces
using the fixed value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 49 ++
On Tue, Jan 17, 2023 at 01:12:39PM -0600, Chris Morgan wrote:
> On Tue, Jan 17, 2023 at 05:58:19PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, Jan 12, 2023 at 11:53:55AM -0600, Chris Morgan wrote:
> > > From: Chris Morgan
> > >
> > > Add helper function to find DSI host for devices where
That one should probably be squashed into the original patch.
Christian.
Am 18.01.23 um 07:12 schrieb Danilo Krummrich:
Don't call drm_gem_object_get() unconditionally.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/drm_exec.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers
Am 18.01.23 um 07:12 schrieb Danilo Krummrich:
This patch series provides a new UAPI for the Nouveau driver in order to
support Vulkan features, such as sparse bindings and sparse residency.
Furthermore, with the DRM GPUVA manager it provides a new DRM core feature to
keep track of GPU virtual a
On Wed, Jan 18, 2023 at 01:39:05AM +0200, Dmitry Baryshkov wrote:
> There are two flags attemting to guard connector polling:
> poll_enabled and poll_running. While poll_enabled semantics is clearly
> defined and fully adhered (mark that drm_kms_helper_poll_init() was
> called and not finalized by
On Tue, Jan 17, 2023 at 05:37:29PM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The definition of intel_selftest_modify_policy() does not match the
> declaration, as gcc-13 points out:
>
> drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c:29:5: error:
> conflicting types for 'in
Hi guys,
for a couple of weeks now the command "dim rebuild-tip" fails for me.
The error message is:
Merging drm-intel/drm-intel-gt-next... Applying manual fixup patch for
drm-tip merge... patching file drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
dim:
dim: FAILURE: Could not merge drm-intel/drm
This series is based on matthias github, for-next.
Changes since v1:
- Remove the unnecessary trailing number
- Add aliases for ovl* and rdma*
Allen-KH Cheng (9):
arm64: dts: mediatek: mt8186: Add MTU3 nodes
dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as
fallback of
The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186,
document this situation.
Signed-off-by: Allen-KH Cheng
Reviewed-by: Rob Herring
---
.../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documen
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 3d88480913eb..a8ff984f1192
The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr
implementation. It causes a crash when system resumes if it binds to the
device.
We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr.
Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding"
Add display nodes and GCE info for MT8186 SoC. Also, add GCE
(Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for
operating the display.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi |
Add ADSP mailbox node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a8ff984f1192..a0b7dacc10
Variables 'sc8280xp_regdma' and 'sm8350_regdma' are defined in the
dpu_hw_catalog.c file, but not used elsewhere, so remove these unused
variables.
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:2029:37: warning: unused
variable 'sc8280xp_regdma'.
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:205
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Tested-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c52f9
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 2700c83031
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a0b7dacc10cd..2700c830316f
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Tested-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
in
Hi,
Thanks for working on this, it looks good to me and it aligns with how i915
uses the facility.
Copying Mirsad who reported the issue in case he is still happy to give it a
quick test. Mirsad, I don't know if you are subscribed to one of the two
mailing lists where series was posted. In
On 17/01/2023 17:52, Nirmoy Das wrote:
Currently there is no easy way for a drm driver to safely check and allow
drm_vma_offset_node for a drm file just once. Allow drm drivers to call
non-refcounted version of drm_vma_node_allow() so that a driver doesn't
need to keep track of each drm_vma_nod
Hi Tvrtko,
On 1/18/2023 10:19 AM, Tvrtko Ursulin wrote:
Hi,
Thanks for working on this, it looks good to me and it aligns with how
i915 uses the facility.
Copying Mirsad who reported the issue in case he is still happy to
give it a quick test. Mirsad, I don't know if you are subscribed to
Hi
Am 18.01.23 um 10:13 schrieb Christian König:
Hi guys,
for a couple of weeks now the command "dim rebuild-tip" fails for me.
The error message is:
Merging drm-intel/drm-intel-gt-next... Applying manual fixup patch for
drm-tip merge... patching file drivers/gpu/drm/i915/gt/uc/intel_uc_fw.
From: Arnd Bergmann
gcc-13 notices a mismatch between the return type of dp_retrieve_lttpr_cap()
and the returned value:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c: In function
'dp_retrieve_lttpr_cap':
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:14
Hi Nirmoy,
On Tue, Jan 17, 2023 at 01:32:34PM +0100, Nirmoy Das wrote:
> From: Chris Wilson
>
> Make sure that upon error after we have acquired the wakeref we do
> release it again.
>
> v2: add another missing "goto out_wf"(Andi).
>
> Fixes: 027c38b4121e ("drm/i915/selftests: Grab the runtime
Am 18.01.23 um 10:29 schrieb Thomas Zimmermann:
Hi
Am 18.01.23 um 10:13 schrieb Christian König:
Hi guys,
for a couple of weeks now the command "dim rebuild-tip" fails for me.
The error message is:
Merging drm-intel/drm-intel-gt-next... Applying manual fixup patch
for drm-tip merge... patc
On 1/18/2023 7:27 AM, Christian König wrote:
Am 17.01.23 um 19:12 schrieb Das, Nirmoy:
Hi Alex,
On 1/17/2023 7:06 PM, Alex Deucher wrote:
On Tue, Jan 17, 2023 at 1:05 PM Nirmoy Das
wrote:
There are no current users of DRM_DEBUG_KMS_RATELIMITED()
so remove it.
Cc: Maarten Lankhorst
Cc:
On Tue, Jan 17, 2023 at 06:52:35PM +0100, Nirmoy Das wrote:
> Currently there is no easy way for a drm driver to safely check and allow
> drm_vma_offset_node for a drm file just once. Allow drm drivers to call
> non-refcounted version of drm_vma_node_allow() so that a driver doesn't
> need to keep
Hi,
On Wed, Jan 18, 2023 at 09:19:40AM +, Tvrtko Ursulin wrote:
>
>
> Hi,
>
> Thanks for working on this, it looks good to me and it aligns with how i915
> uses the facility.
>
> Copying Mirsad who reported the issue in case he is still happy to give it a
> quick test. Mirsad, I don't kn
On 1/18/2023 10:38 AM, Andi Shyti wrote:
On Tue, Jan 17, 2023 at 06:52:35PM +0100, Nirmoy Das wrote:
Currently there is no easy way for a drm driver to safely check and allow
drm_vma_offset_node for a drm file just once. Allow drm drivers to call
non-refcounted version of drm_vma_node_allow()
On 16/01/2023 23:49, Richard Acayan wrote:
From: Daniel Mentz
The MIPI DCS specification demands that brightness values are sent in
big endian byte order. It also states that one parameter (i.e. one byte)
shall be sent/received for 8 bit wide values, and two parameters shall
be used for values
On 16/01/2023 23:49, Richard Acayan wrote:
This panel communicates brightness in big endian. This is not a quirk of
the panels themselves, but rather, a part of the MIPI standard. Use the
new mipi_dsi_dcs_set_display_brightness_large() function that properly
handles 16-bit brightness instead of b
On 16/01/2023 23:49, Richard Acayan wrote:
These panels communicate brightness in big endian. This is not a quirk
of the panels themselves, but rather, a part of the MIPI standard. Use
the new mipi_dsi_dcs_set_display_brightness_large() function that
properly handles 16-bit brightness instead of
Hi guys,
after analyzing this a bit more I think what happened that the patch
"drm/i915: improve the catch-all evict to handle lock contention" came
into drm-tip through both the drm-intel-gt-next and drm-intel-next tree.
It looks like this somehow worked for some people while it broke for me
On 2023-01-18 17:18:33, Jiapeng Chong wrote:
> Variables 'sc8280xp_regdma' and 'sm8350_regdma' are defined in the
> dpu_hw_catalog.c file, but not used elsewhere, so remove these unused
> variables.
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:2029:37: warning: unused
> variable 'sc8280xp_re
On 1/18/2023 11:26 AM, Mirsad Todorovac wrote:
Hi,
On 1/18/23 10:19, Tvrtko Ursulin wrote:
Thanks for working on this, it looks good to me and it aligns with
how i915 uses the facility.
Copying Mirsad who reported the issue in case he is still happy to
give it a quick test. Mirsad, I don'
Add support for Kinetic KTZ8866 backlight, which is used in
Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
downstream implementation [1].
[1]
https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/elish-r-oss/drivers/video/backlight/ktz8866.c
Signed-off-by: Jianhua Lu
---
Changes
From: Tomi Valkeinen
Hi,
Here are some small rcar-du patches based on commits in the Renesas BSP
tree.
Tomi
Koji Matsuoka (2):
drm: rcar-du: lvds: Add reset control
drm: rcar-du: Fix LVDS stop sequence
Tomi Valkeinen (4):
drm: rcar-du: dsi: add 'select RESET_CONTROLLER'
drm: rcar-du:
On 09/01/2023 18:21, Aradhya Bhatia wrote:
Hi Angelo,
Thanks for taking a look at the patches!
On 03-Jan-23 17:21, AngeloGioacchino Del Regno wrote:
Il 03/01/23 07:46, Aradhya Bhatia ha scritto:
Dual-link LVDS interfaces have 2 links, with even pixels traveling on
one link, and odd pixels on
On Tue, Jan 17, 2023 at 02:04:05PM +, Daniel Thompson wrote:
> On Tue, Jan 17, 2023 at 09:47:41PM +0800, Jianhua Lu wrote:
> > Add support for Kinetic KTZ8866 backlight, which is used in
> > Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
> > downstream implementation [1].
> > [1]
On Tue, Jan 17, 2023 at 02:37:07PM +, Daniel Thompson wrote:
> On Tue, Jan 17, 2023 at 10:12:18PM +0800, Jianhua Lu wrote:
> > On Tue, Jan 17, 2023 at 02:04:05PM +, Daniel Thompson wrote:
> > > On Tue, Jan 17, 2023 at 09:47:41PM +0800, Jianhua Lu wrote:
> > > > Add support for Kinetic KTZ88
The RCAR DSI driver uses reset controller, so we should select it in the
Kconfig.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index fd2c2eaee26b..a8f862c68b
From: Koji Matsuoka
According to H/W manual, LVDCR0 register must be cleared bit by bit when
disabling LVDS.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 27 +++
> Since there are people around with real hardware is sh in big endian mode
> (sheb) real ? Its qemu support is quite limited; most PCI devices don't work
> due to endianness issues. It would be interesting to know if this works better
> with real hardware.
Hi Guenter,
SH big endian works
From: Koji Matsuoka
Reset LVDS using the reset control as CPG reset/release is required in
H/W manual sequence.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: Rewrite the patch description]
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
d
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF8Rm, ESCRn, OTARn.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 6 --
2 files changed, 9 insertions(+), 5 deletions(-)
d
On Tue, Jan 17, 2023 at 02:22:04PM +, Daniel Thompson wrote:
> On Tue, Jan 17, 2023 at 09:47:42PM +0800, Jianhua Lu wrote:
> > Add Kinetic KTZ8866 backlight binding documentation.
> >
> > Signed-off-by: Jianhua Lu
>
> Might be a good idea to take a look at this bit of the docs because
> the p
On H3 ES1 two bits in DPLLCR are used to select the DU input dot clock
source. These are bits 20 and 21 for DU2, and bits 22 and 23 for DU1. On
non-ES1, only the higher bits are used (bits 21 and 23), and the lower
bits are reserved and should be set to 0 (or not set at all).
The current code alwa
Le dim. 15 janv. 2023 à 22:45, David Airlie a écrit :
>
> On Thu, Dec 29, 2022 at 12:58 AM Diogo Ivo
> wrote:
> >
> > Hello,
> >
> > Commit 2541626cfb79 breaks GM20B probe with
> > the following kernel log:
> >
> > [2.153892] [ cut here ]
> > [2.153897] WARNING: C
Add support for Kinetic KTZ8866 backlight, which is used in
Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
downstream implementation [1].
[1]
https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/elish-r-oss/drivers/video/backlight/ktz8866.c
Signed-off-by: Jianhua Lu
---
Changes
Add Kinetic KTZ8866 backlight binding documentation.
Signed-off-by: Jianhua Lu
---
Changes in v2:
- Remove "items" between "compatible" and "const: kinetic,ktz8866"
- Change "additionalProperties" to "unevaluatedProperties"
Changes in v3:
- Add Krzysztof's R-b
Changes in v4:
- Drop Krzy
Add Kinetic KTZ8866 backlight binding documentation.
Signed-off-by: Jianhua Lu
---
Changes in v2:
- Remove "items" between "compatible" and "const: kinetic,ktz8866"
- Change "additionalProperties" to "unevaluatedProperties"
Changes in v3:
- Add Krzysztof's R-b
Changes in v4:
- Drop Krzy
rcar_du_crtc.c does a soc_device_match() in
rcar_du_crtc_set_display_timing() to find out if the SoC is H3 ES1, and
if so, apply a WA.
We will need another H3 ES1 check in the following patch, so rather than
adding more soc_device_match() calls, let's add a rcar_du_device_info
entry for the ES1, a
On 1/18/23 01:46, Geert Uytterhoeven wrote:
> Again, I think you're talking about something different.
> Does kexec work for you?
Sorry, got woken up several hours early by sirens and flashy lights this morning
(duplex on the corner caught fire, Austin has a LOT of emergency vehicles), been
a bit
On 17/01/2023 16:44, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> On ARMv5 and earlier, a randconfig build can still run into
>
> WARNING: unmet direct dependencies detected for IOMMU_IO_PGTABLE_LPAE
> Depends on [n]: IOMMU_SUPPORT [=y] && (ARM [=y] || ARM64 || COMPILE_TEST
> [=y]) && !GENE
On Wed, 18 Jan 2023, Christian König wrote:
> Hi guys,
>
> for a couple of weeks now the command "dim rebuild-tip" fails for me.
> The error message is:
>
> Merging drm-intel/drm-intel-gt-next... Applying manual fixup patch for
> drm-tip merge... patching file drivers/gpu/drm/i915/gt/uc/intel_uc
On 2023-01-18 11:09, Steven Price wrote:
On 17/01/2023 16:44, Arnd Bergmann wrote:
From: Arnd Bergmann
On ARMv5 and earlier, a randconfig build can still run into
WARNING: unmet direct dependencies detected for IOMMU_IO_PGTABLE_LPAE
Depends on [n]: IOMMU_SUPPORT [=y] && (ARM [=y] || ARM64
Hi Dave, Daniel,
Here goes the first pull request for 6.3.
What sticks out most is the amount of fixes, majority of which if not all
would have already landed via gt/next fixes pull requests though, so I
will only mention them here briefly.
Most impactful ones are probably in the area of DG2 TLB
Am 18.01.23 um 12:16 schrieb Jani Nikula:
On Wed, 18 Jan 2023, Christian König wrote:
Hi guys,
for a couple of weeks now the command "dim rebuild-tip" fails for me.
The error message is:
Merging drm-intel/drm-intel-gt-next... Applying manual fixup patch for
drm-tip merge... patching file d
>
> From: Alexander Usyskin
>
> Asynchronous runtime resume is not possible while the system is
> suspending.
> The power management subsystem resumes the device only in the suspend
> phase, not in the prepare phase.
> Force resume device in prepare to allow drivers on mei bus to communicate
> i
>
> From: Alexander Usyskin
>
> Client on bus have only one vtag map slot and should disregard the vtag
> value when cleaning pending read flag.
> Fixes read flow control message unexpectedly generated when clent on bus
> send messages with different vtags.
>
> Signed-off-by: Alexander Usyski
On Tue, Jan 17, 2023 at 11:44:08PM +0800, Jianhua Lu wrote:
> Add support for Kinetic KTZ8866 backlight, which is used in
> Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
> downstream implementation [1].
> [1]
> https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/elish-r-oss/driv
Hi,
On 1/18/23 10:19, Tvrtko Ursulin wrote:
Thanks for working on this, it looks good to me and it aligns with how i915
uses the facility.
Copying Mirsad who reported the issue in case he is still happy to give it a quick test. Mirsad, I don't know if you are subscribed
to one of the two mai
On RX5000 series GPUs, using a high refresh rate monitor causes the VRAM to
always stay at the highest clock (according to AMD, this is done to prevent
flickering).
However, when using 2 monitors (e.g. one at 165Hz and another at 60Hz), then
disconnecting the high refresh monitor, before this patc
Le mer. 18 janv. 2023 à 02:29, Ben Skeggs a écrit :
>
> On Mon, 16 Jan 2023 at 22:27, Diogo Ivo wrote:
> >
> > On Mon, Jan 16, 2023 at 07:45:05AM +1000, David Airlie wrote:
> > > On Thu, Dec 29, 2022 at 12:58 AM Diogo Ivo
> > > wrote:
> > > As a quick check can you try changing
> > >
> > > driv
Hi,
On 1/18/23 11:39, Das, Nirmoy wrote:
On 1/18/2023 11:26 AM, Mirsad Todorovac wrote:
Hi,
On 1/18/23 10:19, Tvrtko Ursulin wrote:
Thanks for working on this, it looks good to me and it aligns with how i915
uses the facility.
Copying Mirsad who reported the issue in case he is still happ
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Tested-by: Chen-Yu Tsai
Reviewed-by: AngeloGioacchino Del Regno
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add display nodes and GCE info for MT8186 SoC. Also, add GCE
(Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for
operating the display.
Signed-off-by: Allen-KH Cheng
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Reviewed-by: AngeloGioacchino Del Regno
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Tested-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.d
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add ADSP mailbox node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Reviewed-by: AngeloGioacchino Del Regno
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/med
Il 18/01/23 10:18, Allen-KH Cheng ha scritto:
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/medi
On 18/01/2023 07:16, Niranjana Vishwanathapura wrote:
Support dump capture of persistent mappings upon user request.
Capture of a mapping is requested with the VM_BIND ioctl and
processed during the GPU error handling. They are synchronously
unbound during eviction so that no additional vma reso
On 18/01/2023 07:16, Niranjana Vishwanathapura wrote:
Properly build the sg table for persistent mapping which can
be partial map of the underlying object. Ensure the sg pages
are properly set for page backed regions. The dump capture
support requires this for page backed regions.
v2: Remove red
According to the vendor kernel, byte intf clock rate should be a half of
the byte clock only when DSI PHY version is above 2.0 (in other words,
10nm PHYs and later) and only if PHY is used in D-PHY mode. Currently
MSM DSI code handles only the second part of the clause (C-PHY vs
D-PHY), skipping DS
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2 hosts.
Also, while we are at it, replace another dsi_get_pclk_rate() invocation
with using the stored value at msm_host->pixel_clk_rate.
Signed-off-by: Dmitry Barys
On Mon, Jan 09 2023 at 12:33, Byungchul Park wrote:
> +/*
> + * sdt_might_sleep() and its family will be committed in __schedule()
> + * when it actually gets to __schedule(). Both dept_request_event() and
> + * dept_wait() will be performed on the commit.
> + */
> +
> +/*
> + * Use the code locati
On Tue, Jan 17 2023 at 10:18, Boqun Feng wrote:
> On Mon, Jan 16, 2023 at 10:00:52AM -0800, Linus Torvalds wrote:
>> I also recall this giving a fair amount of false positives, are they all
>> fixed?
>
> From the following part in the cover letter, I guess the answer is no?
> ...
> 6
On Mon, Jan 09 2023 at 12:33, Byungchul Park wrote:
> It'd be useful to show Dept internal stats and dependency graph on
> runtime via proc for better information. Introduced the knobs.
proc?
That's what debugfs is for.
On Mon, Jan 09 2023 at 12:33, Byungchul Park wrote:
> Makes Dept able to track dependencies by
> wait_for_completion()/complete().
>
> In order to obtain the meaningful caller points, replace all the
> wait_for_completion*() declarations with macros in the header.
That's just wrong.
> -extern voi
Hi Dave & Daniel,
On 17/01/2023 17:52, Nirmoy Das wrote:
Currently there is no easy way for a drm driver to safely check and allow
drm_vma_offset_node for a drm file just once. Allow drm drivers to call
non-refcounted version of drm_vma_node_allow() so that a driver doesn't
need to keep track
It's been some time since I last sent this series. This version fixes
a regression Dan Johansen reported. The reason turned out to be simple,
I used the YUV420 register values instead of the RGB ones.
I realized that we cannot achieve several modes offered by my monitor
as these require pixelclock
The driver checks if the pixel clock of the given mode matches an entry
in the mpll config table. At least for the Synopsys phy the frequencies
in the mpll table are meant as a frequency range up to which the entry
works, not as a frequency that must match the pixel clock. Return
MODE_OK when the p
This adds the PLL/phy settings to support higher resolutions like 4k@30.
The values were taken from the Rockchip downstream Kernel.
Tested-by: Michael Riesch
Link: https://lore.kernel.org/r/20220926080435.259617-3-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v
The Rockchip PLL drivers are currently table based and support only
the most common pixelclocks. Discard all modes we cannot achieve
at all. Normally the desired pixelclocks have an exact match in the
PLL driver, nevertheless allow for a 0.1% error just in case.
Signed-off-by: Sascha Hauer
---
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