Hi
Am 22.12.22 um 23:21 schrieb Matthew Brost:
Hello,
This is a submission for Xe, a new driver for Intel GPUs that supports both
integrated and discrete platforms starting with Tiger Lake (first platform with
Intel Xe Architecture). The intention of this new driver is to have a fresh base
to w
On Sun, Jan 01, 2023 at 10:58:42PM -0600, Steev Klimaszewski wrote:
> On Sat, Dec 31, 2022 at 8:27 AM Abel Vesa wrote:
> >
> > The actual name is R133NW4K-R0.
> >
> > Fixes: 0f9fa5f58c784 ("drm/panel-edp: add IVO M133NW4J-R3 panel entry")
> > Signed-off-by: Abel Vesa
> > ---
> >
> > Assuming the
On Sat, Dec 31, 2022 at 04:27:21PM +0200, Abel Vesa wrote:
> Add an eDP panel entry for IVO M133NW4J.
>
> Due to lack of documentation, use the delay_200_500_p2e100 timings like
> some other IVO entries for now.
>
> Signed-off-by: Abel Vesa
> ---
>
> Assuming the information from here is correc
On Thu, Dec 29, 2022 at 12:34 PM Andrzej Hajda wrote:
> __xchg will be used for non-atomic xchg macro.
>
> Signed-off-by: Andrzej Hajda
> Reviewed-by: Arnd Bergmann
Acked-by: Geert Uytterhoeven [m68k]
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of
On 1/1/23 21:29, youling257 wrote:
> Linux 6.2-rc1 has memory leak on amdgpu, git bisect bad commit is
> "drm/scheduler: rework entity flush, kill and fini".
> git bisect start
> # status: waiting for both good and bad commits
> # good: [eb7081409f94a9a8608593d0fb63a1aa3d6f95d8] Linux 6.1-rc6
> gi
On 31.12.2022 22:50, Marijn Suijten wrote:
> Neither of these SoCs has INTF0, they only have a DSI interface on index
> 1. Stop enabling an interrupt that can't fire.
Double space.
Reviewed-by: Konrad Dybcio
Konrad
>
> Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM611
On 31.12.2022 22:52, Marijn Suijten wrote:
> On 2022-12-31 22:50:02, Marijn Suijten wrote:
>> Since hardware revision 5.0.0 the TE configuration moved out of the
>> PINGPONG block into the INTF block, including vsync source selection
>> that was previously part of MDP top. Writing to the MDP_VS
On 29/12/2022 14:31, Luca Ceresoli wrote:
> VIP is the parallel video capture component within the video input
> subsystem of Tegra20 (and other Tegra chips, apparently).
>
> Signed-off-by: Luca Ceresoli
>
> ---
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
Hello Pavel,
On 1/1/23 22:21, Pavel Machek wrote:
> Hi!
>
>> This series add support for the display present in the PinePhone Pro.
>>
>> Patch #1 adds a driver for panels using the Himax HX8394 panel controller,
>> such as the HSD060BHW4 720x1440 TFT LCD panel present in the PinePhone Pro.
>>
>>
On 12/29/2022 12:13 AM, Bjorn Andersson wrote:
> On Wed, Dec 21, 2022 at 10:43:59PM +0530, Akhil P Oommen wrote:
>> From: Ulf Hansson
>>
>> Some genpd providers doesn't ensure that it has turned off at hardware.
>> This is fine until the consumer really requires during some special
>> scenarios th
Hi,
On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on so
Hi
Am 21.12.22 um 21:07 schrieb Maíra Canal:
On 12/20/22 13:11, Thomas Zimmermann wrote:
Add dedicated helper to convert from XRGB to ARGB. Sets
all alpha bits to make pixels fully opaque.
v2:
* use cpubuf_to_le32()
* type fixes
Signed-off-by: Thomas Zimmermann
Review
Hi
Am 23.12.22 um 13:44 schrieb José Expósito:
Hi Thomas,
Compiling this patch with sparse enabled (you can do it from the KUnit
tests adding "--make_options C=2") throws a warning:
drm_format_helper.c:614:27: warning: incorrect type in assignment (different
base types)
drm_format_helper.c:61
So far the adreno quirks have all been assigned with an OR operator,
which is problematic, because they were assigned consecutive integer
values, which makes checking them with an AND operator kind of no bueno..
Switch to using BIT(n) so that only the quirks that the programmer chose
are taken int
Hi,
On Mon, 19 Dec 2022 10:02:36 +0100, Carlo Caione wrote:
> This patchset is trying to fix problems seen on S905X boards when interfacing
> with an ILI9486 equipped SPI panel.
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next)
[1/2] drm/tiny: ili9486
On 2023-01-02 10:29:03, Konrad Dybcio wrote:
>
>
> On 31.12.2022 22:50, Marijn Suijten wrote:
> > Neither of these SoCs has INTF0, they only have a DSI interface on index
> > 1. Stop enabling an interrupt that can't fire.
> Double space.
In case you hadn't noticed I'm employing this habit for q
On 2023-01-02 10:30:58, Konrad Dybcio wrote:
>
>
> On 31.12.2022 22:52, Marijn Suijten wrote:
> > On 2022-12-31 22:50:02, Marijn Suijten wrote:
> >> Since hardware revision 5.0.0 the TE configuration moved out of the
> >> PINGPONG block into the INTF block, including vsync source selection
> >> t
Move the cadence dsi bridge under drm/bridge/cadence
directory, to prepare for adding j721e wrapper
support
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/Kconfig| 11 ---
drivers/gpu/drm/bridge/Makefile | 1
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++
2 files changed, 157 insertions(+), 112 deletions(-)
dele
Add support for wrapper settings for DSI bridge on
j721e. Also enable DPI0
--- ---
| ---| |--- |
| DSS | DPI2 |->| DPI0 | DSI Wrapper |
| ---| |--- |
--- --
Create a header file for cdns dsi and move
register offsets and structure to header,
to prepare for adding j721e wrapper support
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
---
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 446 +
.../gpu/drm/bridge/cadence/cdns-dsi-co
Add compatible to support dsi bridge on j721e
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,dsi.yaml | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yam
On 2.01.2023 11:18, Marijn Suijten wrote:
> On 2023-01-02 10:30:58, Konrad Dybcio wrote:
>>
>>
>> On 31.12.2022 22:52, Marijn Suijten wrote:
>>> On 2022-12-31 22:50:02, Marijn Suijten wrote:
Since hardware revision 5.0.0 the TE configuration moved out of the
PINGPONG block into the INT
On 2023-01-01 06:28:23, Dmitry Baryshkov wrote:
> On 31/12/2022 23:50, Marijn Suijten wrote:
> > Since hardware revision 5.0.0 the TE configuration moved out of the
> > PINGPONG block into the INTF block. Writing these registers has no
> > effect, and is omitted downstream via the DPU/SDE_PINGPONG
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v10:
- Rebased to v6.2-rc1
- Accumulated the Reviewed-by acks
v9:
- Fixed below based on review comments in v8
- Added more info on wrapper in the commit message
- Fixed the description in Kconfig
- Fixed the formatting
Hi,
On Fri, 2 Dec 2022 12:52:12 +0100, Tomeu Vizoso wrote:
> This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
> as in the VIM3 board.
>
> The IP is very closely based on previous Vivante GPUs, so the etnaviv
> kernel driver works basically unchanged.
>
> The userspace par
Hi
Am 19.12.22 um 10:02 schrieb Carlo Caione:
SPI devices use the spi_device_id for module autoloading even on
systems using device tree.
Add the spi_device_id entry to enable autoloading for the 3.5inch RPi
Display (rpi-lcd-35 and piscreen).
Reviewed-by: Neil Armstrong
Signed-off-by: Carlo C
Hi,
On Fri, 2 Dec 2022 12:52:12 +0100, Tomeu Vizoso wrote:
> This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
> as in the VIM3 board.
>
> The IP is very closely based on previous Vivante GPUs, so the etnaviv
> kernel driver works basically unchanged.
>
> The userspace par
On 2023-01-01 15:12:35, Dmitry Baryshkov wrote:
> On 31/12/2022 23:50, Marijn Suijten wrote:
> >
> > -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch,
> > _features, _reg, _underrun_bit, _vsync_bit) \
> > +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch,
> >
Hi,
On Fri, 2 Dec 2022 12:52:12 +0100, Tomeu Vizoso wrote:
> This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
> as in the VIM3 board.
>
> The IP is very closely based on previous Vivante GPUs, so the etnaviv
> kernel driver works basically unchanged.
>
> The userspace par
On Thu, 29 Dec 2022 16:46:38 -0300, Maíra Canal wrote:
> If vc4_hdmi_reset_link() returns -EDEADLK, it means that a deadlock
> happened in the locking context. This situation should be addressed by
> dropping all currently held locks and block until the contended lock
> becomes available. Currently
On Thu, 22 Dec 2022 18:52:13 +, Dave Stevenson wrote:
> Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to drm_panel")
> added code to copy prepare_prev_first from drm_panel to pre_enable_prev_first
> in drm_bridge when called through devm_panel_bridge_add, but
> missed drmm_panel_
This is a rework of [1] using genpd instead of 'reset' framework.
As per the recommended reset sequence of Adreno gpu, we should ensure that
gpucc-cx-gdsc has collapsed at hardware to reset gpu's internal hardware states.
Because this gdsc is implemented as 'votable', gdsc driver doesn't poll an
From: Ulf Hansson
Some genpd providers doesn't ensure that it has turned off at hardware.
This is fine until the consumer really requires during some special
scenarios that the power domain collapse at hardware before it is
turned ON again.
An example is the reset sequence of Adreno GPU which re
Add support for the newly added 'synced_poweroff' genpd flag. This allows
some clients (like adreno gpu driver) to request gdsc driver to ensure
a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
---
(no changes since v3)
Chang
When a device has multiple power domains, dev->power_domain is left
empty during probe. That didn't cause any issue so far because we are
freeloading on smmu driver's vote on cx gdsc. Instead of that, create
a device_link between cx genpd device and gmu device to keep a vote from
gpu driver.
Befor
Remove the unused 'reset' interface which was supposed to help to ensure
that cx gdsc has collapsed during gpu recovery. This is was not enabled
so far due to missing gpucc driver support. Similar functionality using
genpd framework will be implemented in the upcoming patch.
This effectively rever
As per the recommended recovery sequence of adreno gpu, cx gdsc should
collapse at hardware before it is turned back ON. This helps to clear
out the stale states in hardware before it is reinitialized. Use the
genpd notifier along with the newly introduced
dev_pm_genpd_synced_poweroff() api to ensu
On 1/2/2023 3:32 PM, Konrad Dybcio wrote:
> So far the adreno quirks have all been assigned with an OR operator,
> which is problematic, because they were assigned consecutive integer
> values, which makes checking them with an AND operator kind of no bueno..
>
> Switch to using BIT(n) so that only
Hello Javier,
On Sat, Dec 31, 2022 at 04:29:49PM +0100, Javier Martinez Canillas wrote:
> Hello Ondřej,
>
> Thanks a lot for your feedback.
>
> On 12/30/22 16:37, Ondřej Jirman wrote:
>
> [...]
>
> >> &i2c0 {
> >>clock-frequency = <40>;
> >>i2c-scl-rising-time-ns = <168>;
> >> @@
Hello Javier,
On Sat, Dec 31, 2022 at 04:15:24PM +0100, Javier Martinez Canillas wrote:
> Hello Ondřej,
>
> Thanks a lot for your comments.
>
> On 12/30/22 16:40, Ondřej Jirman wrote:
> > Hi Javier,
> >
> > On Fri, Dec 30, 2022 at 12:31:52PM +0100, Javier Martinez Canillas wrote:
> >> From: Kam
On 2023-01-01 15:32:11, Dmitry Baryshkov wrote:
> On 31/12/2022 23:50, Marijn Suijten wrote:
> > Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the
> > PINGPONG block and into the INTF. Implement the necessary callbacks in
> > the INTF block, and use these callbacks together w
Fix the selection of the fbdev emulation's color format and make
XRGB the only emulated color format. Resolves the blank screen
in cases where video= specifies an unsupported color format. Also
resolves the issues around current format-conversion helpers.
Version 2 of the patchset fixes the fo
Select color format for EFI/VESA firmware scanout buffer from the
number of bits per pixel and the position of the individual color
components. Fixes the selected format for the buffer in several odd
cases. For example, XRGB1555 has been reported as ARGB1555 because
of the different use of depth an
Add dedicated helper to convert from XRGB to ARGB. Sets
all alpha bits to make pixels fully opaque.
v3:
* use __le32 for destination buffer (Jose, kernel test robot)
v2:
* use cpubuf_to_le32()
* type fixes
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Marti
Fix to-RGB565 conversion helpers to store the result in little-
endian byte order. Update test cases as well.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
drivers/gpu/drm/drm_format_helper.c | 9 +
.../gpu/drm/tests/drm_format_help
RGB888 is different than the other formats as most of its pixels are
unaligned and therefore helper functions do not use endianness conversion
helpers. Comment on this in the source code.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
drivers/gpu/drm/d
Convert test input for format helpers from host byte order to
little-endian order. The current code does it the other way around,
but there's no effective difference to the result.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
.../gpu/drm/tests/drm_fo
Change the source-buffer type of le32buf_to_cpu() to __le32* to
reflect endianness. Result buffers are converted to local endianness,
so instantiate them from regular u8 or u32 types.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
drivers/gpu/drm/tests
Add conversion from XRGB to XRGB1555, ARGB1555 and RGBA5551, which
are the formats currently supported by the simplefb infrastructure. The
new helpers allow the output of XRGB framebuffers to firmware
scanout buffers in one of the 15-bit formats.
v3:
* use __le* for destination buf
Add dedicated helper to convert from XRGB to ARGB2101010. Sets
all alpha bits to make pixels fully opaque.
v2:
* set correct format in struct drm_framebuffer (Javier)
* use cpubuf_to_le32()
* type fixes
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Can
Upcoming changes to the format conversion will mostly blit from
XRGB to some other format. So put the source format in blit's
outer branches to make the code more readable. For cases where
a format only changes its endianness, such as XRGB565, introduce
dedicated branches that handle this for a
Split the single-probe helper's implementation into multiple
functions and get locking and overallocation out of the way of
the surface setup. Simplifies later changes to the setup code.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
---
drivers/gpu/drm/drm_fb_helper.c |
The DRM helper drm_fb_build_fourcc_list() creates a list of color
formats for primary planes of the generic drivers. Simplify the helper:
- It used to mix and filter native and emulated formats as provided
by the driver. Now the only emulated format is XRGB, which is
required as fallbac
Fix the color-format selection of the single-probe helper. Go
through all user-specified values and test each for compatibility
with the driver. If none is supported, use the driver-provided
default. This guarantees that the console is always available in
any color format at least.
Until now, the
Drivers only emulate XRGB framebuffers. Remove all conversion
helpers that do not use XRGB as their source format. Also remove
some special cases for alpha formats in the blit helper.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
---
drivers/gpu/drm/drm_format_h
On Mon, 02 Jan 2023, Thomas Zimmermann wrote:
> Hi
>
> Am 22.12.22 um 23:21 schrieb Matthew Brost:
>> Hello,
>>
>> This is a submission for Xe, a new driver for Intel GPUs that supports both
>> integrated and discrete platforms starting with Tiger Lake (first platform
>> with
>> Intel Xe Archite
Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to
drm_panel") introduced an access to the bridge pointer in the
devm_drm_panel_bridge_add_typed() function.
However, due to the unusual ERR_PTR check when getting that pointer, the
pointer access is done even though the pointer might be
Hi Maxime,
Thank you for the patch.
On Mon, Jan 02, 2023 at 01:01:23PM +0100, Maxime Ripard wrote:
> Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to
> drm_panel") introduced an access to the bridge pointer in the
> devm_drm_panel_bridge_add_typed() function.
>
> However, due to t
On 02.01.2023 13:01, Maxime Ripard wrote:
Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to
drm_panel") introduced an access to the bridge pointer in the
devm_drm_panel_bridge_add_typed() function.
However, due to the unusual ERR_PTR check when getting that pointer, the
pointer
Currently, the array of BOs that are lookup up at the start of exec is being
instantiated as drm_gem_dma_object, which is not needed and makes it difficult
to use the drm_gem_objects_lookup() helper. Therefore, replace
drm_gem_dma_object for drm_gem_object and then replace obj lookup steps with
drm
As vc4_cl_lookup_bos() performs the same steps as drm_gem_objects_lookup(),
replace the open-coded implementation in vc4 to simply use the DRM function.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/vc4/vc4_gem.c | 43 ++-
1 file changed, 2 insertions(+), 41 dele
The array of BOs that are lookup up at the start of exec doesn't need
to be instantiated as drm_gem_dma_object, as it doesn't benefit
from its attributes. So, simplify the code by replacing the array of
drm_gem_dma_object for an array of drm_gem_object in the struct
vc4_exec_info.
Suggested-by: Me
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:38PM +0530, Rahul T R wrote:
> Convert cdns,dsi.txt binding to yaml format
>
> Signed-off-by: Rahul T R
> Reviewed-by: Rob Herring
> ---
> .../bindings/display/bridge/cdns,dsi.txt | 112 -
> .../bindings/display
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:39PM +0530, Rahul T R wrote:
> Add compatible to support dsi bridge on j721e
>
> Signed-off-by: Rahul T R
> Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
> ---
> .../bindings/display/bridge/cdns,dsi.yaml | 25 +++
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:40PM +0530, Rahul T R wrote:
> Move the cadence dsi bridge under drm/bridge/cadence
> directory, to prepare for adding j721e wrapper
> support
>
> Signed-off-by: Rahul T R
> Reviewed-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/br
Nirmoy, thanks for fixing it
Reviewed-by: Gwan-gyeong Mun
On 12/30/22 8:35 PM, Nirmoy Das wrote:
Switch to %zu for printing size_t which will
fix compilation warning for 32-bit build.
Reported-by: kernel test robot
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c |
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:41PM +0530, Rahul T R wrote:
> Create a header file for cdns dsi and move
> register offsets and structure to header,
> to prepare for adding j721e wrapper support
You don't have to wrap lines at 43 characters, you can go all the w
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:42PM +0530, Rahul T R wrote:
> Add support for wrapper settings for DSI bridge on
> j721e. Also enable DPI0
>
> --- ---
> | ---| |--- |
> | DSS | DPI2 |->| DP
Hello Ondřej,
On 1/2/23 11:57, Ondřej Jirman wrote:
[...]
>>
>> You tell me, it is your patch :) I just cherry-picked this from your tree:
>
> I have other patches to goodix driver that do power off the touch sensor chip
> during sleep, so that it doesn't consume excessinve amounts of power whe
On Mon, 26 Dec 2022 06:18, CK Hu (胡俊光) wrote:
>Hi, Guillaume:
>
>On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> On mt8195 the ddc i2c controller is part of the hdmi IP block and
>> thus has no
>> specific register range, power dom
Hello Ondřej,
On 1/2/23 11:59, Ondřej Jirman wrote:
[...]
>> Yes, because as you said were debug printks. Feel free to propose adding the
>> debug printks if you consider useful for normal usage and not just for devel
>> purposes.
>
> I already did, and used them do debug and fix the issues. Th
On Tue, 27 Dec 2022 20:40:03 +0300
Alexey Lukyachuk wrote:
> On Tue, 27 Dec 2022 11:39:25 -0500
> Rodrigo Vivi wrote:
>
> > On Sun, Dec 25, 2022 at 09:55:08PM +0300, Alexey Lukyanchuk wrote:
> > > dell wyse 3040 doesn't peform poweroff properly, but instead remains in
> > > turned power on sta
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fail, as vc4 accepts
to create a framebuffer with an invalid modifier. Therefore, check
for valid formats before creating framebuffers on vc4 and
On 02/01/2023 12:25, Marijn Suijten wrote:
On 2023-01-01 06:28:23, Dmitry Baryshkov wrote:
On 31/12/2022 23:50, Marijn Suijten wrote:
Since hardware revision 5.0.0 the TE configuration moved out of the
PINGPONG block into the INTF block. Writing these registers has no
effect, and is omitted do
Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver initialization to fail with
the messages b
Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver initialization to fail with
the messages b
[Cc: Back to dal...@libc.org]
Dear Linux folks,
Please ignore version 2.
Am 02.01.23 um 15:02 schrieb Paul Menzel:
[…]
---
Update Rich’s address.
I should have read the undelivered message better:
```
: host brightrain.aerifal.cx[216.12.86.13] said:
550-Message
blocked for policy r
Il 02/01/23 14:38, Guillaume Ranquet ha scritto:
On Mon, 26 Dec 2022 06:18, CK Hu (胡俊光) wrote:
Hi, Guillaume:
On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:
Add mt8195 SoC bindings for hdmi and hdmi-ddc
On mt8195 the ddc i2c controller is part of the hdmi IP block and
thus has n
which patch?
2023-01-02 17:24 GMT+08:00, Dmitry Osipenko :
> On 1/1/23 21:29, youling257 wrote:
>> Linux 6.2-rc1 has memory leak on amdgpu, git bisect bad commit is
>> "drm/scheduler: rework entity flush, kill and fini".
>> git bisect start
>> # status: waiting for both good and bad commits
>> # g
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fail, as vc4 accepts
to create a framebuffer with an invalid modifier. Therefore, check
for valid
On Fri, Dec 30, 2022 at 07:35:00PM +0100, Nirmoy Das wrote:
> Switch to %zu for printing size_t which will
> fix compilation warning for 32-bit build.
>
> Reported-by: kernel test robot
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
> ---
> drivers/gpu/drm/i915/gem/i915_gem_shmem.
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fail, as vc4 accepts
to create a framebuffer with
On 1/2/23 14:57, Paul Menzel wrote:
Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver init
On 1/2/23 2:21 AM, Johan Hovold wrote:
On Sun, Jan 01, 2023 at 10:58:42PM -0600, Steev Klimaszewski wrote:
On Sat, Dec 31, 2022 at 8:27 AM Abel Vesa wrote:
The actual name is R133NW4K-R0.
Fixes: 0f9fa5f58c784 ("drm/panel-edp: add IVO M133NW4J-R3 panel entry")
Signed-off-by: Abel Vesa
---
On 11/30/22 03:08, Rob Clark wrote:
> From: Rob Clark
>
> Add a sequence # for more easily matching up cmd/resp, and the # of free
> slots in the virtqueue to more easily see starvation issues.
>
> v2: Fix handling of string fields as well
>
> Signed-off-by: Rob Clark
> Reviewed-by: Dmitry Osi
On 11/9/22 12:19, Xiu Jianfeng wrote:
> The virtio_gpu_object_shmem_init() will alloc memory and save it in
> @ents, so when virtio_gpu_array_alloc() fails, this memory should be
> freed, this patch fixes it.
>
> Fixes: e7fef0923303 ("drm/virtio: Simplify error handling of
> virtio_gpu_object_cre
On 11/23/22 03:13, Dmitry Osipenko wrote:
> The drm_sched_entity_kill() is invoked twice by drm_sched_entity_destroy()
> while userspace process is exiting or being killed. First time it's invoked
> when sched entity is flushed and second time when entity is released. This
> causes a lockup within
On 1/2/23 17:17, youling 257 wrote:
> which patch?
https://patchwork.freedesktop.org/patch/512652/
I applied it to next-fixes
--
Best regards,
Dmitry
On Mon, 02 Jan 2023 15:14, AngeloGioacchino Del Regno
wrote:
>Il 02/01/23 14:38, Guillaume Ranquet ha scritto:
>> On Mon, 26 Dec 2022 06:18, CK Hu (胡俊光) wrote:
>>> Hi, Guillaume:
>>>
>>> On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:
Add mt8195 SoC bindings for hdmi and hdmi-ddc
On Mon, Jan 02, 2023 at 02:51:42PM +0100, Javier Martinez Canillas wrote:
> Hello Ondřej,
>
> [...]
>
> My goal was to have some initial support in mainline even if there could be
> some
> issues. IMO it is better to use upstream as a baseline and attempt to support
> the
> PPP incrementally.
>
On Mon, Jan 02, 2023 at 04:18:30PM +0530, Akhil P Oommen wrote:
> Remove the unused 'reset' interface which was supposed to help to ensure
> that cx gdsc has collapsed during gpu recovery. This is was not enabled
> so far due to missing gpucc driver support. Similar functionality using
> genpd fram
Hi
Am 02.01.23 um 15:29 schrieb Maíra Canal:
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fai
On 12/30/22 07:35, Hang Zhang wrote:
In do_fb_ioctl(), user specified "fb_info" can be freed in the callee
fbcon_get_con2fb_map_ioctl() -> set_con2fb_map() ->
con2fb_release_oldinfo(), this free operation is protected by
console_lock() in fbcon_set_con2fb_map_ioctl(), it also results in
the chang
On 1/2/23 12:21, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 15:29 schrieb Maíra Canal:
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@
Am 30.12.22 um 06:21 schrieb Mario Limonciello:
If SDMA microcode is not available during early init, the firmware
framebuffer will have already been released and the screen will
freeze.
Move the request from SDMA microcode into the IP discovery phase
so that if it's not available, IP discove
Hi
Am 02.01.23 um 16:39 schrieb Maíra Canal:
On 1/2/23 12:21, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 15:29 schrieb Maíra Canal:
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
fra
Struct dpu_encoder_virt_ops is used to provide several callbacks to the
phys_enc backends. However these ops are static and are not supposed to
change in the foreseeble future. Drop the indirection and call
corresponding functions directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc
assigned using dpu_encoder_as
On 02/01/2023 13:06, Marijn Suijten wrote:
On 2023-01-01 15:32:11, Dmitry Baryshkov wrote:
On 31/12/2022 23:50, Marijn Suijten wrote:
Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the
PINGPONG block and into the INTF. Implement the necessary callbacks in
the INTF block, a
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