On Tue, Oct 18, 2022 at 11:01:48AM +0530, Ankit Nautiyal wrote:
> This patch parses HFVSDB fields for VRR capabilities of an
> HDMI2.1 sink and stores the VRR caps in a new structure in
> drm_hdmi_info.
>
> Signed-off-by: Ankit Nautiyal
Makes sense to add this VRR info to drm_hdmi_info struct an
Den 18.10.2022 18.45, skrev Tommaso Merciai:
> Hi All,
> This series support for ilitek,ili9488 based displays like
> Waveshare-ResTouch-LCD-3.5 display. Tested on Waveshare-ResTouch-LCD-3.5
> connected to px30-evb via SPI.
There's a generic MIPI DBI SPI driver now that should work with all
th
On Tue, Oct 18, 2022 at 07:01:57PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_
On Tue, Oct 18, 2022 at 12:11:51PM -0400, Zack Rusin wrote:
> From: Zack Rusin
>
> v2: Thomas and Laurent noticed that in radeon_fb.c I forgot to set the
> info->apertures->ranges[0].base and Laurent noticed a neat little cleanup
> in the hisilicon driver as a result of the drm_mode_config::fb_ba
On 10/17/2022 4:44 PM, John Harrison wrote:
On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be l
> On Oct 18, 2022, at 4:20 PM, Andy Shevchenko
> wrote:
>
> ⚠ External Email
>
> On Tue, Oct 18, 2022 at 12:11:51PM -0400, Zack Rusin wrote:
>> From: Zack Rusin
>>
>> v2: Thomas and Laurent noticed that in radeon_fb.c I forgot to set the
>> info->apertures->ranges[0].base and Laurent notice
Hi Maxime,
W dniu 18.10.2022 o 10:31, Maxime Ripard pisze:
> Hi,
>
> On Sun, Oct 16, 2022 at 09:46:49PM +0200, Mateusz Kwiatkowski wrote:
>> @@ -308,14 +324,15 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[]
>> = {
>> };
>>
>> static inline const struct vc4_vec_tv_mode *
>> -vc4_vec
On Tue, Oct 18, 2022 at 08:26:17PM +, Zack Rusin wrote:
> > On Oct 18, 2022, at 4:20 PM, Andy Shevchenko
> > wrote:
> > On Tue, Oct 18, 2022 at 12:11:51PM -0400, Zack Rusin wrote:
> >> From: Zack Rusin
> >>
> >> v2: Thomas and Laurent noticed that in radeon_fb.c I forgot to set the
> >> inf
Hi
On Tue, Oct 18, 2022 at 9:06 PM Noralf Trønnes wrote:
>
>
>
> Den 18.10.2022 18.45, skrev Tommaso Merciai:
> > Hi All,
> > This series support for ilitek,ili9488 based displays like
> > Waveshare-ResTouch-LCD-3.5 display. Tested on Waveshare-ResTouch-LCD-3.5
> > connected to px30-evb via SPI.
Hi Maxime,
W dniu 18.10.2022 o 12:00, Maxime Ripard pisze:
> On Mon, Oct 17, 2022 at 12:31:31PM +0200, Noralf Trønnes wrote:
>> Den 16.10.2022 20.52, skrev Mateusz Kwiatkowski:
static int vc4_vec_connector_get_modes(struct drm_connector *connector)
{
- struct drm_connector_state
On Fri, 2022-10-14 at 16:30 -0700, Matt Roper wrote:
> The bspec was just updated with a correction to the forcewake domain
> required when accessing registers in the CCS engine ranges (0x1a000 -
> 0x1 and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
> the RENDER domain, not the GT
Waitboost (when SLPC is enabled) results in a H2G message. This can result
in thousands of messages during a stress test and fill up an already full
CTB. There is no need to request for RP0 if GuC is already requesting the
same.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_r
On 2022-10-18 11:37, Alex Deucher wrote:
> On Tue, Oct 18, 2022 at 11:11 AM Christian König
> wrote:
>>
>> Gentle ping to others to get this reviewed.
>>
>> Alex, this is fixing the TLB flush errors and I think we need to get it
>> into -fixes ASAP.
>>
>> Christian.
>>
>> Am 14.10.22 um 10:15 schr
Den 18.10.2022 23.28, skrev Michael Nazzareno Trimarchi:
> Hi
>
> On Tue, Oct 18, 2022 at 9:06 PM Noralf Trønnes wrote:
>>
>>
>>
>> Den 18.10.2022 18.45, skrev Tommaso Merciai:
>>> Hi All,
>>> This series support for ilitek,ili9488 based displays like
>>> Waveshare-ResTouch-LCD-3.5 display. T
On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
What is GCD?
of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB
Hi,
This is the v13 series to introduce i.MX8qm/qxp Display Processing Unit(DPU)
DRM support.
DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer. Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of bli
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v4->v13:
* No change.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Use new dt
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v7->v13:
* No change.
v6->v7:
* Add Rob's R-b tag back.
v5->v6:
* Use graph schema. So, drop Rob's R-b tag as review is needed.
v4->v5:
* No change.
v3->v4:
* Improve compat
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v10->v13:
* No change.
v9->v10:
* Add Rob's R-b tag.
v8->v9:
* Reference 'interrupts-extended' schema instead of 'interrupts' to require
an additional interrupt(r_r
Artificially use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.
Acked-by: Daniel Vetter
Signed-off-by: Liu Ying
---
v6->v13:
* No change.
v5->v6:
* Fix commit message typo - s/Artifically/Artificially/
v4->v5:
* N
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Acked-by: Laurentiu Palcu
Signed-off-by: Liu Ying
---
v11->v13:
* No change.
v10->v11:
* Rebase upon v6.0-rc1.
v9->v10:
* Add Laurentiu's A-b tag.
v1->v9:
* No change.
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
di
/drm-tip linus/master v6.1-rc1 next-
> 20221018]
[...]
> All errors (new ones prefixed by >>):
>
>drivers/gpu/drm/imx/dpu/dpu-drv.c: In function 'dpu_drm_bind':
> > > drivers/gpu/drm/imx/dpu/dpu-drv.c:67:12: error: 'struct
> > > d
On Tue, Oct 18, 2022 at 04:28:07PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not
From: Zack Rusin
v4: Fix issue spotted by the kernel test robot
The fb_base in struct drm_mode_config has been unused for a long time.
Some drivers set it and some don't leading to a very confusing state
where the variable can't be relied upon, because there's no indication
as to which driver se
On Tue, 2022-10-18 at 23:59 +0300, Andy Shevchenko wrote:
> ⚠ External Email
>
> On Tue, Oct 18, 2022 at 08:26:17PM +, Zack Rusin wrote:
> > > On Oct 18, 2022, at 4:20 PM, Andy Shevchenko
> > > wrote:
> > > On Tue, Oct 18, 2022 at 12:11:51PM -0400, Zack Rusin wrote:
> > > > From: Zack Rusin
From: Xinlei Lee
The difference between MT8186 and other ICs is that when modifying the
output format, we need to modify the mmsys_base+0x400 register to take
effect.
So when setting the dpi output format, we need to call mmsys_func to set
it to MT8186 synchronously.
Adding mmsys all the settings
From: Xinlei Lee
Dpi output needs to adjust the output format to dual edge for MT8186.
Co-developed-by: Jitao Shi
Signed-off-by: Jitao Shi
Signed-off-by: Xinlei Lee
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/dri
From: Xinlei Lee
Base on the branch of linus/master v6.1 rc1.
Change since v11:
1. Rebase on v6.1-rc1. Change nothing.
Change since v10:
1. Modify patch title and add review tag.
Change since v9:
1. Modify the location of the mmsys_dev member variable.
Change since v8:
1. Modified the title a
From: Xinlei Lee
Add the compatible because use edge_cfg_in_mmsys in mt8186.
Signed-off-by: Xinlei Lee
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
2 files ch
From: Xinlei Lee
Modify dpi power on/off sequence so that the first gpio operation will take
effect.
Fixes: 6bd4763fd532 ("drm/mediatek: set dpi pin mode to gpio low to avoid
leakage current")
Signed-off-by: Xinlei Lee
---
change note:
v1: Rebase on linus/master v6.1-rc1. Change nothing.
Be
On 2022-10-18 04:05, Yang Yingliang wrote:
> If kset_register() fails, the refcount of device is not 0, the name allocated
> in dev_set_name() is leaked. Fix this by calling kset_put(), so that it will
> be freed in callback function kobject_cleanup().
>
Good catch, but looking at the code it see
On 2022-10-18 23:37, Luben Tuikov wrote:
> On 2022-10-18 04:05, Yang Yingliang wrote:
>> If kset_register() fails, the refcount of device is not 0, the name allocated
>> in dev_set_name() is leaked. Fix this by calling kset_put(), so that it will
>> be freed in callback function kobject_cleanup().
On Tue, Oct 18, 2022 at 05:44:38PM -0700, John Harrison wrote:
> On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
> > From: Aravind Iddamsetty
> >
...
> > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> > b/drivers/gpu/drm/i915/gt/intel_wopcm.c
> > similarity index 86%
> > rename from driver
On Tue, Oct 18, 2022 at 06:30:58PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not hav
On Tue, Oct 18, 2022 at 01:20:06PM -0700, Niranjana Vishwanathapura wrote:
On Tue, Oct 18, 2022 at 07:01:57PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure req
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency types
From: Don Hiatt
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 resi
From: Badal Nilawar
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor
From: Badal Nilawar
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing fo
On Mon, 17 Oct 2022 01:27:35 -0700, Jani Nikula wrote:
Hi Jani,
Thanks for reviewing, great suggestions overall. I have taken care of most
of them in series version v6. Please see below.
> On Fri, 14 Oct 2022, Ashutosh Dixit wrote:
> > @@ -811,9 +809,23 @@ u64 intel_rc6_residency_ns(struct inte
Register content protect property in drm so that bridge can update
the property from userspace request.
HDCP property needs to be created after the connecter is initialized
and before the connector is registered. Since some bridge may be
attached without connector, register this property in drm dr
On Wed, Oct 19, 2022 at 2:26 AM Sean Paul wrote:
>
> On Mon, Oct 17, 2022 at 9:49 AM Hsin-Yi Wang wrote:
> >
> > On Wed, Oct 12, 2022 at 12:20 PM Hsin-Yi Wang wrote:
> > >
> > > Some bridges are able to update HDCP status from userspace request if
> > > they support HDCP.
> > >
> > > HDCP proper
The symbol is not used outside of the file, so mark it static.
Fixes the following warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mmhubbub.c:214:28:
warning: symbol 'dcn32_mmhubbub_funcs' was
not declared. Should it be static?
Signed-off-by: ruanjinjie
---
drivers/gpu/drm/amd/di
The symbol is not used outside of the file, so mark it static.
Fixes the following warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:985:24: warning:
symbol 'dcn32_mpc_funcs' was not declared. Should it be static?
Signed-off-by: ruanjinjie
---
drivers/gpu/drm/amd/display/dc/d
Hi,
On 2022/10/19 11:37, Luben Tuikov wrote:
On 2022-10-18 04:05, Yang Yingliang wrote:
If kset_register() fails, the refcount of device is not 0, the name allocated
in dev_set_name() is leaked. Fix this by calling kset_put(), so that it will
be freed in callback function kobject_cleanup().
G
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