Am 05.09.22 um 18:35 schrieb Arvind Yadav:
Here's on debug enabling software signaling for the stub fence
which is always signaled. This fence should enable software
signaling otherwise the AMD GPU scheduler will cause a GPU reset
due to a GPU scheduler cleanup activity timeout.
Signed-off-by
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
Here's on debug enabling software signaling for selftest.
Please drop all the #ifdefs, apart from that looks pretty good to me.
Christian.
Signed-off-by: Arvind Yadav
---
Changes in v1 :
1- Addressing Christian's comment to remove unnecessary cal
From: ye xingchen
Return the value vmw_cotable_notify() directly instead of storing it in
another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: ye xingchen
---
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/driv
From: Thomas Zimmermann
Restore the display mode whne resuming from suspend. Currently, the
display remains dark.
On resume, the CRTC's mode does not change, but the 'active' flag
changes to 'true'. Taking this into account when considering a mode
switch restores the display mode.
The bug is re
From: Thomas Zimmermann
Implement the reset_resume callback of struct usb_driver. Set the
standard channel when called.
Signed-off-by: Thomas Zimmermann
Signed-off-by: Takashi Iwai
---
drivers/gpu/drm/udl/udl_drv.c | 11 +++
drivers/gpu/drm/udl/udl_drv.h | 1 +
drivers/gpu/drm/udl/
Hi,
this is a revised patch set for cleaning up and fixes for UDL driver.
It covers the PM problems, regressions in the previous patch set,
fixes for the stalls on some systems, as well as more hardening.
Takashi
===
v1->v2: cleanups as suggested by Thomas
- Drop numurbs parameter patch
- Clea
This reverts the recent fix commit
e25d5954264d ("drm/udl: Kill pending URBs at suspend and disconnect")
as it turned out to lead to potential hangup at a disconnection, and
it doesn't help much for suspend/resume problem, either.
Acked-by: Thomas Zimmermann
Signed-off-by: Takashi Iwai
---
dr
From: Thomas Zimmermann
Call drm_plane_enable_fb_damage_clips() and give userspace a chance
of minimizing the updated display area.
Signed-off-by: Thomas Zimmermann
Signed-off-by: Takashi Iwai
---
drivers/gpu/drm/udl/udl_modeset.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gp
It's better to perform the sync at the very last of the suspend
instead of the pipe-disable function, so that we can catch all pending
URBs (if any).
While we're at it, drop the error code from udl_sync_pending_urb()
since we basically ignore it; instead, give a clear error message
indicating a pr
It seems that the current size (4) for the URB list is too small on
some devices, and it resulted in the occasional stalls. Increase the
default URB list size to 20 for working around it.
Acked-by: Thomas Zimmermann
Signed-off-by: Takashi Iwai
---
drivers/gpu/drm/udl/udl_main.c | 2 +-
1 file
udl_alloc_urb_list() retires the allocation if there is no enough room
left, and it reinitializes the stuff unnecessarily such as the linked
list head and the waitqueue, which could be harmful. Those should be
outside the retry loop.
Acked-by: Thomas Zimmermann
Signed-off-by: Takashi Iwai
---
The alignment of damaged area was needed for the original udlfb driver
that tried to trim the superfluous copies between front and backend
buffers and handle data in long int. It's not the case for udl DRM
driver, hence we can omit the whole unneeded alignment, as well as the
dead code.
Signed-of
In the current design, udl_get_urb() may be called asynchronously
during the driver freeing its URL list via udl_free_urb_list().
The problem is that the sync is determined by comparing the urbs.count
and urbs.available fields, while we clear urbs.count field only once
after udl_free_urb_list() fin
The driver may receive -EPROTO at the URB completion when the device
gets disconnected, and it's a normal situation. Suppress the error
print for that, too.
Signed-off-by: Takashi Iwai
---
drivers/gpu/drm/udl/udl_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/udl/udl
A couple of error handlings forgot to process the URB completion.
Those are both with WARN_ON() so should be visible, but we must fix
them in anyway.
Fixes: 7350b2a3fbc6 ("drm/udl: Replace BUG_ON() with WARN_ON()")
Acked-by: Thomas Zimmermann
Signed-off-by: Takashi Iwai
---
drivers/gpu/drm/udl/
Hi Biju,
On Tue, 6 Sept 2022 at 08:42, Biju Das wrote:
>
> Hi Clement,
>
> >
> > Hi,
> >
> > On Mon, 5 Sept 2022 at 20:17, Biju Das
> > wrote:
> > >
> > > Hi,
> > >
> > > Thanks for the patch.
> > >
> > > > Subject: [PATCH v3 4/5] drm/panfrost: devfreq: set opp to the
> > > > recommended one to
Hi Clement,
> Subject: Re: [PATCH v3 4/5] drm/panfrost: devfreq: set opp to the
> recommended one to configure and enable regulator
>
> Hi Biju,
>
> On Tue, 6 Sept 2022 at 08:42, Biju Das
> wrote:
> >
> > Hi Clement,
> >
> > >
> > > Hi,
> > >
> > > On Mon, 5 Sept 2022 at 20:17, Biju Das
> > >
Hi,
On Tue, 6 Sept 2022 at 10:06, Biju Das wrote:
>
> Hi Clement,
>
> > Subject: Re: [PATCH v3 4/5] drm/panfrost: devfreq: set opp to the
> > recommended one to configure and enable regulator
> >
> > Hi Biju,
> >
> > On Tue, 6 Sept 2022 at 08:42, Biju Das
> > wrote:
> > >
> > > Hi Clement,
> > >
On Tue, Sep 06, 2022 at 08:37:00AM +0700, Bagas Sanjaya wrote:
> On 9/6/22 01:47, Michał Winiarski wrote:
> > References: commit 6fc3a8636a7b ("kunit: tool: Enable virtio/PCI by default
> > on UML")
>
> Use Fixes: tag for bugfix patches instead.
Can documentation update (when the referenced patc
Hi Doug,
Am Montag, dem 05.09.2022 um 14:05 -0700 schrieb Doug Brown:
> Hi Christian,
>
> On 9/3/2022 4:49 AM, Christian Gmeiner wrote:
>
> > I had a quick look at what vivantes kernel driver did. It uses a per
> > gpu instance variable powerBaseAddress
> > that gets set accordingly. I am not su
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
The core DMA-buf framework needs to enable signaling
before the fence is signaled. The core DMA-buf framework
can forget to enable signaling before the fence is signaled.
This sentence is a bit confusing. I'm not a native speaker of English
either, bu
[Why]
Ghost BO is released with non-empty bulk move object. There is a
warning trace:
WARNING: CPU: 19 PID: 1582 at ttm/ttm_bo.c:366 ttm_bo_release+0x2e1/0x2f0
[amdttm]
Call Trace:
amddma_resv_reserve_fences+0x10d/0x1f0 [amdkcl]
amdttm_bo_put+0x28/0x30 [amdttm]
amdttm_bo_move_accel_cleanup+0
Am 06.09.22 um 10:46 schrieb ZhenGuo Yin:
[Why]
Ghost BO is released with non-empty bulk move object. There is a
warning trace:
WARNING: CPU: 19 PID: 1582 at ttm/ttm_bo.c:366 ttm_bo_release+0x2e1/0x2f0
[amdttm]
Call Trace:
amddma_resv_reserve_fences+0x10d/0x1f0 [amdkcl]
amdttm_bo_put+0x28/
Michał Winiarski writes:
> On Tue, Sep 06, 2022 at 08:37:00AM +0700, Bagas Sanjaya wrote:
>> On 9/6/22 01:47, Michał Winiarski wrote:
>> > References: commit 6fc3a8636a7b ("kunit: tool: Enable virtio/PCI by
>> > default on UML")
>>
>> Use Fixes: tag for bugfix patches instead.
>
> Can documenta
On 03-09-2022 05:02, Matt Roper wrote:
> Xe_LPM+ platforms have "standalone media." I.e., the media unit is
> designed as an additional GT with its own engine list, GuC, forcewake,
> etc. Let's allow platforms to include media GTs in their device info.
>
> v2:
> - Simplify GSI register handl
Hi Dan,
On 01/09/2022 16:38, Dan Carpenter wrote:
This code uses struct_size() but it stores the result in an int so the
integer overflow checks are not effective. Record the types as size_t
to prevent the size from being truncated.
Fixes: bf3c50837506 ("drm/i915/query: Use struct_size() hel
Il 06/09/22 10:44, nathan.lu ha scritto:
From: Nathan Lu
modify VDOSYS0 mmsys device tree Documentations for MT8188.
Signed-off-by: Nathan Lu
Reviewed-by: AngeloGioacchino Del Regno
Il 06/09/22 10:44, nathan.lu ha scritto:
From: Nathan Lu
modify VDOSYS0 mutex device tree Documentations for MT8188.
Signed-off-by: Nathan Lu
Reviewed-by: AngeloGioacchino Del Regno
Il 06/09/22 10:44, nathan.lu ha scritto:
From: Nathan Lu
add mtk-mutex support for mt8188 vdosys0.
Signed-off-by: amy zhang
Signed-off-by: Nathan Lu
Reviewed-by: AngeloGioacchino Del Regno
On 06/09/2022 09:39, Christian König wrote:
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
The core DMA-buf framework needs to enable signaling
before the fence is signaled. The core DMA-buf framework
can forget to enable signaling before the fence is signaled.
This sentence is a bit confusing.
On 2022-09-05 15:37, Hans de Goede wrote:
> The gma500 page-flip code kinda assume that userspace never queues more
> then 1 vblank event. So basically it assume that userspace does:
>
> - page-flip
> - wait for vblank event
> - render
> - page-flip
> - etc.
>
> In the case where userspace would
Am 06.09.22 um 11:51 schrieb Christoph Hellwig:
+{
+ struct vfio_pci_dma_buf *priv = dmabuf->priv;
+ int rc;
+
+ rc = pci_p2pdma_distance_many(priv->vdev->pdev, &attachment->dev, 1,
+ true);
This should just use pci_p2pdma_distance.
+
Am 06.09.22 um 12:20 schrieb Tvrtko Ursulin:
On 06/09/2022 09:39, Christian König wrote:
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
The core DMA-buf framework needs to enable signaling
before the fence is signaled. The core DMA-buf framework
can forget to enable signaling before the fence is s
On 03-09-2022 05:02, Matt Roper wrote:
> GT non-engine registers (referred to as "GSI" registers by the spec)
> have the same relative offsets on standalone media as they do on the
> primary GT, just with an additional "GSI offset" added to their MMIO
> address. If we store this GSI offset in t
Em Fri, 19 Aug 2022 05:38:28 +0300
Laurent Pinchart escreveu:
> Mauro, would you be fine with this patch going through the DRM tree for
> v6.1 ? I don't foresee any risk of conflict with other changes to the
> VSP driver scheduled for the next kernel version. If that's fine with
> you, could you
Hi Jingyu,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on e47eb90a0a9ae20b82635b9b99a8d0979b757ad8]
url:
https://github.com/intel-lab-lkp/linux/commits/Jingyu-Wang/drm-amdgpu-cleanup-coding-style-in-amdgpu_kms-c/20220906-104802
base
On 06/09/2022 11:43, Christian König wrote:
Am 06.09.22 um 12:20 schrieb Tvrtko Ursulin:
On 06/09/2022 09:39, Christian König wrote:
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
The core DMA-buf framework needs to enable signaling
before the fence is signaled. The core DMA-buf framework
can f
Am 06.09.22 um 13:21 schrieb Tvrtko Ursulin:
On 06/09/2022 11:43, Christian König wrote:
Am 06.09.22 um 12:20 schrieb Tvrtko Ursulin:
On 06/09/2022 09:39, Christian König wrote:
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
The core DMA-buf framework needs to enable signaling
before the fence
Hi Greg,
Alex has explained how we figured out the patch. We did analyze the
code and found it possible to reach the vulnerability code. But we
have no physical device in hand to test the driver. So we'd like to
discuss with developers to see if the issue exists or not.
Best regards,
Zheng Wang.
On 06/09/2022 12:21, Tvrtko Ursulin wrote:
On 06/09/2022 11:43, Christian König wrote:
Am 06.09.22 um 12:20 schrieb Tvrtko Ursulin:
On 06/09/2022 09:39, Christian König wrote:
Am 05.09.22 um 18:35 schrieb Arvind Yadav:
The core DMA-buf framework needs to enable signaling
before the fence
On 2022-09-04 20:15, Jingyu Wang wrote:
[...]
@@ -565,8 +566,8 @@ module_param_named(timeout_period,
amdgpu_watchdog_timer.period, uint, 0644);
*/
#ifdef CONFIG_DRM_AMDGPU_SI
-#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
-int amdgpu_si_support = 0;
+#if IS_ENABLED
On Tue, Sep 06, 2022 at 12:38:44PM +0200, Christian König wrote:
> Am 06.09.22 um 11:51 schrieb Christoph Hellwig:
> > > +{
> > > + struct vfio_pci_dma_buf *priv = dmabuf->priv;
> > > + int rc;
> > > +
> > > + rc = pci_p2pdma_distance_many(priv->vdev->pdev, &attachment->dev, 1,
> > > +
On 2022-09-04 05:13, Chris Ruehl wrote:
Hi,
Something you might have a head up for it,
have a mediapipe application for POSE which use the T860 GPU for the
calculation
but the kernel driver report error (js fault) - I see one or 2
calculation frames on the mat-picture output only before
the
On Tue, 6 Sept 2022 at 04:58, Xin Ji wrote:
>
> On Mon, Sep 05, 2022 at 06:48:06PM +0200, Robert Foss wrote:
> > Hi Xin,
> >
> > On Sat, 3 Sept 2022 at 15:09, Xin Ji wrote:
> > >
> > > Some panels trigger HPD irq due to noise, the HPD debounce
> > > may be 1.8ms, exceeding the default irq detect
On 01.09.2022 23:03, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> contex
On Mon, Sep 05, 2022 at 03:07:48PM -0700, Guenter Roeck wrote:
> On 9/5/22 12:55, Andy Shevchenko wrote:
> > On Mon, Sep 5, 2022 at 10:51 PM Dmitry Torokhov
> > wrote:
> > > On Mon, Sep 05, 2022 at 10:41:40PM +0300, Andy Shevchenko wrote:
> > > > On Mon, Sep 5, 2022 at 10:40 PM Dmitry Torokhov
> >
On Tue, Sep 6, 2022 at 2:48 PM Jason Gunthorpe wrote:
>
> On Tue, Sep 06, 2022 at 12:38:44PM +0200, Christian König wrote:
> > Am 06.09.22 um 11:51 schrieb Christoph Hellwig:
> > > > +{
> > > > + struct vfio_pci_dma_buf *priv = dmabuf->priv;
> > > > + int rc;
> > > > +
> > > > + rc = pci_p2pdma_di
On Mon, Sep 5, 2022 at 3:37 PM Hans de Goede wrote:
>
> gma_crtc_page_flip() was holding the event_lock spinlock while calling
> crtc_funcs->mode_set_base() which takes ww_mutex.
>
> The only reason to hold event_lock is to clear gma_crtc->page_flip_event
> on mode_set_base() errors.
>
> Instead u
>-Original Message-
>From: dri-devel On Behalf Of
>Matt Roper
>Sent: Friday, September 2, 2022 7:33 PM
>To: intel-...@lists.freedesktop.org
>Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
>
>Subject: [PATCH v2 01/12] drm/i915: Move locking and unclaimed check into
>mmio_debug_{
Am 2022-09-05 um 04:38 schrieb Jingyu Wang:
Fix everything checkpatch.pl complained about in amdgpu_amdkfd_gpuvm.c
Signed-off-by: Jingyu Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
From: Mikko Perttunen
Add support for the Tegra234 version of NVDEC to the NVDEC driver.
This version sports a RISC-V controller and requires a few additional
clocks. After firmware has been loaded, the behavior is, however,
backwards compatible.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/
From: Mikko Perttunen
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/Makefile | 3 +-
drivers/gpu/drm/tegra/riscv.c | 106 +
drivers/gpu/drm/tegra/riscv.h |
From: Mikko Perttunen
NVDEC on Tegra234 requires multiple clocks. Add support for that.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/nvdec.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers
From: Mikko Perttunen
Add entries for NVDEC to the Tegra234 SID table.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..d6b4614f968f 100644
--- a
From: Mikko Perttunen
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not a
From: Mikko Perttunen
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for the internal microcontroller, which brings along
a change in how the engine is booted. Otherwise it is backwards
compatible with earli
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we can determine by checking the
starting address of the carveout. As such, add an MC API to quer
From: Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.
Signed-off-by: Mikko Perttunen
---
include/dt-bindings/clock/tegra234-clock.h | 4
include/dt-bindings/memory/tegra234-mc.h | 3 +++
include/dt-bindings/power/tegra234
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the memo
64 DRM device nodes is not enough for everyone.
Upgrade it to ~512K (which definitely is more than enough).
To allow testing userspace support for >64 devices, add additional DRM
modparam (skip_legacy_minors) which causes DRM to skip allocating minors
in 0-192 range.
Additionally - one minor tweak
Having a limit of 64 DRM devices is not good enough for modern world
where we have multi-GPU servers, SR-IOV virtual functions and virtual
devices used for testing.
Let's utilize full minor range for DRM devices.
To avoid regressing the existing userspace, we're still maintaining the
numbering sche
While there is support for >64 DRM devices on kernel side, existing
userspace may still have some hardcoded assumptions and it's possible
that it will require changes to be able to use more than 64 devices.
Add a modparam to simplify testing and development of >64 devices
support on userspace side
Operating on drm minor is not done in IRQ context, which means that we
could safely downgrade to regular non-irq spinlock.
But we can also go further and drop the idr_preload tricks by just using
a mutex.
Signed-off-by: Michał Winiarski
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_drv.c |
Using might_alloc() lets us catch problems in a deterministic manner,
even if we end up not allocating anything.
Signed-off-by: Michał Winiarski
---
lib/radix-tree.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/radix-tree.c b/lib/radix-tree.c
index 3c78e1e8b2ad..787ab01001de 100644
On Tue, Sep 06, 2022 at 04:01:13PM +0200, Michał Winiarski wrote:
> 64 DRM device nodes is not enough for everyone.
> Upgrade it to ~512K (which definitely is more than enough).
>
> To allow testing userspace support for >64 devices, add additional DRM
> modparam (skip_legacy_minors) which causes
On Mon, Sep 05, 2022 at 06:32:56PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Document the "framebuffer" compatible string for reserved memory nodes
> to annotate reserved memory regions used for framebuffer carveouts.
>
> Signed-off-by: Thierry Reding
> ---
> .../bindings/reserve
VGA_IS1_RC is the color mode register (VGA_IS1_RM the one for monochrome
mode, note C vs. M at the end). So when using VGA_IS1_RC make sure the
vga device is actually in color mode and set the corresponding bit in the
misc register.
Reproducible when booting VMs in UEFI mode with some edk2 versio
On Mon, 05 Sep 2022, Stanislav Lisovskiy wrote:
> Adding DP DSC register definitions, we might need for further
> DSC implementation, supporting MST and DP branch pass-through mode.
>
> v2: - Fixed checkpatch comment warning
> v3: - Removed function which is not yet used(Jani Nikula)
>
> Reviewed-
On Tue, 06 Sep 2022, Jani Nikula wrote:
> On Mon, 05 Sep 2022, Stanislav Lisovskiy
> wrote:
>> Adding DP DSC register definitions, we might need for further
>> DSC implementation, supporting MST and DP branch pass-through mode.
>>
>> v2: - Fixed checkpatch comment warning
>> v3: - Removed functi
On 2022-09-02 09:10, Greg Kroah-Hartman wrote:
On Fri, Sep 02, 2022 at 03:01:05PM +0200, Greg Kroah-Hartman wrote:
When calling debugfs_lookup() the result must have dput() called on it,
otherwise the memory will leak over time. Fix this up by properly
calling dput().
Cc: Harry Wentland
Cc
On Tue, Sep 06, 2022 at 10:52:28AM -0400, Rodrigo Siqueira Jordao wrote:
>
>
> On 2022-09-02 09:10, Greg Kroah-Hartman wrote:
> > On Fri, Sep 02, 2022 at 03:01:05PM +0200, Greg Kroah-Hartman wrote:
> > > When calling debugfs_lookup() the result must have dput() called on it,
> > > otherwise the m
On Mon, Sep 5, 2022 at 2:29 AM Jingyu Wang wrote:
>
> Fix everything checkpatch.pl complained about in amdgpu_atpx_handler.c
>
> Signed-off-by: Jingyu Wang
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 27 +++
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff
On Tue, Sep 06, 2022 at 08:53:25AM +0200, Maarten Lankhorst wrote:
> Hi Dave, Daniel,
>
> A pull request prepared in Germany and Denmark, but sent from Sweden after
> fighting with gpg on an infamous bridge.
>
> My computer's somewhere in my trunk so I just copied someone else's pull
> request
Hi Mikko,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on clk/clk-next krzk-mem-ctrl/for-next pza/reset/next
linus/master v6.0-rc4 next-20220906]
[If your patch is applied to the wrong git tree, kindly drop us a note
Hi,
This is a refresh of previous patches sent to enable GPU Devfreq on H6
Beelink GS1 but that wasn't stable at that time[0].
With the recent fix on GPU PLL from Roman Stratiienko I have retested
and everything seems stable and works as expected[1].
Regards,
Clement
0:
https://lore.kernel.org
Enabling panfrost GPU OPP with dynamic regulator will make OPP
responsible to enable and configure it.
Unfortunatly OPP configure and enable the regulator when an OPP
is asked to be set, which is not the case during
panfrost_devfreq_init().
This leave the regulator unconfigured and if no GPU load
Add an Operating Performance Points table for the GPU to
enable Dynamic Voltage & Frequency Scaling on the H6.
The voltage range is set with minimal voltage set to the target
and the maximal voltage set to 1.2V. This allow DVFS framework to
work properly on board with fixed regulator.
Signed-off-
Add a simple cooling map for the GPU.
This cooling map come from the vendor kernel 4.9 with a
2°C hysteresis added.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 51 +++-
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/
Devfreq cooling device framework is used in Panfrost
to throttle GPU in order to regulate its temperature.
Enable this driver for ARM64 SoC.
Signed-off-by: Clément Péron
Acked-by: Jernej Skrabec
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/con
Enable GPU OPP table for Beelink GS1.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
in
On Mon, Sep 5, 2022 at 3:40 AM Jingyu Wang wrote:
>
> Fix everything checkpatch.pl complained about in amdgpu_fence.c,
> modified use "} else {", sent it again, thx.
>
> Signed-off-by: Jingyu Wang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 15 +--
> 1 file changed, 9 inserti
On 2022-09-06 11:06, Greg Kroah-Hartman wrote:
On Tue, Sep 06, 2022 at 10:52:28AM -0400, Rodrigo Siqueira Jordao wrote:
On 2022-09-02 09:10, Greg Kroah-Hartman wrote:
On Fri, Sep 02, 2022 at 03:01:05PM +0200, Greg Kroah-Hartman wrote:
When calling debugfs_lookup() the result must have dpu
On Mon, 05 Sep 2022, Stanislav Lisovskiy wrote:
> Currently we have only DSC support for DP SST.
As discussed elsewhere, the patches were modified while applying to
resolve conflicts, leading to further conflicts in drm-tip rebuild, and
eventually drm-tip build breakage. They would've created fur
On Tue, 06 Sep 2022, Jani Nikula wrote:
> On Mon, 05 Sep 2022, Stanislav Lisovskiy
> wrote:
>> Adding DP DSC register definitions, we might need for further
>> DSC implementation, supporting MST and DP branch pass-through mode.
>>
>> v2: - Fixed checkpatch comment warning
>> v3: - Removed functi
On 2022-09-02 03:54, cgel@gmail.com wrote:
From: zhang songyi
Return the enable_link_dp() directly instead of storing it in another
redundant variable.
Reported-by: Zeal Robot
Signed-off-by: zhang songyi
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
1 file changed,
On Tue, Sep 06, 2022 at 11:39:44AM -0400, Rodrigo Siqueira Jordao wrote:
>
>
> On 2022-09-06 11:06, Greg Kroah-Hartman wrote:
> > On Tue, Sep 06, 2022 at 10:52:28AM -0400, Rodrigo Siqueira Jordao wrote:
> > >
> > >
> > > On 2022-09-02 09:10, Greg Kroah-Hartman wrote:
> > > > On Fri, Sep 02, 202
Hi All,
The builds of next-20220906 fails for mips, xtensa and arm allmodconfig.
The errors in mips and xtensa are:
ERROR: modpost: "__divdi3" [drivers/gpu/drm/vkms/vkms.ko] undefined!
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/vkms/vkms.ko] undefined!
The error in arm
On Tue, Sep 06, 2022 at 03:21:25PM +0100, Matthew Wilcox wrote:
> On Tue, Sep 06, 2022 at 04:01:13PM +0200, Michał Winiarski wrote:
> > 64 DRM device nodes is not enough for everyone.
> > Upgrade it to ~512K (which definitely is more than enough).
> >
> > To allow testing userspace support for >64
On 05/09/2022 10:34, Tvrtko Ursulin wrote:
On 01/09/2022 19:38, Niranjana Vishwanathapura wrote:
So far, different views (normal, partial, rotated and remapped)
into the same object are only supported for GGTT mappings.
But with the upcoming VM_BIND feature, PPGTT will also use the
partial vi
https://bugzilla.kernel.org/show_bug.cgi?id=216455
Bug ID: 216455
Summary: PCI AER error caused by LTR enablement on amdgpu with
LTR disabled on video card PCIe bridge
Product: Drivers
Version: 2.5
Kernel Version: 5.19.6
https://bugzilla.kernel.org/show_bug.cgi?id=216455
--- Comment #1 from Gustaw Smolarczyk (wielkie...@gmail.com) ---
Created attachment 301754
--> https://bugzilla.kernel.org/attachment.cgi?id=301754&action=edit
lspci -vvnn on vega10 system
--
You may reply to this email to add a comment.
You
https://bugzilla.kernel.org/show_bug.cgi?id=216455
--- Comment #2 from Gustaw Smolarczyk (wielkie...@gmail.com) ---
Hardware:
CPU: Ryzen Threadripper 1950X
MB: Asrock X399 Taichi
GPU: Radeon Vega 64 [1002:687f]
--
You may reply to this email to add a comment.
You are receiving this mail because
On Thu, Sep 01, 2022 at 09:55:08AM +0200, Christian König wrote:
> Am 01.09.22 um 01:12 schrieb Jason Gunthorpe:
> > Used to increment the refcount of the dma buf's struct file, only if the
> > refcount is not zero. Useful to allow the struct file's lifetime to
> > control the lifetime of the dmabu
On Tue, Sep 06, 2022 at 06:43:22PM +0300, Jani Nikula wrote:
> On Tue, 06 Sep 2022, Jani Nikula wrote:
> > On Mon, 05 Sep 2022, Stanislav Lisovskiy
> > wrote:
> >> Adding DP DSC register definitions, we might need for further
> >> DSC implementation, supporting MST and DP branch pass-through mod
Hi,
On 9/6/22 14:50, Patrik Jakobsson wrote:
> On Mon, Sep 5, 2022 at 3:37 PM Hans de Goede wrote:
>>
>> gma_crtc_page_flip() was holding the event_lock spinlock while calling
>> crtc_funcs->mode_set_base() which takes ww_mutex.
>>
>> The only reason to hold event_lock is to clear gma_crtc->page_
Hi Michel,
On 9/6/22 12:25, Michel Dänzer wrote:
> On 2022-09-05 15:37, Hans de Goede wrote:
>> The gma500 page-flip code kinda assume that userspace never queues more
>> then 1 vblank event. So basically it assume that userspace does:
>>
>> - page-flip
>> - wait for vblank event
>> - render
>> -
On Sat, 6 Aug 2022 at 18:34, Markuss Broks wrote:
>
> Make the EFI earlycon driver be suitable for any linear framebuffers.
> This should be helpful for early porting of boards with no other means of
> output, like smartphones/tablets. There seems to be an issue with
> early_ioremap
> function on
On Tue, Sep 06, 2022 at 06:39:14AM -0700, Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel On Behalf Of
> >Matt Roper
> >Sent: Friday, September 2, 2022 7:33 PM
> >To: intel-...@lists.freedesktop.org
> >Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
> >
> >Subjec
>-Original Message-
>From: Roper, Matthew D
>Sent: Tuesday, September 6, 2022 1:09 PM
>To: Ruhl, Michael J
>Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Sripada,
>Radhakrishna
>Subject: Re: [PATCH v2 01/12] drm/i915: Move locking and unclaimed check
>into mmio_de
Hi Jingyu,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on e47eb90a0a9ae20b82635b9b99a8d0979b757ad8]
url:
https://github.com/intel-lab-lkp/linux/commits/Jingyu-Wang/drm-amdgpu-cleanup-coding-style-in-amdgpu_kms-c/20220906-104802
base
1 - 100 of 212 matches
Mail list logo
