Hi,
On 27/06/2022 00:32, Martin Blumenstingl wrote:
Hi Neil,
On Fri, Jun 17, 2022 at 9:27 AM Neil Armstrong wrote:
+/* [31:16] RW intr_stat/clr. Default 0.
+ * For each bit, read as this interrupt level status,
+ * write 1 to clear.
Do you know if an interrupt line fr
Hi Lucas
Am 26.06.22 um 23:01 schrieb Lucas De Marchi:
On Fri, Jun 17, 2022 at 01:52:04AM -0700, Lucas De Marchi wrote:
Like was done for read, provide the equivalent for write. Even if
current users are not in the hot path, this should future-proof it.
v2:
- Remove default from _Generic() -
On 23/06/2022 10:21, Jocelyn Falempe wrote:
On 22/06/2022 20:34, Lyude Paul wrote:
Some small nitpicks:
On Wed, 2022-06-22 at 14:48 +0200, Jocelyn Falempe wrote:
With an AST2600, the screen is garbage when going out of suspend.
This is because color settings are lost, and not restored on resum
Hi Dan,
On Mon 27 Jun 22, 08:26, Dan Carpenter wrote:
> On Fri, Jun 24, 2022 at 04:53:25PM +0200, Paul Kocialkowski wrote:
> > Hello Dan,
> >
> > On Tue 14 Jun 22, 15:07, Dan Carpenter wrote:
> > > Hello Paul Kocialkowski,
> > >
> > > The patch efeeaefe9be5: "drm: Add support for the LogiCVC dis
Hi Kevin
Am 24.06.22 um 22:26 schrieb Kevin Brace:
From: Kevin Brace
Hi Dave and Daniel,
This is my first attempt (this is not a RFC posting) in trying to get
OpenChrome DRM pulled in for Linux 5.20.
First of all, thank you so much for working on this.
I started to work on this seriously
Am 27.06.22 um 09:31 schrieb Jocelyn Falempe:
On 23/06/2022 10:21, Jocelyn Falempe wrote:
On 22/06/2022 20:34, Lyude Paul wrote:
Some small nitpicks:
On Wed, 2022-06-22 at 14:48 +0200, Jocelyn Falempe wrote:
With an AST2600, the screen is garbage when going out of suspend.
This is because c
Thanks for fixing this issue.
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 6/22/22 6:59 PM, Matthew Auld wrote:
For imported dma-buf objects we leave the object as cache_coherent = 0
across all platforms, which is reasonable given that have no clue what
the memory underneath is, and its n
On Wed, May 25, 2022 at 1:54 PM Miaoqian Lin wrote:
> Every iteration of for_each_available_child_of_node() decrements
> the reference counter of the previous node. There is no decrement
> when break out from the loop and results in refcount leak.
> Add missing of_node_put() to fix this.
>
> Fixe
Hello Linus,
On 6/26/22 20:54, Linus Torvalds wrote:
> So this has been going on for a while, and it's quite annoying.
>
> At bootup, my main desktop (Threadripper 3970X with radeon graphics)
> now complains about
>
> resource sanity check: requesting [mem 0xd000-0xdfff], which
> spans
Hi Sam,
On 6/24/22 21:54, Sam Ravnborg wrote:
On Fri, Jun 10, 2022 at 01:15:11PM +0200, Bastian Krause wrote:
Add support for the Ampire AM-800600P5TMQW-TB8H 800x600 panel. Data
sheet is currently not publicly available, unfortunately.
Signed-off-by: Bastian Krause
Applied to drm-misc (dr
On 24/06/2022 21:23, Zeng, Oak wrote:
Let's compare "tlb invalidate at vm unbind" vs "tlb invalidate at backing
storage":
Correctness:
consider this sequence of:
1. unbind va1 from pa1,
2. then bind va1 to pa2. //user space has the freedom to do this as it manages
virtual address space
3. Su
On 27/06/2022 09:39, Thomas Zimmermann wrote:
Am 27.06.22 um 09:31 schrieb Jocelyn Falempe:
On 23/06/2022 10:21, Jocelyn Falempe wrote:
On 22/06/2022 20:34, Lyude Paul wrote:
Some small nitpicks:
On Wed, 2022-06-22 at 14:48 +0200, Jocelyn Falempe wrote:
With an AST2600, the screen is garba
Maxime Ripard wrote:
> Commit 30f8c74ca9b7 ("drm/vc4: Warn if some v3d code is run on BCM2711")
> introduced a check in vc4_perfmon_get() that dereferences a pointer before
> we checked whether that pointer is valid or not.
>
> Let's rework that function a bit to do things in the proper order.
>
>
On Fri, Jun 24, 2022 at 04:46:36PM +0200, Paul Kocialkowski wrote:
> Hi,
>
> On Fri 24 Jun 22, 16:37, Maxime Ripard wrote:
> > Hi,
> >
> > On Fri, Jun 24, 2022 at 04:35:25PM +0200, Paul Kocialkowski wrote:
> > > On Tue 14 Jun 22, 15:08, Dan Carpenter wrote:
> > > > The "regmap" is supposed to be
+ Ying
> Subject: [PATCH v6 2/2] drm: lcdif: Add support for i.MX8MP LCDIF variant
>
> Add support for i.MX8MP LCDIF variant. This is called LCDIFv3 and is
> completely different from the LCDIFv3 found in i.MX23 in that it has a
> completely scrambled register layout compared to all previous LCDI
On Sat, Jun 25, 2022 at 12:02:19PM -0700, Niranjana Vishwanathapura wrote:
> On Fri, Jun 24, 2022 at 10:07:26PM +0200, Daniel Vetter wrote:
> > On Fri, Jun 24, 2022 at 10:49:36AM -0700, Niranjana Vishwanathapura wrote:
> > > VM_BIND and related uapi definitions
> > >
> > > v2: Reduce the scope to
Hi
Am 26.06.22 um 20:54 schrieb Linus Torvalds:
So this has been going on for a while, and it's quite annoying.
At bootup, my main desktop (Threadripper 3970X with radeon graphics)
now complains about
resource sanity check: requesting [mem 0xd000-0xdfff], which
spans more than BOOTF
Remove the param "struct drm_buddy *mm" which is unused in
the function drm_block_alloc()/drm_block_free().
Signed-off-by: Cai Huoqing
---
drivers/gpu/drm/drm_buddy.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/dri
On Sat, Jun 25, 2022 at 06:08:21PM -0700, Niranjana Vishwanathapura wrote:
> On Sat, Jun 25, 2022 at 12:02:19PM -0700, Niranjana Vishwanathapura wrote:
> > On Fri, Jun 24, 2022 at 10:07:26PM +0200, Daniel Vetter wrote:
> > > On Fri, Jun 24, 2022 at 10:49:36AM -0700, Niranjana Vishwanathapura wrote:
On Sat, Jun 25, 2022 at 01:01:14PM +0200, Jason A. Donenfeld wrote:
> This is already set by anon_inode_getfile(), since dma_buf_fops has
> non-NULL ->llseek, so we don't need to set it here too.
>
> Suggested-by: Al Viro
> Cc: Sumit Semwal
> Cc: Christian König
> Cc: dri-devel@lists.freedeskto
On 27/06/2022 09:06, conor.doo...@microchip.com wrote:
>
>
> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>> On 21/06/2022 11:49, conor.doo...@microchip.com wrote:
>>> On 20/06/2022 01:25, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>>
Hi Daniel,
On Mon, Jun 27, 2022 at 11:08:32AM +0200, Daniel Vetter wrote:
> On Sat, Jun 25, 2022 at 01:01:14PM +0200, Jason A. Donenfeld wrote:
> > This is already set by anon_inode_getfile(), since dma_buf_fops has
> > non-NULL ->llseek, so we don't need to set it here too.
> >
> > Suggested-by:
Il 27/06/22 10:03, Bo-Chen Chen ha scritto:
From: Markus Schneider-Pargmann
This patch adds a embedded displayport driver for the MediaTek mt8195 SoC.
It supports the MT8195, the embedded DisplayPort units. It offers
DisplayPort 1.4 with up to 4 lanes.
The driver creates a child device for th
Il 27/06/22 10:03, Bo-Chen Chen ha scritto:
From: Guillaume Ranquet
This patch adds External DisplayPort support to the mt8195 eDP driver.
Signed-off-by: Guillaume Ranquet
[Bo-Chen: Move some dp features here and modify for reviewers' comments.]
Signed-off-by: Bo-Chen Chen
---
drivers/gpu/
Il 27/06/22 10:03, Bo-Chen Chen ha scritto:
From: Jitao Shi
From the DP spec 1.4a chapter 3.3, upstream devices should implement
HPD signal de-bouncing on an external connection.
A period of 100ms should be used to detect an HPD connect event.
To cover these cases, HPD de-bounce should be impl
Il 27/06/22 10:03, Bo-Chen Chen ha scritto:
Set the monitor power state to DP_SET_POWER_D3 to avoid garbage.
Signed-off-by: Jitao Shi
Signed-off-by: Bo-Chen Chen
Reviewed-by: AngeloGioacchino Del Regno
On Thu, 23 Jun 2022 at 16:31, Matthew Auld wrote:
>
> On 23/06/2022 15:52, Christian König wrote:
> > Am 23.06.22 um 16:13 schrieb Matthew Auld:
> >> [SNIP]
> TTM_BO_VM_NUM_PREFAULT);
> + /*
> +* Ensure we check for any fatal errors if we had to
>
Il 24/06/22 05:09, Bo-Chen Chen ha scritto:
From: Guillaume Ranquet
Dpintf is the displayport interface hardware unit. This unit is similar
to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main
differences are:
- 4 pixels for one iteration
Il 24/06/22 05:09, Bo-Chen Chen ha scritto:
From: Guillaume Ranquet
Enabling the dpi too early causes glitches on screen.
Move the call to mtk_dpi_enable() at the end of the bridge_enable
callback to ensure everything is setup properly before enabling dpi.
Fixes: 9e629c17aa8d ("drm/mediatek:
Il 27/06/22 12:30, Rex-BC Chen ha scritto:
On Mon, 2022-06-27 at 18:07 +0800, AngeloGioacchino Del Regno wrote:
Il 27/06/22 10:03, Bo-Chen Chen ha scritto:
From: Markus Schneider-Pargmann
This patch adds a embedded displayport driver for the MediaTek
mt8195 SoC.
It supports the MT8195, the e
On 6/26/22 12:28, Helge Deller wrote:
> This series fixes possible out-of-bound memory accesses when users trigger
> screen resolutions changes with invalid input parameters, e.g. reconfigures
> screen which is smaller than the current font size, or if the virtual screen
> size is smaller than the
On Sun, Jun 19, 2022 at 09:31:03PM -0100, Melissa Wen wrote:
> Add 3D LUT for gammar correction using a 3D lookup table. The position
> in the color correction pipeline where 3D LUT is applied depends on hw
> design, being after CTM or gamma. If just after CTM, a shaper lut must
> be set to shape
On 27/06/2022 07:40, allen wrote:
From: allen chen
add read max-lane and max-pixel-clock from dt property
Those 2 properties should be documented first in the DT bindings.
Neil
Signed-off-by: Allen Chen
Signed-off-by: Pin-yen Lin
---
drivers/gpu/drm/bridge/ite-it6505.c | 35 ++
On 24/06/2022 20:19, Marek Vasut wrote:
The DSI lane count can be accessed via the dsi device pointer,
make use of that. No functional change.
Signed-off-by: Marek Vasut
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: Lucas Stach
Cc: Maxime Ripard
Cc: Robert Foss
Cc: Sam Ravnborg
---
drivers
Hi,
On 24/06/2022 14:10, Geert Uytterhoeven wrote:
The various Freescale i.MX8 display bridges are only present on
Freescale i.MX8 SoCs. Hence add a dependency on ARCH_MXC, to prevent
asking the user about these drivers when configuring a kernel without
i.MX SoC support.
Fixes: e60c4354840b2fe
Hi Javier, Daniel,
On Fri, Jun 24, 2022 at 11:18:40PM +0200, Javier Martinez Canillas wrote:
> Hello Daniel,
>
> On 6/24/22 23:01, Daniel Vetter wrote:
> >
> > [...]
> >
> > Hey so since you have a bunch of patches merged into drm already but seem
> > to lack drm-misc commit rights to push these
There are two events that signal a real change of the link state: HPD going
high means the sink is newly connected or wants the source to re-read the
EDID, RX sense going low is a indication that the link has been disconnected.
Ignore the other two events that also trigger interrupts, but don't ne
Thanks for the comments, Dmitry. I haven't noticed mode->hdisplay being used.
My idea was to run thru the topology and tie up the encoders with dspp to the
CRTCs.
Since mode is available only in the commit, we cannot use the
dpu_encoder_get_topology during initialization sequence.
The requireme
Hello José,
On 6/27/22 14:36, José Expósito wrote:
> Hi Javier, Daniel,
>
> On Fri, Jun 24, 2022 at 11:18:40PM +0200, Javier Martinez Canillas wrote:
>> Hello Daniel,
>>
>> On 6/24/22 23:01, Daniel Vetter wrote:
>>>
>>> [...]
>>>
>>> Hey so since you have a bunch of patches merged into drm alread
Il 23/06/22 11:31, allen ha scritto:
From: allen chen
add read max-lane and max-pixel-clock from dt property
Signed-off-by: Allen-kh Cheng
Signed-off-by: Pin-yen Lin
Hello Allen,
as Sam also pointed out, please fix your S-o-b email: it has to match with the
author one.
Anyway, you're add
From: vijendar
Fixed below checkpatch warnings and errors
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:131: CHECK: Comparison to NULL could be
written "apd"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:150: CHECK: Comparison to NULL could be
written "apd"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:196: CHE
On 2022-06-26 10:20, Tom Rix wrote:
sparse reports
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3885:6: warning:
symbol 'FORCE_RATE' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3886:10: warning:
symbol 'FORCE_LANE_COUNT' was
On 2022-06-26 10:46, Tom Rix wrote:
sparse reports
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn32/irq_service_dcn32.c:39:20:
warning: symbol 'to_dal_irq_source_dcn32' was not declared. Should it be static?
to_dal_irq_source_dnc32() is only referenced in irq_service_dnc32.c, so change
it
On Mon, 27 Jun 2022 16:03:32 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann
>
> This controller is present on several mediatek hardware. Currently
> mt8195 and mt8395 have this controller without a functional difference,
> so only one compatible field is added.
>
> The controller c
On Fri, Jun 24, 2022 at 11:26 AM Rob Herring wrote:
>
> On Tue, 21 Jun 2022 18:10:14 +0300, Mikko Perttunen wrote:
> > From: Thierry Reding
> >
> > Convert the Tegra host1x controller bindings from the free-form text
> > format to json-schema.
> >
> > This also adds the missing display-hub DT bin
On Sat, 11 Jun 2022, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Liu Ying
> ---
> v8->v9:
> * No change.
>
> v7->v8:
> * No change.
>
> v6->v7:
> * Add Rob's R-b tag.
>
> v5->v6:
> * Drop 'selec
Hi,
Le jeudi 23 juin 2022 à 10:58 +0200, Lucas Stach a écrit :
> > > In the DMA API keeping things mapped is also a valid use-case, but then
> > > you need to do explicit domain transfers via the dma_sync_* family,
> > > which DMA-buf has not inherited. Again those sync are no-ops on cache
> > > c
On Wed, 22 Jun 2022 10:02:43 +0200, Maxime Ripard wrote:
> Commit 30f8c74ca9b7 ("drm/vc4: Warn if some v3d code is run on BCM2711")
> introduced a check in vc4_perfmon_get() that dereferences a pointer before
> we checked whether that pointer is valid or not.
>
> Let's rework that function a bit t
Le jeudi 23 juin 2022 à 11:33 +0200, Lucas Stach a écrit :
> >
> > See for example on AMD/Intel hardware most of the engines can perfectly
> > deal with cache coherent memory accesses. Only the display engines can't.
> >
> > So on import time we can't even say if the access can be coherent and
Am Montag, dem 27.06.2022 um 09:54 -0400 schrieb Nicolas Dufresne:
> Le jeudi 23 juin 2022 à 11:33 +0200, Lucas Stach a écrit :
> > >
> > > See for example on AMD/Intel hardware most of the engines can perfectly
> > > deal with cache coherent memory accesses. Only the display engines can't.
> > >
On Tue, 21 Jun 2022, cy_huang wrote:
> From: ChiYuan Huang
>
> Add 'richtek,bled-ocp-microamp' property parsing in
> device_property_init function.
>
> This value may configure prior to the kernel driver. If it's not specified in
> devicetree, keep the original setting. Else, use clamp to align
On Tue, 21 Jun 2022, cy_huang wrote:
> From: ChiYuan Huang
>
> Add 'richtek,bled-ocp-microamp' property to make it chooseable.
>
> The wrong backlight ocp level may affect the backlight channel output
> current smaller than configured.
>
> Signed-off-by: ChiYuan Huang
> Reviewed-by: Daniel Th
On 6/3/22 15:41, Yannick Fertre wrote:
All plans must be disabled before the CRTC shutdown helping
the crtc to restart from a clean situation (without unwanted
planes already enable).
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 6 ++
1 file changed, 6 insertions(+)
On 6/3/22 15:42, Yannick Fertre wrote:
Remove error message about scaling & replace it by a debug
message to avoid too much error.
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/stm/ltdc.c
On 6/3/22 15:43, Yannick Fertre wrote:
Fix issues reported by checkpatch.pl:
- Braces {} should be used on all arms
- Blank lines
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/stm/ltdc.
On 6/3/22 15:45, Yannick Fertre wrote:
Support of vertical & horizontal mirroring features thanks to
the plane rotation property.
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 163 -
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed,
On 6/3/22 15:46, Yannick Fertre wrote:
The latest hardware version (0x40100) supports a hardware threshold
register (aka FUTR) to trigger a fifo underrun interrupt.
A software threshold has been implemented for other hardware versions.
The threshold is set to 128 by default.
Signed-off-by: Ya
On Sat, 18 Jun 2022, ChiaEn Wu wrote:
> Hi Lee,
>
> Thanks for your helpful comments, we have some questions and replies below.
>
> Lee Jones 於 2022年6月16日 週四 清晨6:49寫道：
>
> >
> > On Mon, 13 Jun 2022, ChiaEn Wu wrote:
> >
> > > From: ChiYuan Huang
> > >
> > > Add Mediatek MT6370 MFD support.
>
On 6/3/22 15:44, Yannick Fertre wrote:
Zpos property is immutable for all hardware versions except the last
version (0x40100) which support the blending order feature
(dynamic z-order).
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/drv.c | 1 +
drivers/gpu/drm/stm/ltdc.c | 23 ++
From: Mikko Perttunen
Add schema information for specifying context stream IDs. This uses
the standard iommu-map property.
Signed-off-by: Mikko Perttunen
Reviewed-by: Robin Murphy
Acked-by: Rob Herring
---
v3:
* New patch
v4:
* Remove memory-contexts subnode.
---
.../bindings/display/tegra/n
From: Mikko Perttunen
Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.
Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual
From: Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers
for Host1x and VIC on Tegra234.
Signed-off-by: Mikko Perttunen
Acked-by: Krzysztof Kozlowski
---
include/dt-bindings/clock/tegra234-clock.h | 4
include/dt-bindings/memory/tegra234-mc.h |
From: Mikko Perttunen
For new (Tegra186+) SoCs, use a new ('full-featured') job opcode
sequence that is compatible with virtualization. In particular,
the Host1x hardware in Tegra234 is more strict regarding the sequence,
requiring ACQUIRE_MLOCK-SETCLASS-SETSTREAMID opcodes to occur in
that seque
From: Mikko Perttunen
Add device tree nodes for Host1x and VIC on Tegra234.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
b/arch/arm64/boot/dts/
From: Mikko Perttunen
NVDEC's TRANSCFG register is at a different offset than VIC.
This becomes a problem now when context isolation is enabled and
the reset value of the register is no longer sufficient.
Signed-off-by: Mikko Perttunen
---
v6:
* New patch
---
drivers/gpu/drm/tegra/nvdec.c | 4
From: Mikko Perttunen
Add device data and chip headers for Tegra234.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/Makefile | 3 +-
drivers/gpu/host1x/dev.c | 42
drivers/gpu/host1x/hw/host1x08.c | 33
drivers/gpu/host1x
From: Mikko Perttunen
Refactor 'regs' property loading using devm_platform_ioremap_*
and add loading of the 'common' region found on Tegra234.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 46 +---
drivers/gpu/host1x/dev.h | 3 +++
2 files c
From: Mikko Perttunen
For engines that support context isolation, allocate a context when
opening a channel, and set up stream ID offset and context fields
when submitting a job.
As of this commit, the stream ID offset and fallback stream ID
are not used when context isolation is disabled. Howev
From: Mikko Perttunen
Implement the get_streamid_offset and can_use_memory_ctx callbacks
required for supporting context isolation. Since old firmware on VIC
cannot support context isolation without hacks that we don't want to
implement, check the firmware binary to see if context isolation
shoul
From: Mikko Perttunen
Update VIC and Host1x bindings for changes in Tegra234.
Namely,
- New compatible strings
- Sharded syncpoint interrupts
- Optional reset.
Also, fix the order of descriptions for VM/hypervisor
register apertures -- while the reg-names specification
was correct, the descript
From: Mikko Perttunen
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen
---
v2:
* Directly set DMA mask instead of inheriting from Host1x.
* Use iommu-map instead of custom DT property.
v4:
* Use u64 instead of dm
From: Mikko Perttunen
Program virtualization tables specifying which VMs have access to which
Host1x hardware resources. Programming these has become mandatory in
Tegra234.
For now, since the driver does not operate as a Host1x hypervisor, we
basically allow access to everything to everyone.
Si
From: Mikko Perttunen
Add Tegra234 support for VIC. It is backwards compatible with
Tegra194.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/vic.c | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.c b/driv
From: Mikko Perttunen
Integrated the Host1x context isolation series (patches 1 to 8) and
Tegra234 support series (patches 9 to 22) in one email thread for
the benefit of automatic testers.
Changes from previous versions:
Context isolation:
* Improved check to ensure context devices are attache
From: Mikko Perttunen
When MLOCK enforcement is enabled, the 0-word write currently done
is rejected by the hardware outside of an MLOCK region. As such,
on these chips, which also have the newer, more convenient RESTART_W
opcode, use that instead to skip over the timed out job.
Signed-off-by: M
From: Mikko Perttunen
On Tegra234, each Host1x VM has 8 interrupt lines. Each syncpoint
can be configured with which interrupt line should be used for
threshold interrupt, allowing for load balancing.
For now, to keep backwards compatibility, just set all syncpoints
to the first interrupt.
Sign
From: Mikko Perttunen
The bracketing for the interrupts property in the device tree
example is incorrect. Fix it.
Signed-off-by: Mikko Perttunen
---
.../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/Documentat
From: Mikko Perttunen
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/falcon.c |
From: Mikko Perttunen
Host1x class information and opcodes are unchanged or backwards
compatible across SoCs so let's not duplicate them for each one
but have them in a shared header file.
At the same time, add opcode functions for acquire/release_mlock.
Signed-off-by: Mikko Perttunen
---
dri
From: Mikko Perttunen
With the full-featured opcode sequence using MLOCKs, we need to also
unlock those MLOCKs in the event of a timeout. However, it turns out
that on Tegra186/Tegra194, by default, we don't need to do this;
furthermore, on Tegra234 it is much simpler to do; so only implement
thi
From: Mikko Perttunen
Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor,
if one
Le lundi 27 juin 2022 à 16:06 +0200, Lucas Stach a écrit :
> Am Montag, dem 27.06.2022 um 09:54 -0400 schrieb Nicolas Dufresne:
> > Le jeudi 23 juin 2022 à 11:33 +0200, Lucas Stach a écrit :
> > > >
> > > > See for example on AMD/Intel hardware most of the engines can perfectly
> > > > deal with
From: Mikko Perttunen
Host1x on Tegra234 does not have a software-controllable reset line.
As such, don't bail out if we don't find one in the device tree.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/host1x/dev.c
On Mon, 27 Jun 2022 13:40:04 +
Dennis Tsiang wrote:
> This patch is an early RFC to discuss the viable options and
> alternatives for inclusion of unsigned integer formats for the DRM API.
>
> This patch adds a new single component 16-bit and a two component 32-bit
> DRM fourcc’s that repres
https://bugzilla.kernel.org/show_bug.cgi?id=216175
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On 6/24/2022 6:15 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-06-24 18:02:50)
On 6/24/2022 5:46 PM, Dmitry Baryshkov wrote:
On Sat, 25 Jun 2022 at 03:28, Dmitry Baryshkov
wrote:
On Sat, 25 Jun 2022 at 03:23, Kuogee Hsieh wrote:
On 6/24/2022 5:21 PM, Dmitry Baryshkov wrote:
On Sat,
Hi Lee,
Thanks for your reply!
Lee Jones 於 2022年6月27日 週一 晚上10:14寫道：
>
> On Sat, 18 Jun 2022, ChiaEn Wu wrote:
>
> > Hi Lee,
> >
> > Thanks for your helpful comments, we have some questions and replies below.
> >
> > Lee Jones 於 2022年6月16日 週四 清晨6:49寫道：
> >
> > >
> > > On Mon, 13 Jun 2022, ChiaEn
On Mon, 27 Jun 2022 at 18:33, Kuogee Hsieh wrote:
>
>
> On 6/24/2022 6:15 PM, Stephen Boyd wrote:
> > Quoting Kuogee Hsieh (2022-06-24 18:02:50)
> >> On 6/24/2022 5:46 PM, Dmitry Baryshkov wrote:
> >>> On Sat, 25 Jun 2022 at 03:28, Dmitry Baryshkov
> >>> wrote:
> On Sat, 25 Jun 2022 at 03:23
On 6/27/2022 8:38 AM, Dmitry Baryshkov wrote:
On Mon, 27 Jun 2022 at 18:33, Kuogee Hsieh wrote:
On 6/24/2022 6:15 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-06-24 18:02:50)
On 6/24/2022 5:46 PM, Dmitry Baryshkov wrote:
On Sat, 25 Jun 2022 at 03:28, Dmitry Baryshkov
wrote:
On Sat
On Sat, Jun 25, 2022 at 06:49:14PM -0700, Niranjana Vishwanathapura wrote:
> VM_BIND design document with description of intended use cases.
>
> v2: Reduce the scope to simple Mesa use case.
> v3: Expand documentation on dma-resv usage, TLB flushing and
> execbuf3.
> v4: Remove vm_bind tlb flu
Hello everyone,
This series is a follow up of the XRGB to RGB332 conversion KUnit tests.
The first 3 patches refactor the existing test to make them agnostic of the
target format and add support for "swab".
The last patch adds the RGB565 conversion values, and shows how more formats
will b
The RGB565 conversion functions take an extra parameter ("swab")
indicating whether the bytes should be swapped into the clip buffer or
not.
Create a union in the "convert_xrgb_result" structure holding the
value of the "swab" parameter as well as the conversion function
pointer.
Signed-off-b
The tests available at the moment only check the conversion from
XRGB to RGB332. However, more conversion will be tested in the
future.
In order to make the struct and functions present in the tests more
generic, rename xrgb_to_rgb332_* to convert_xrgb_*.
Signed-off-by: José Expósito
Extend the existing test cases to test the conversion from XRGB to
RGB565.
The documentation and the color picker available on [1] are useful
resources to understand this patch and validate the values returned by
the conversion function.
[1] http://www.barth-dev.de/online/rgb565-color-picker/
In order to support multiple destination format conversions, store the
target format, conversion function, parameters and expected result in
its own structure.
Signed-off-by: José Expósito
---
.../gpu/drm/tests/drm_format_helper_test.c| 88 ++-
1 file changed, 64 insertions(+
https://bugzilla.kernel.org/show_bug.cgi?id=216119
Daniel Vetter (dan...@ffwll.ch) changed:
What|Removed |Added
CC||dan...@ffwll.ch
--- Com
[...]
> > > > > +#define MT6370_IRQ_DSV_VPOS_OCP 124
> > > > > +#define MT6370_IRQ_DSV_BST_OCP 125
> > > > > +#define MT6370_IRQ_DSV_VNEG_SCP 126
> > > > > +#define MT6370_IRQ_DSV_VPOS_SCP 127
> > > > > +
> > > > > +struct mt6370_info {
> > > >
If for some reason the msm_dp_config::descs array starts from non-zero
index or contains the hole, setting the msm_dp_config::num_descs might
be not that obvious and error-prone. Use ARRAY_SIZE to set this field
rather than encoding the value manually.
Reported-by: Kuogee Hsieh
Signed-off-by: Dmi
On Mon, Jun 20, 2022 at 09:06:34PM +, conor.doo...@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> >> From:
On Wed, Jun 15, 2022 at 12:13:46AM +0530, Ramalingam C wrote:
> From: Niranjana Vishwanathapura
>
> In i915_fence_get_driver_name(), user may not hold a
> reference to rq->engine. Hence do not access it. Instead,
> store required device private pointer in 'rq->i915' and use it.
>
> Signed-off-by
1 - 100 of 239 matches
Mail list logo
