Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin wrote:
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > From: Conor Dooley
> >
> > snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> > width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
Am 21.06.22 um 00:02 schrieb Andrey Grodzovsky:
Problem:
In amdgpu_job_submit_direct - The refcount should drop by 2
but it drops only by 1.
amdgpu_ib_sched->emit -> refcount 1 from first fence init
dma_fence_get -> refcount 2
dme_fence_put -> refcount 1
Fix:
Add put for external_hw_fence in am
This patch series add support for loadavg values for GPU
sub-components. I am adding a SMA algorithm as I was not
really sure if EWMA would be a good fit for this use case.
Changes v2:
- Addressed feedback from Lucas
Christian Gmeiner (4):
drm/etnaviv: add simple moving average (SMA)
drm/etn
This adds a SMA algorithm inspired by Exponentially weighted moving
average (EWMA) algorithm found in the kernel.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_sma.h | 53 +++
1 file changed, 53 insertions(+)
create mode 100644 drivers/gpu/drm/etna
Might be helpful to see the loadavg in debugfs.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 202002a
The GPU has an idle state register where each bit represents the idle
state of a sub-GPU component like FE or TX. Sample this register
every 10ms and calculate a simple moving average over the sub-GPU
component idle states with a total observation time frame of 1s.
This provides us with a percenta
Make it possible to access the sub-GPU component load value from
user space with the perfmon infrastructure.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 79 +++
1 file changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv
If the backlight node is not enabled, this (silently) returns with
-EPROBE_DEFER. /sys/kernel/debug/devices_deferred also shows nothing
helpful:
$ cat /sys/kernel/debug/devices_deferred
display
With this patch, there is a helpful hint:
$ cat /sys/kernel/debug/devices_deferred
display panel-simple:
Am 21.06.22 um 00:02 schrieb Andrey Grodzovsky:
This function should drop the fence refcount when it extracts the
fence from the fence array, just as it's done in amdgpu_fence_process.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fen
On Mon, Jun 20, 2022 at 6:19 PM Tvrtko Ursulin
wrote:
>
>
> On 20/06/2022 11:02, zys.zlj...@gmail.com wrote:
> > From: katrinzhou
> >
> > The variable ret is reassigned and the value EINVAL is never used.
> > Thus, remove the unused assignments.
> >
> > Addresses-Coverity: ("Unused value")
> > Fi
Greg KH writes:
> On Mon, Jun 20, 2022 at 11:49:07AM +0200, maciej.kwapulin...@linux.intel.com
> wrote:
>> Please share your thoughts.
>
> No code here to share thoughts about :(
code will be published in comming weeks to dri-devel ML
Consider '*' alignment in comments
Signed-off-by: Jiang Jian
---
drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c
b/drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c
index 6fbfeb01b3
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley
> ---
> .../bindings/spi/snps
On Wed, 16 Jun 2021 09:38:14 +0200, Maciej Kwapulinski wrote:
> after consulting, we will try to share api and some kernel code
> between the two drivers.
We prepared a prototype work based on Daniel Vetter’s invitation to
evaluate DRM framework as prospective fit.
Early results look quite promis
On 6/21/22 06:06, conor.doo...@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>> From: Conor Dooley
>>>
>>> snps,dw
From: katrinzhou
The variable ret is reassigned and the value EINVAL is never used.
Thus, remove the unused assignments.
Addresses-Coverity: ("Unused value")
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create
parameters (v5)")
Signed-off-by: katrinzhou
---
drivers/gpu/
On 2022-06-17 01:52, Nicolin Chen wrote:
The ap_aqic() is called by vfio_ap_irq_enable() where it passes in a
virt value that's casted from a physical address "h_nib". Inside the
ap_aqic(), it does virt_to_phys() again.
Since ap_aqic() needs a physical address, let's just pass in a pa of
ind dir
From: katrinzhou
Add missing else in set_proto_ctx_param() to fix coverity issue.
Addresses-Coverity: ("Unused value")
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create
parameters (v5)")
Suggested-by: Tvrtko Ursulin
Signed-off-by: katrinzhou
---
Update from v1:
Fixed
On Mon, Jun 20, 2022 at 6:13 PM Jani Nikula wrote:
>
> On Mon, 20 Jun 2022, zys.zlj...@gmail.com wrote:
> > From: katrinzhou
> >
> > The variable ret is reassigned and the value EINVAL is never used.
> > Thus, remove the unused assignments.
>
> It's obviously a bug, but it's not obvious just thro
On 6/21/22 07:49, Conor Dooley wrote:
>
>
> On 20/06/2022 23:46, Damien Le Moal wrote:
>> On 6/21/22 06:06, conor.doo...@microchip.com wrote:
>>> On 20/06/2022 21:56, Serge Semin wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
content is safe
Am 21.06.22 um 00:03 schrieb Andrey Grodzovsky:
Problem:
After we start handling timed out jobs we assume there fences won't be
signaled but we cannot be sure and sometimes they fire late. We need
to prevent concurrent accesses to fence array from
amdgpu_fence_driver_clear_job_fences during GPU r
Am 21.06.22 um 00:03 schrieb Andrey Grodzovsky:
Problem:
This patch caused negative refcount as described in [1] because
for that case parent fence did not signal by the time of drm_sched_stop and
hence
kept in pending list the assumption was they will not signal and
so fence was put to account
Am 21.06.22 um 00:03 schrieb Andrey Grodzovsky:
Align refcount behaviour for amdgpu_job embedded HW fence with
classic pointer style HW fences by increasing refcount each
time emit is called so amdgpu code doesn't need to make workarounds
using amdgpu_job.job_run_counter to keep the HW fence refc
--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Adri-n-Larumbe/devcoredump-support-for-Panfrost-GPU-driver/20220621-103431
base: git://anongit.freedesktop.org/drm/drm drm-next
config: s390-buildonly-randconfig-r006-2
On Tue, Jun 21, 2022 at 12:36:56PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/xlnx/zynqmp_disp.c: In function 'zynqmp_disp_create_planes':
> drivers/gpu/drm/xlnx/zynqmp_disp.c
From: Ville Syrjälä
Dropping drm_blend.h from drm_crtc.h broke the
xlnx driver. Make it build again by including
drm_blend.h from the driver directly.
My .config was missing some required dependencies so
I never build tested it :/
Cc: Hyun Kwon
Cc: Laurent Pinchart
Reported-by: Stephen Rothwe
Hi Ville,
Thank you for the patch.
On Tue, Jun 21, 2022 at 10:56:48AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Dropping drm_blend.h from drm_crtc.h broke the
> xlnx driver. Make it build again by including
> drm_blend.h from the driver directly.
>
> My .config was missing some req
On Tue, Jun 21, 2022 at 11:15:35AM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> Thank you for the patch.
>
> On Tue, Jun 21, 2022 at 10:56:48AM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Dropping drm_blend.h from drm_crtc.h broke the
> > xlnx driver. Make it build again by in
On 20/06/2022 17:29, Niranjana Vishwanathapura wrote:
On Mon, Jun 20, 2022 at 11:43:10AM +0100, Tvrtko Ursulin wrote:
Hi,
On 17/06/2022 06:14, Niranjana Vishwanathapura wrote:
VM_BIND design document with description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
si
On 17/06/2022 13:33, Thomas Hellström wrote:
On 5/25/22 20:43, Matthew Auld wrote:
With the uAPI in place we should now have enough in place to ensure a
working system on small BAR configurations.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc:
On 6/21/2022 10:38 AM, Matthew Auld wrote:
On 17/06/2022 13:33, Thomas Hellström wrote:
On 5/25/22 20:43, Matthew Auld wrote:
With the uAPI in place we should now have enough in place to ensure a
working system on small BAR configurations.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Add destination side post processing hw block support in sc7280.
This hwblock enablement is necessary to support color features
like CT Matix (Ex: Night Light feature)
Change-Id: Iba7d5e1693b06cede2891f5b998466070a77c6ef
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catal
Crtc color management needs to be registered only for the crtc which has the
capability to handle it. Since topology decides which encoder will get the
dspp hw block, tie up the crtc and the encoder together
(encoder->possible_crtcs)
Change-Id: If5a0f33547b6f527ca4b8fbb78424b141dbbd711
Signed-off
On Tue, 2022-06-21 at 11:05 +0200, Das, Nirmoy wrote:
>
> On 6/21/2022 10:38 AM, Matthew Auld wrote:
> > On 17/06/2022 13:33, Thomas Hellström wrote:
> > >
> > > On 5/25/22 20:43, Matthew Auld wrote:
> > > > With the uAPI in place we should now have enough in place to
> > > > ensure a
> > > > wor
Hi
Am 21.06.22 um 11:38 schrieb David Gow:
On Tue, Jun 21, 2022 at 12:06 AM José Expósito
wrote:
Add a helper macro to initialize a rectangle from x, y, width and
height information.
Reviewed-by: Jani Nikula
Acked-by: Thomas Zimmermann
Signed-off-by: José Expósito
---
This looks good to
Hi,
On 5/19/22 11:02, Jani Nikula wrote:
> On Wed, 18 May 2022, Hans de Goede wrote:
>> Hi,
>>
>> On 5/18/22 10:55, Jani Nikula wrote:
>>> On Tue, 17 May 2022, Hans de Goede wrote:
ATM on x86 laptops where we want userspace to use the acpi_video backlight
device we often register both
On Tue, 21 Jun 2022, Thomas Zimmermann wrote:
> Hi
>
> Am 21.06.22 um 11:38 schrieb David Gow:
>> On Tue, Jun 21, 2022 at 12:06 AM José Expósito
>> wrote:
>>>
>>> Add a helper macro to initialize a rectangle from x, y, width and
>>> height information.
>>>
>>> Reviewed-by: Jani Nikula
>>> Acked-
Hi
Am 21.06.22 um 00:02 schrieb Alex Deucher:
Maybe someone more familiar with the generic drm fbdev helpers can
help me understand why they don't work with hibernation, at least with
AMD GPUs. We converted amdgpu to use the generic helpers instead of
rolling our own in this patch[1], but it se
Hi Andy,
Am 21.06.22 um 12:17 schrieb Andy.Hsieh:
On 2/16/21 4:39 AM, Nicolas Dufresne wrote:
> Le lundi 15 février 2021 à 09:58 +0100, Christian König a écrit :
>> Hi guys,
>>
>> we are currently working an Freesync and direct scan out from system
>> memory on AMD APUs in A+A laptops.
>>
>> O
From: ChiYuan Huang
This patch series is to add the backlight ocp level property parsing.
Since v4
- Fix wrong macro usage, must be 'DIV_ROUND_UP', not 'roundup'
Since v3
- Refine the description for backlight ocp property.
- Use the enum to list the supported value.
Since v2
- change the pr
From: ChiYuan Huang
Add 'richtek,bled-ocp-microamp' property to make it chooseable.
The wrong backlight ocp level may affect the backlight channel output
current smaller than configured.
Signed-off-by: ChiYuan Huang
Reviewed-by: Daniel Thompson
Reviewed-by: Krzysztof Kozlowski
---
Since v3:
From: ChiYuan Huang
Add 'richtek,bled-ocp-microamp' property parsing in
device_property_init function.
This value may configure prior to the kernel driver. If it's not specified in
devicetree, keep the original setting. Else, use clamp to align the
value in min/max range and also roundup to choo
On Tue, 21 Jun 2022 at 12:06, Kalyan Thota wrote:
>
> Add destination side post processing hw block support in sc7280.
>
> This hwblock enablement is necessary to support color features
> like CT Matix (Ex: Night Light feature)
>
> Change-Id: Iba7d5e1693b06cede2891f5b998466070a77c6ef
> Signed-off-
Clip memory range to screen-buffer size to avoid out-of-bounds access
in fbdev deferred I/O's damage handling.
Fbdev's deferred I/O can only track pages. From the range of pages, the
damage handler computes the clipping rectangle for the display update.
If the fbdev screen buffer ends near the beg
Test-with: 20220621103001.184373-1-matthew.a...@intel.com
IGT: https://patchwork.freedesktop.org/series/104368/#rev2
Mesa: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16739 (WIP)
--
2.36.1
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture. (Thomas)
- Add probed_cpu_visible_size. (Lionel
Vulkan would like to have a rough measure of how much device memory can
in theory be allocated. Also add unallocated_cpu_visible_size to track
the visible portion, in case the device is using small BAR. Also tweak
the locking so we nice consistent values for both the mm->avail and the
visible track
Userspace wants to know the size of CPU visible portion of device
local-memory, and on small BAR devices the probed_size is no longer
enough. In Vulkan, for example, it would like to know the size in bytes
for CPU visible VkMemoryHeap. We already track the io_size for each
region, so plumb that thr
No longer used.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Akeem G Abodunrin
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/intel_memory_region.c | 4 +--
On small BAR configurations, when dealing with I915_MEMORY_CLASS_DEVICE
allocations, we assume that by default, all userspace allocations should
be placed in the non-CPU visible portion. Note that dumb buffers are
not included here, since these are not "GPU accelerated" and likely need
CPU access.
If set, force the allocation to be placed in the mappable portion of
I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory
(i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the
object, that way we can always spill the object into system memory if we
can't
Skip capturing any lmem pages that can't be copied using the CPU. This
in now only best effort on platforms that have small BAR.
Testcase: igt@gem-exec-capture@capture-invisible
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
Cc: Da
A non-recoverable context must be used if the user wants proper error
capture on discrete platforms. In the future the kernel may want to blit
the contents of some objects when later doing the capture stage. Also
extend to newer integrated platforms.
v2(Thomas):
- Also extend to newer integrated p
We should always be explicit and allocate a fence slot before adding a
new fence.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Akeem G Abodunrin
---
drivers/gpu/drm
With the uAPI in place we should now have enough in place to ensure a
working system on small BAR configurations.
v2: (Nirmoy & Thomas):
- s/full BAR/Resizable BAR/ which is hopefully more easily
understood by users.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Just for CI.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 82c3d2d0f0e0..62c3f8185852 100644
--- a/drivers/gpu/d
If the move or clear operation somehow fails, and the memory underneath
is not cleared, like when moving to lmem, then we currently fallback to
memcpy or memset. However with small-BAR systems this fallback might no
longer be possible. For now we use the set_wedged sledgehammer if we
ever encounter
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++
1 file changed, 6 insertio
This change avoids panel prepare/unprepare based on self-refresh
state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/bridge/panel.c | 102 +++--
1 file changed, 98 insertions(+), 4 deletion
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 36 +
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/bridge/panel.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --g
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/dp/dp_cata
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Chang
Hi
Am 17.06.22 um 16:12 schrieb Alex Williamson:
On Fri, 17 Jun 2022 14:41:01 +0200
Thomas Zimmermann wrote:
Hi
Am 17.06.22 um 14:29 schrieb Javier Martinez Canillas:
[adding Zack and Alex to Cc list]
Hello Thomas,
Thanks a lot for tracking this down and figuring out the root cause!
On 6
Hi Dmitry,
>On Mon, 21 Feb 2022 at 17:52, Vinod Polimera
>wrote:
>>
>> Add support for basic panel self refresh (PSR) feature for eDP.
>> Add a new interface to set PSR state in the sink from DPU.
>> Program the eDP controller to issue PSR enter and exit SDP to the
>> sink.
>>
>> Signed-off-by: S
> -Original Message-
> From: Stephen Boyd
> Sent: Wednesday, February 23, 2022 2:59 AM
> To: quic_vpolimer ; agr...@kernel.org;
> airl...@linux.ie; bjorn.anders...@linaro.org; dan...@ffwll.ch;
> devicet...@vger.kernel.org; diand...@chromium.org; dri-
> de...@lists.freedesktop.org; freedr
Generic comment: y...@qualcomm.com address bounces. Please remove it from
the cc list. If you need to send a patch for the internal reasons,
please use Bcc.
On Tue, 21 Jun 2022 at 12:06, Kalyan Thota wrote:
>
> Crtc color management needs to be registered only for the crtc which has the
> capabil
Hi Bjorn,
>> Add support for basic panel self refresh (PSR) feature for eDP.
>> Add a new interface to set PSR state in the sink from DPU.
>> Program the eDP controller to issue PSR enter and exit SDP to the
>> sink.
>>
>> Signed-off-by: Sankeerth Billakanti
>>
>> Changes in v2:
>> - Use dp bri
Am 6/17/22 um 23:19 schrieb David Hildenbrand:
On 17.06.22 21:27, Sierra Guiza, Alejandro (Alex) wrote:
On 6/17/2022 12:33 PM, David Hildenbrand wrote:
On 17.06.22 19:20, Sierra Guiza, Alejandro (Alex) wrote:
On 6/17/2022 4:40 AM, David Hildenbrand wrote:
On 31.05.22 22:00, Alex Sierra wrot
Hi
Am 21.06.22 um 02:14 schrieb Javier Martinez Canillas:
[...]
Since we are talking about remove_conflicting_devices() here, a better code
example could be for a platform device instead of a PCI device, like this:
* static const struct platform_driver example_driver = {
*
On 21.06.22 13:25, Felix Kuehling wrote:
>
> Am 6/17/22 um 23:19 schrieb David Hildenbrand:
>> On 17.06.22 21:27, Sierra Guiza, Alejandro (Alex) wrote:
>>> On 6/17/2022 12:33 PM, David Hildenbrand wrote:
On 17.06.22 19:20, Sierra Guiza, Alejandro (Alex) wrote:
> On 6/17/2022 4:40 AM, Davi
On 20/06/2022 05:07, szuni chen wrote:
> Dear Krzysztof,
>
> Thank you for the valuable command.
>
> Krzysztof Kozlowski 於 2022年6月17日 週五 清晨5:09寫道：
>>
>> On 13/06/2022 04:11, ChiaEn Wu wrote:
>>> From: ChiYuan Huang
>>>
>>> Add Mediatek mt6370 current sink type LED indicator binding documentatio
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
From: Guillaume Ranquet
Dpintf is the displayport interface hardware unit. This unit is similar
to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main
differences are:
- 4 pixels for one round for
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
MediaTek dpi supports direct connection to pins while dp_intf does not
support. Therefore, add a config "support_direct_pin" to control this.
Signed-off-by: Bo-Chen Chen
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
1 file changed,
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
Dp_intf supports YUV422 as output format. In MT8195 Chrome project,
YUV422 output format is used for 4K resolution.
To support this, it is also needed to support color format transfer.
Color format transfer is a new feature for both dpi and dpintf of M
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
For RGB colorimetry, CTA-861 support both limited and full range data
when receiving video with RGB color space.
We use drm_default_rgb_quant_range() to determine the correct setting.
Signed-off-by: Bo-Chen Chen
Reviewed-by: CK Hu
Reviewed-by: Ange
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
This driver will support dp_intf and there are many configs between dpi
and dp_intf. Therefore, we will add many configs in "struct mtk_dpi_conf".
To let this structure more readable, we add this kernel doc.
Signed-off-by: Bo-Chen Chen
Reviewed-by:
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
From: Markus Schneider-Pargmann
DP_INTF is similar to DPI but does not have the exact same feature set
or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the
DisplayPort controller and encoder unit. It takes the sam
David Hildenbrand writes:
> On 21.06.22 13:25, Felix Kuehling wrote:
>>
>> Am 6/17/22 um 23:19 schrieb David Hildenbrand:
>>> On 17.06.22 21:27, Sierra Guiza, Alejandro (Alex) wrote:
On 6/17/2022 12:33 PM, David Hildenbrand wrote:
> On 17.06.22 19:20, Sierra Guiza, Alejandro (Alex) wro
On 21.06.22 13:55, Alistair Popple wrote:
>
> David Hildenbrand writes:
>
>> On 21.06.22 13:25, Felix Kuehling wrote:
>>>
>>> Am 6/17/22 um 23:19 schrieb David Hildenbrand:
On 17.06.22 21:27, Sierra Guiza, Alejandro (Alex) wrote:
> On 6/17/2022 12:33 PM, David Hildenbrand wrote:
>>
Hello Thomas,
On 6/21/22 13:29, Thomas Zimmermann wrote:
[...]
>>> +
>>> +static bool overlap(resource_size_t base1, resource_size_t end1,
>>> + resource_size_t base2, resource_size_t end2)
>>> +{
>>> + return (base1 < end2) && (end1 > base2);
>>> +}
>>
>> There's a resource_over
On 6/21/22 12:44, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture. (Tho
On 2022-06-20 19:13, Jernej Skrabec wrote:
Kernel occasionally complains that there is mismatch in segment size
when trying to render HW decoded videos and rendering them directly with
sun4i DRM driver. Following message can be observed on H6 SoC:
[ 184.298308] [ cut here ]-
Quoting Stephen Kitt (2022-06-16 18:08:21)
> This started with work on the removal of backlight_properties'
> deprecated fb_blank field, much of which can be taken care of by using
> helper functions provided by backlight.h instead of directly accessing
> fields in backlight_properties. This patch
Hi Adrian,
Great work on the devcoredump support! This is really cool to see coming
along, thank you! I've left a few notes below:
> + if (panfrost_dump_registers[i] >= JS_HEAD_LO(0) &&
> + panfrost_dump_registers[i] <= JS_CONFIG_NEXT(0))
> + js_as_
On Wed, Jun 15, 2022 at 11:13:33AM -0700, Prashant Malani wrote:
> I should add:
>
> Series submission suggestions (of course, open to better suggestions too):
> - Patches 1-3 can go through the USB repo.
I will take patches 1 and 2 now.
seems the others need reworks or acks from the DT people.
The various Freescale i.MX8MP display bridges are only present on
Freescale i.MX8 SoCs. Hence add a dependency on ARCH_MXC, to prevent
asking the user about these drivers when configuring a kernel without
i.MX SoC support.
Fixes: e60c4354840b2fe8 ("drm/bridge: imx: Add LDB support for i.MX8qm")
F
https://bugzilla.kernel.org/show_bug.cgi?id=216119
--- Comment #13 from Alex Deucher (alexdeuc...@gmail.com) ---
Created attachment 301243
--> https://bugzilla.kernel.org/attachment.cgi?id=301243&action=edit
patch 1/4
Can you try this patch set instead?
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https://bugzilla.kernel.org/show_bug.cgi?id=216119
--- Comment #14 from Alex Deucher (alexdeuc...@gmail.com) ---
Created attachment 301244
--> https://bugzilla.kernel.org/attachment.cgi?id=301244&action=edit
patch 2/4
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https://bugzilla.kernel.org/show_bug.cgi?id=216119
--- Comment #15 from Alex Deucher (alexdeuc...@gmail.com) ---
Created attachment 301245
--> https://bugzilla.kernel.org/attachment.cgi?id=301245&action=edit
patch 3/4
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--- Comment #16 from Alex Deucher (alexdeuc...@gmail.com) ---
Created attachment 301246
--> https://bugzilla.kernel.org/attachment.cgi?id=301246&action=edit
patch 4/4
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Hi Yunfei,
Le samedi 18 juin 2022 à 15:29 +0800, Yunfei Dong a écrit :
> Need to get dec_capability from scp first, then initialize decoder
> supported format and other parameters according to dec_capability value.
Perhaps something to improve in the future. On top of describing the fix, it
could
Applied. Thanks!
On Tue, Jun 21, 2022 at 9:17 AM Jiang Jian wrote:
>
> there is an unexpected word "the" in the comments that need to be dropped
>
> file: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> line: 57
> * the kernel tells the the ring what VMID to use for that command
> changed to
> * th
>drivers/gpu/drm/panfrost/panfrost_dump.c: In function 'panfrost_core_dump':
> >> drivers/gpu/drm/panfrost/panfrost_dump.c:115:20: error: 'struct
> >> panfrost_job' has no member named 'file_priv'
> 115 | as_nr = job->file_priv->mmu->as;
> |^~
FWIW --
On Tue, Jun 21, 2022 at 09:35:16AM +0100, Tvrtko Ursulin wrote:
On 20/06/2022 17:29, Niranjana Vishwanathapura wrote:
On Mon, Jun 20, 2022 at 11:43:10AM +0100, Tvrtko Ursulin wrote:
Hi,
On 17/06/2022 06:14, Niranjana Vishwanathapura wrote:
VM_BIND design document with description of intende
Le mercredi 15 juin 2022 à 19:33 +0800, yunfei.d...@mediatek.com a écrit :
> Hi Nicolas,
>
> Thanks for your comments.
> On Mon, 2022-06-13 at 16:08 -0400, Nicolas Dufresne wrote:
> > Le jeudi 12 mai 2022 à 11:46 +0800, Yunfei Dong a écrit :
> > > Add h264 decode driver to support mt8186. For the
Le mercredi 15 juin 2022 à 19:37 +0800, yunfei.d...@mediatek.com a écrit :
> Hi Nicolas,
>
> Thanks for your comments.
> On Mon, 2022-06-13 at 16:10 -0400, Nicolas Dufresne wrote:
> > >
>
> > Le jeudi 12 mai 2022 à 11:46 +0800, Yunfei Dong a écrit :
> > > Firstly, add mt8186 compatible and priva
From: Mikko Perttunen
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/falcon.c |
From: Mikko Perttunen
Add schema information for specifying context stream IDs. This uses
the standard iommu-map property.
Signed-off-by: Mikko Perttunen
Reviewed-by: Robin Murphy
Acked-by: Rob Herring
---
v3:
* New patch
v4:
* Remove memory-contexts subnode.
---
.../bindings/display/tegra/n
From: Mikko Perttunen
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen
---
v2:
* Directly set DMA mask instead of inheriting from Host1x.
* Use iommu-map instead of custom DT property.
v4:
* Use u64 instead of dm
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